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phy: rockchip-naneng-combo: Support rk3562

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Change-Id: I4da12613bb01c477f8fca9c38c516f5dab0851d9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2022-12-01 20:38:15 +08:00
committed by Tao Huang
parent 63f30f7541
commit 0cdb526c1f
1 changed files with 189 additions and 0 deletions
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189
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -561,6 +561,191 @@ static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
.combphy_cfg = rk3528_combphy_cfg,
};
static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
struct clk *refclk = NULL;
unsigned long rate;
int i;
u32 val;
/* Configure PHY reference clock frequency */
for (i = 0; i < priv->num_clks; i++) {
if (!strncmp(priv->clks[i].id, "refclk", 6)) {
refclk = priv->clks[i].clk;
break;
}
}
if (!refclk) {
dev_err(priv->dev, "No refclk found\n");
return -EINVAL;
}
switch (priv->mode) {
case PHY_TYPE_PCIE:
/* Set SSC downward spread spectrum */
val = readl(priv->mmio + (0x1f << 2));
val &= ~GENMASK(5, 4);
val |= 0x01 << 4;
writel(val, priv->mmio + 0x7c);
param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
break;
case PHY_TYPE_USB3:
/* Set SSC downward spread spectrum */
val = readl(priv->mmio + (0x1f << 2));
val &= ~GENMASK(5, 4);
val |= 0x01 << 4;
writel(val, priv->mmio + 0x7c);
/* Enable adaptive CTLE for USB3.0 Rx */
val = readl(priv->mmio + (0x0e << 2));
val &= ~GENMASK(0, 0);
val |= 0x01;
writel(val, priv->mmio + (0x0e << 2));
/* Set PLL KVCO fine tuning signals */
val = readl(priv->mmio + (0x20 << 2));
val &= ~(0x7 << 2);
val |= 0x2 << 2;
writel(val, priv->mmio + (0x20 << 2));
/* Set PLL LPF R1 to su_trim[10:7]=1001 */
writel(0x4, priv->mmio + (0xb << 2));
/* Set PLL input clock divider 1/2 */
val = readl(priv->mmio + (0x5 << 2));
val &= ~(0x3 << 6);
val |= 0x1 << 6;
writel(val, priv->mmio + (0x5 << 2));
/* Set PLL loop divider */
writel(0x32, priv->mmio + (0x11 << 2));
/* Set PLL KVCO to min and set PLL charge pump current to max */
writel(0xf0, priv->mmio + (0xa << 2));
param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
break;
default:
dev_err(priv->dev, "incompatible PHY type\n");
return -EINVAL;
}
rate = clk_get_rate(refclk);
switch (rate) {
case 24000000:
if (priv->mode == PHY_TYPE_USB3) {
/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
val = readl(priv->mmio + (0x0e << 2));
val &= ~GENMASK(7, 6);
val |= 0x01 << 6;
writel(val, priv->mmio + (0x0e << 2));
val = readl(priv->mmio + (0x0f << 2));
val &= ~GENMASK(7, 0);
val |= 0x5f;
writel(val, priv->mmio + (0x0f << 2));
}
break;
case 25000000:
param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
break;
case 100000000:
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->mode == PHY_TYPE_PCIE) {
/* PLL KVCO tuning fine */
val = readl(priv->mmio + (0x20 << 2));
val &= ~(0x7 << 2);
val |= 0x2 << 2;
writel(val, priv->mmio + (0x20 << 2));
/* Enable controlling random jitter, aka RMJ */
writel(0x4, priv->mmio + (0xb << 2));
val = readl(priv->mmio + (0x5 << 2));
val &= ~(0x3 << 6);
val |= 0x1 << 6;
writel(val, priv->mmio + (0x5 << 2));
writel(0x32, priv->mmio + (0x11 << 2));
writel(0xf0, priv->mmio + (0xa << 2));
}
break;
default:
dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
return -EINVAL;
}
if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
val = readl(priv->mmio + (0xc << 2));
val |= 0x3 << 4 | 0x1 << 7;
writel(val, priv->mmio + (0xc << 2));
val = readl(priv->mmio + (0xd << 2));
val |= 0x1;
writel(val, priv->mmio + (0xd << 2));
}
}
if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
val = readl(priv->mmio + (0x7 << 2));
val |= BIT(4);
writel(val, priv->mmio + (0x7 << 2));
}
return 0;
}
static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
/* pipe-phy-grf */
.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
.pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
.pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
.pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
/* peri-grf */
.u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 },
};
static const struct clk_bulk_data rk3562_clks[] = {
{ .id = "refclk" },
{ .id = "apbclk" },
{ .id = "pipe_clk" },
};
static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
.num_clks = ARRAY_SIZE(rk3562_clks),
.clks = rk3562_clks,
.grfcfg = &rk3562_combphy_grfcfgs,
.combphy_cfg = rk3562_combphy_cfg,
.force_det_out = true,
};
static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -1061,6 +1246,10 @@ static const struct of_device_id rockchip_combphy_of_match[] = {
.compatible = "rockchip,rk3528-naneng-combphy",
.data = &rk3528_combphy_cfgs,
},
{
.compatible = "rockchip,rk3562-naneng-combphy",
.data = &rk3562_combphy_cfgs,
},
{
.compatible = "rockchip,rk3568-naneng-combphy",
.data = &rk3568_combphy_cfgs,