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clk: rockchip: rk3228: export hdmiphy clock

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Change-Id: Ib7acd4c2f576ad320e069ab2bd9137156062e2d9
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
WeiYong Bi
2017-06-06 08:32:54 +08:00
committed by Tao Huang
parent 0e5ae6bda6
commit 0de87ca269
2 changed files with 2 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3228.c
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@@ -254,7 +254,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(4), 0, GFLAGS),
/* PD_MISC */
MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
RK2928_MISC_CON, 13, 1, MFLAGS),
MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
RK2928_MISC_CON, 14, 1, MFLAGS),

1
include/dt-bindings/clock/rk3228-cru.h
View File

@@ -77,6 +77,7 @@
/* dclk gates */
#define DCLK_VOP 190
#define DCLK_HDMI_PHY 191
#define HDMIPHY 192
/* aclk gates */
#define ACLK_DMAC 194