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arm64: dts: rockchip: rk3588s: add spi node

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Change-Id: I4e72251952f5aae5b9588c4c5cb00de4f70b7ae1
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2021-09-02 10:23:39 +08:00
committed by Tao Huang
parent abdc763b77
commit 0e542bf348
2 changed files with 260 additions and 0 deletions
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175
arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
View File

@@ -3719,4 +3719,179 @@
<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
spi0-hs {
/omit-if-no-ref/
spi0m0_pins_hs: spi0m0-pins {
rockchip,pins =
/* spi0_clk_m0 */
<0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
/* spi0_miso_m0 */
<0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
/* spi0_mosi_m0 */
<0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi0m1_pins_hs: spi0m1-pins {
rockchip,pins =
/* spi0_clk_m1 */
<4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
/* spi0_miso_m1 */
<4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
/* spi0_mosi_m1 */
<4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi0m2_pins_hs: spi0m2-pins {
rockchip,pins =
/* spi0_clk_m2 */
<1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
/* spi0_miso_m2 */
<1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
/* spi0_mosi_m2 */
<1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi0m3_pins_hs: spi0m3-pins {
rockchip,pins =
/* spi0_clk_m3 */
<3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
/* spi0_miso_m3 */
<3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
/* spi0_mosi_m3 */
<3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
};
};
spi1-hs {
/omit-if-no-ref/
spi1m1_pins_hs: spi1m1-pins {
rockchip,pins =
/* spi1_clk_m1 */
<3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
/* spi1_miso_m1 */
<3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
/* spi1_mosi_m1 */
<3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi1m2_pins_hs: spi1m2-pins {
rockchip,pins =
/* spi1_clk_m2 */
<1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
/* spi1_miso_m2 */
<1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
/* spi1_mosi_m2 */
<1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
};
};
spi2-hs {
/omit-if-no-ref/
spi2m0_pins_hs: spi2m0-pins {
rockchip,pins =
/* spi2_clk_m0 */
<1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
/* spi2_miso_m0 */
<1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
/* spi2_mosi_m0 */
<1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi2m1_pins_hs: spi2m1-pins {
rockchip,pins =
/* spi2_clk_m1 */
<4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
/* spi2_miso_m1 */
<4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
/* spi2_mosi_m1 */
<4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi2m2_pins_hs: spi2m2-pins {
rockchip,pins =
/* spi2_clk_m2 */
<0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
/* spi2_miso_m2 */
<0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
/* spi2_mosi_m2 */
<0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
};
};
spi3-hs {
/omit-if-no-ref/
spi3m1_pins_hs: spi3m1-pins {
rockchip,pins =
/* spi3_clk_m1 */
<4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
/* spi3_miso_m1 */
<4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
/* spi3_mosi_m1 */
<4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi3m2_pins_hs: spi3m2-pins {
rockchip,pins =
/* spi3_clk_m2 */
<0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
/* spi3_miso_m2 */
<0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
/* spi3_mosi_m2 */
<0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi3m3_pins_hs: spi3m3-pins {
rockchip,pins =
/* spi3_clk_m3 */
<3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
/* spi3_miso_m3 */
<3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
/* spi3_mosi_m3 */
<3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
};
};
spi4-hs {
/omit-if-no-ref/
spi4m0_pins_hs: spi4m0-pins {
rockchip,pins =
/* spi4_clk_m0 */
<1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
/* spi4_miso_m0 */
<1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
/* spi4_mosi_m0 */
<1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi4m1_pins_hs: spi4m1-pins {
rockchip,pins =
/* spi4_clk_m1 */
<3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
/* spi4_miso_m1 */
<3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
/* spi4_mosi_m1 */
<3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
};
/omit-if-no-ref/
spi4m2_pins_hs: spi4m2-pins {
rockchip,pins =
/* spi4_clk_m2 */
<1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
/* spi4_miso_m2 */
<1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
/* spi4_mosi_m2 */
<1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
};
};
};

85
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -33,6 +33,11 @@
serial7 = &uart7;
serial8 = &uart8;
serial9 = &uart9;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &spi4;
};
cpus {
@@ -1350,6 +1355,70 @@
status = "disabled";
};
spi0: spi@feb00000 {
compatible = "rockchip,rk3066-spi";
reg = <0x0 0xfeb00000 0x0 0x1000>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac0 14>, <&dmac0 15>;
dma-names = "tx", "rx";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
status = "disabled";
};
spi1: spi@feb10000 {
compatible = "rockchip,rk3066-spi";
reg = <0x0 0xfeb10000 0x0 0x1000>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac0 16>, <&dmac0 17>;
dma-names = "tx", "rx";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
pinctrl-1 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins_hs>;
status = "disabled";
};
spi2: spi@feb20000 {
compatible = "rockchip,rk3066-spi";
reg = <0x0 0xfeb20000 0x0 0x1000>;
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac1 15>, <&dmac1 16>;
dma-names = "tx", "rx";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>;
status = "disabled";
};
spi3: spi@feb30000 {
compatible = "rockchip,rk3066-spi";
reg = <0x0 0xfeb30000 0x0 0x1000>;
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac1 17>, <&dmac1 18>;
dma-names = "tx", "rx";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
pinctrl-1 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins_hs>;
status = "disabled";
};
uart1: serial@feb40000 {
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
reg = <0x0 0xfeb40000 0x0 0x100>;
@@ -1646,6 +1715,22 @@
status = "disabled";
};
spi4: spi@fecb0000 {
compatible = "rockchip,rk3066-spi";
reg = <0x0 0xfecb0000 0x0 0x1000>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac2 13>, <&dmac2 14>;
dma-names = "tx", "rx";
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
pinctrl-1 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins_hs>;
status = "disabled";
};
otp: otp@fecc0000 {
compatible = "rockchip,rk3588-otp";
reg = <0x0 0xfecc0000 0x0 0x400>;