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clk: clock: Fix PCIE100M clock output some corner chip swing small issue

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PD#170610: clock: Fix PCIE100M clock output

Change-Id: I8ada918f6910b537374115260ebaea7a4489e9d6
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
This commit is contained in:
Shunzhou Jiang
2018-07-25 16:42:42 +08:00
committed by Yixun Lan
parent 63585c7993
commit 0e7db6285c
1 changed files with 2 additions and 2 deletions
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4
drivers/amlogic/clk/g12a/g12a_clk-pll.c
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@@ -61,8 +61,8 @@
#define G12A_PCIE_PLL_CNTL3 0x10058e00
#define G12A_PCIE_PLL_CNTL4 0x000100c0
#define G12A_PCIE_PLL_CNTL4_ 0x008100c0
#define G12A_PCIE_PLL_CNTL5 0x28000048
#define G12A_PCIE_PLL_CNTL5_ 0x28000068
#define G12A_PCIE_PLL_CNTL5 0x68000048
#define G12A_PCIE_PLL_CNTL5_ 0x68000068
#define G12A_SYS_PLL_CNTL1 0x00000000
#define G12A_SYS_PLL_CNTL2 0x00000000