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rk3036:update rk312x.dtsi with iommu and gpu

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xxm
2014-07-23 13:41:30 +08:00
parent 1f58780f1d
commit 0ea7f1bb3f
1 changed files with 66 additions and 0 deletions
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66
arch/arm/boot/dts/rk312x.dtsi
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@@ -207,6 +207,38 @@
/* rockchip,clocks-uboot-has-init =
<&aclk_vio1>;*/
};
gpu {
compatible = "arm,mali400";
reg = <0x10091000 0x200>,
<0x10090000 0x100>,
<0x10093000 0x100>,
<0x10098000 0x1100>,
<0x10094000 0x100>;
<0x1009A000 0x1100>,
<0x10095000 0x100>;
reg-names = "Mali_L2",
"Mali_GP",
"Mali_GP_MMU",
"Mali_PP0",
"Mali_PP0_MMU",
"Mali_PP1",
"Mali_PP1_MMU";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "Mali_GP_IRQ",
"Mali_GP_MMU_IRQ",
"Mali_PP0_IRQ",
"Mali_PP0_MMU_IRQ";
"Mali_PP1_IRQ",
"Mali_PP1_MMU_IRQ";
};
clocks-enable {
compatible = "rockchip,clocks-enable";
@@ -485,4 +517,38 @@
clock-names = "aclk_iep", "hclk_iep";
status = "okay";
};
vop_mmu {
dbgname = "vop";
compatible = "iommu,vop_mmu";
reg = <0x1010e300 0x100>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
};
hevc_mmu {
dbgname = "hevc";
compatible = "iommu,hevc_mmu";
reg = <0x10104440 0x100>,
<0x10104480 0x100>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
};
vpu_mmu {
dbgname = "vpu";
compatible = "iommu,vpu_mmu";
reg = <0x10104800 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
};
iep_mmu {
dbgname = "iep";
compatible = "iommu,iep_mmu";
reg = <0x10108800 0x100>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
};
};