shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

video/rockchip: rga2 && rga add debug nod and some auto check case and combine rga version

Browse Source 
add rga debug node rga1: d/rga_debug/rga rga2: d/rga2_debug/rga2
auto check case :align check,scale check,memory check.
combine rga version from kernel 3.1 and 4.4 into one version by macro definition.

Change-Id: I97f7d9c670f81ae13768029126f7dbd6976c79f1
Signed-off-by: Shixiang Zheng <shixiang.zheng@rock-chips.com>
This commit is contained in:
Shixiang Zheng
2018-10-01 20:02:52 +08:00
committed by Tao Huang
parent 93bdae5de9
commit 0fb4dd2ca8
9 changed files with 2169 additions and 338 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/video/rockchip/rga/rga.h
View File

@@ -26,7 +26,7 @@
#define rgaNO_ERROR(status) (status >= 0)
#define rgaIS_SUCCESS(status) (status == 0)
#define RGA_DEBUGFS 1
/* RGA process mode enum */
enum

1184
drivers/video/rockchip/rga/rga_drv.c
View File

File diff suppressed because it is too large Load Diff

90
drivers/video/rockchip/rga/rga_mmu_info.c
View File

@@ -23,6 +23,10 @@
extern rga_service_info rga_service;
extern struct rga_mmu_buf_t rga_mmu_buf;
#if RGA_DEBUGFS
extern int RGA_CHECK_MODE;
#endif
#define KERNEL_SPACE_VALID 0xc0000000
@@ -244,6 +248,72 @@ static int rga_buf_size_cal(unsigned long yrgb_addr, unsigned long uv_addr, unsi
return pageCount;
}
#if RGA_DEBUGFS
static int rga_usermemory_cheeck(struct page **pages, u32 w, u32 h, u32 format, int flag)
{
int bits;
void *vaddr = NULL;
int taipage_num;
int taidata_num;
int *tai_vaddr = NULL;
switch (format) {
case RK_FORMAT_RGBA_8888:
case RK_FORMAT_RGBX_8888:
case RK_FORMAT_BGRA_8888:
bits = 32;
break;
case RK_FORMAT_RGB_888:
case RK_FORMAT_BGR_888:
bits = 24;
break;
case RK_FORMAT_RGB_565:
case RK_FORMAT_RGBA_5551:
case RK_FORMAT_RGBA_4444:
case RK_FORMAT_YCbCr_422_SP:
case RK_FORMAT_YCbCr_422_P:
case RK_FORMAT_YCrCb_422_SP:
case RK_FORMAT_YCrCb_422_P:
bits = 16;
break;
case RK_FORMAT_YCbCr_420_SP:
case RK_FORMAT_YCbCr_420_P:
case RK_FORMAT_YCrCb_420_SP:
case RK_FORMAT_YCrCb_420_P:
bits = 12;
break;
case RK_FORMAT_YCbCr_420_SP_10B:
case RK_FORMAT_YCrCb_420_SP_10B:
bits = 15;
break;
default:
printk(KERN_DEBUG "un know format\n");
return -1;
}
taipage_num = w * h * bits / 8 / (1024 * 4);
taidata_num = w * h * bits / 8 % (1024 * 4);
if (taidata_num == 0) {
vaddr = kmap(pages[taipage_num - 1]);
tai_vaddr = (int *)vaddr + 1023;
} else {
vaddr = kmap(pages[taipage_num]);
tai_vaddr = (int *)vaddr + taidata_num / 4 - 1;
}
if (flag == 1) {
printk(KERN_DEBUG "src user memory check\n");
printk(KERN_DEBUG "tai data is %d\n", *tai_vaddr);
} else {
printk(KERN_DEBUG "dst user memory check\n");
printk(KERN_DEBUG "tai data is %d\n", *tai_vaddr);
}
if (taidata_num == 0)
kunmap(pages[taipage_num - 1]);
else
kunmap(pages[taipage_num]);
return 0;
}
#endif
static int rga_MapUserMemory(struct page **pages,
uint32_t *pageTable,
unsigned long Memory,
@@ -528,7 +598,13 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req)
pr_err("rga map src memory failed\n");
status = ret;
break;
}
}
#if RGA_DEBUGFS
if (RGA_CHECK_MODE)
rga_usermemory_cheeck(&pages[0], req->src.vir_w,
req->src.vir_h, req->src.format, 1);
#endif
}
}
else {
@@ -555,6 +631,12 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req)
status = ret;
break;
}
#if RGA_DEBUGFS
if (RGA_CHECK_MODE)
rga_usermemory_cheeck(&pages[0], req->src.vir_w,
req->src.vir_h, req->src.format, 2);
#endif
}
}
else {
@@ -612,7 +694,7 @@ static int rga_mmu_info_color_palette_mode(struct rga_reg *reg, struct rga_req *
uint32_t AllSize;
uint32_t *MMU_Base = NULL, *MMU_Base_phys = NULL;
uint32_t *MMU_p;
int ret, status;
int ret, status = 0;
uint32_t stride;
uint8_t shift;
@@ -721,7 +803,7 @@ static int rga_mmu_info_color_palette_mode(struct rga_reg *reg, struct rga_req *
rga_mmu_buf_get(&rga_mmu_buf, AllSize + 16);
reg->MMU_len = AllSize + 16;
return status;
return status;
}
while(0);
@@ -1108,7 +1190,7 @@ static int rga_mmu_info_update_patten_buff_mode(struct rga_reg *reg, struct rga_
}
MMU_Base = kzalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
if(pages == NULL) {
if(MMU_Base == NULL) {
pr_err("RGA MMU malloc MMU_Base point failed\n");
status = RGA_MALLOC_ERROR;
break;

70
drivers/video/rockchip/rga/rga_reg_info.c
View File

@@ -31,6 +31,7 @@
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/wakelock.h>
#include <linux/version.h>
#include "rga_reg_info.h"
#include "rga_rop.h"
@@ -92,7 +93,7 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
void
static void
dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile)
{
u32 width = msg->dst.act_w;
@@ -286,7 +287,7 @@ Date:
20012-2-2 10:59:25
**************************************************************/
void
static void
src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile)
{
s32 x0, x1, x2, x3, y0, y1, y2, y3;
@@ -438,7 +439,7 @@ Date:
20012-2-2 10:59:25
**************************************************************/
void
static void
RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_MODE_CTL;
@@ -562,7 +563,7 @@ Date:
20012-2-2 10:59:25
**************************************************************/
void
static void
RGA_set_src(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_SRC_VIR_INFO;
@@ -670,8 +671,8 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
static s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_DST_MST;
u32 *bRGA_DST_UV_MST;
@@ -702,9 +703,8 @@ s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
*bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (y_off * stride) + (x_off * pw);
*bRGA_DST_UV_MST = 0;
*bRGA_YUV_OUT_CFG = 0;
*bRGA_DST_UV_MST = 0;
*bRGA_YUV_OUT_CFG = 0;
if (msg->rotate_mode == 1) {
if (msg->sina == 65536 && msg->cosa == 0) {
/* rotate 90 */
@@ -777,11 +777,11 @@ s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
*bRGA_DST_VIR_INFO = reg;
*bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
if (msg->render_mode == pre_scaling_mode) {
*bRGA_YUV_OUT_CFG &= 0xfffffffe;
}
#endif
return 0;
}
@@ -796,7 +796,7 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
void
static void
RGA_set_alpha_rop(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_ALPHA_CON;
@@ -857,8 +857,8 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
void
static void
RGA_set_color(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_SRC_TR_COLOR0;
@@ -891,8 +891,8 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
s32
static s32
RGA_set_fading(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_FADING_CON;
@@ -923,8 +923,8 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
s32
static s32
RGA_set_pat(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_PAT_CON;
@@ -956,8 +956,8 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
void
static void
RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile)
{
u32 *bRGA_SRC_Y_MST;
@@ -1141,8 +1141,8 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
void
static void
RGA_set_color_palette_reg_info(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_SRC_Y_MST;
@@ -1178,7 +1178,7 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
void
static void
RGA_set_color_fill_reg_info(u8 *base, const struct rga_req *msg)
{
@@ -1216,8 +1216,8 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg)
static s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_LINE_DRAW;
u32 *bRGA_DST_VIR_INFO;
@@ -1321,9 +1321,9 @@ s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg)
}
/*full*/
s32
RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg)
/*full*/
static s32
RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_BLUR_SHARP_INFO;
u32 reg = 0;
@@ -1342,7 +1342,7 @@ RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg)
/*full*/
s32
static s32
RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_PRE_SCALE_INFO;
@@ -1405,8 +1405,8 @@ RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg)
/*full*/
int
/*full*/
static int
RGA_set_update_palette_table_reg_info(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_LUT_MST;
@@ -1424,8 +1424,8 @@ RGA_set_update_palette_table_reg_info(u8 *base, const struct rga_req *msg)
/*full*/
int
/*full*/
static int
RGA_set_update_patten_buff_reg_info(u8 *base, const struct rga_req *msg)
{
u32 *bRGA_PAT_MST;
@@ -1467,8 +1467,8 @@ Author:
Date:
20012-2-2 10:59:25
**************************************************************/
s32
static s32
RGA_set_mmu_ctrl_reg_info(u8 *base, const struct rga_req *msg)
{
u32 *RGA_MMU_TLB, *RGA_MMU_CTRL_ADDR;

4
drivers/video/rockchip/rga2/rga2.h
View File

@@ -702,9 +702,7 @@ struct rga2_service_info {
};
#define RGA2_TEST_CASE 0
#define RGA2_TEST 0
#define RGA2_TEST_MSG 0
#define RGA2_TEST_TIME 0
#define RGA2_DEBUGFS 1
//General Registers
#define RGA2_SYS_CTRL 0x000

1032
drivers/video/rockchip/rga2/rga2_drv.c
View File

File diff suppressed because it is too large Load Diff

101
drivers/video/rockchip/rga2/rga2_mmu_info.c
View File

@@ -20,7 +20,9 @@
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include "rga2_mmu_info.h"
#if RGA2_DEBUGFS
extern int RGA2_CHECK_MODE;
#endif
extern struct rga2_service_info rga2_service;
extern struct rga2_mmu_buf_t rga2_mmu_buf;
@@ -290,6 +292,78 @@ static int rga2_buf_size_cal(unsigned long yrgb_addr, unsigned long uv_addr, uns
return pageCount;
}
#if RGA2_DEBUGFS
static int rga2_UserMemory_cheeck(struct page **pages, u32 w, u32 h, u32 format, int flag)
{
int bits;
void *vaddr = NULL;
int taipage_num;
int taidata_num;
int *tai_vaddr = NULL;
switch (format) {
case RGA2_FORMAT_RGBA_8888:
case RGA2_FORMAT_RGBX_8888:
case RGA2_FORMAT_BGRA_8888:
case RGA2_FORMAT_BGRX_8888:
bits = 32;
break;
case RGA2_FORMAT_RGB_888:
case RGA2_FORMAT_BGR_888:
bits = 24;
break;
case RGA2_FORMAT_RGB_565:
case RGA2_FORMAT_RGBA_5551:
case RGA2_FORMAT_RGBA_4444:
case RGA2_FORMAT_BGR_565:
case RGA2_FORMAT_YCbCr_422_SP:
case RGA2_FORMAT_YCbCr_422_P:
case RGA2_FORMAT_YCrCb_422_SP:
case RGA2_FORMAT_YCrCb_422_P:
case RGA2_FORMAT_BGRA_5551:
case RGA2_FORMAT_BGRA_4444:
bits = 16;
break;
case RGA2_FORMAT_YCbCr_420_SP:
case RGA2_FORMAT_YCbCr_420_P:
case RGA2_FORMAT_YCrCb_420_SP:
case RGA2_FORMAT_YCrCb_420_P:
bits = 12;
break;
case RGA2_FORMAT_YCbCr_420_SP_10B:
case RGA2_FORMAT_YCrCb_420_SP_10B:
case RGA2_FORMAT_YCbCr_422_SP_10B:
case RGA2_FORMAT_YCrCb_422_SP_10B:
bits = 15;
break;
default:
printk("un know format\n");
return -1;
}
taipage_num = w * h * bits / 8 / (1024 * 4);
taidata_num = w * h * bits / 8 % (1024 * 4);
if (taidata_num == 0) {
vaddr = kmap(pages[taipage_num - 1]);
tai_vaddr = (int *)vaddr + 1023;
} else {
vaddr = kmap(pages[taipage_num]);
tai_vaddr = (int *)vaddr + taidata_num / 4 - 1;
}
if (flag == 1) {
printk(KERN_DEBUG "src user memory check\n");
printk(KERN_DEBUG "tai data is %d\n", *tai_vaddr);
} else {
printk(KERN_DEBUG "dst user memory check\n");
printk(KERN_DEBUG "tai data is %d\n", *tai_vaddr);
}
if (taidata_num == 0)
kunmap(pages[taipage_num - 1]);
else
kunmap(pages[taipage_num]);
return 0;
}
#endif
static int rga2_MapUserMemory(struct page **pages, uint32_t *pageTable,
unsigned long Memory, uint32_t pageCount,
int writeFlag)
@@ -438,6 +512,9 @@ static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req)
Src0PageCount = 0;
Src1PageCount = 0;
DstPageCount = 0;
Src0Start = 0;
Src1Start = 0;
DstStart = 0;
/* cal src0 buf mmu info */
if (req->mmu_info.src0_mmu_flag & 1) {
@@ -497,12 +574,19 @@ static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req)
(rga2_mmu_buf.front & (rga2_mmu_buf.size - 1));
mutex_unlock(&rga2_service.lock);
if (Src0MemSize) {
if (req->sg_src0)
if (req->sg_src0) {
ret = rga2_MapION(req->sg_src0,
&MMU_Base[0], Src0MemSize);
else
} else {
ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0],
Src0Start, Src0PageCount, 0);
#if RGA2_DEBUGFS
if (RGA2_CHECK_MODE)
rga2_UserMemory_cheeck(&pages[0], req->src.vir_w,
req->src.vir_h, req->src.format,
1);
#endif
}
if (ret < 0) {
pr_err("rga2 map src0 memory failed\n");
@@ -541,13 +625,20 @@ static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req)
req->src1.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK));
}
if (DstMemSize) {
if (req->sg_dst)
if (req->sg_dst) {
ret = rga2_MapION(req->sg_dst, MMU_Base + Src0MemSize
+ Src1MemSize, DstMemSize);
else
} else {
ret = rga2_MapUserMemory(&pages[0], MMU_Base
+ Src0MemSize + Src1MemSize,
DstStart, DstPageCount, 1);
#if RGA2_DEBUGFS
if (RGA2_CHECK_MODE)
rga2_UserMemory_cheeck(&pages[0], req->src.vir_w,
req->src.vir_h, req->src.format,
2);
#endif
}
if (ret < 0) {
pr_err("rga2 map dst memory failed\n");
status = ret;

22
drivers/video/rockchip/rga2/rga2_reg_info.c
View File

@@ -29,14 +29,13 @@
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/wakelock.h>
#include <linux/version.h>
#include "rga2_reg_info.h"
#include "../rga/rga_type.h"
//#include "../rga/rga_rop.h"
#include "rga2_type.h"
#include "rga2_rop.h"
#include "rga2.h"
extern unsigned int rga2_ROP3_code[256];
static void RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
{
RK_U32 *bRGA_SRC_INFO;
@@ -632,14 +631,14 @@ static void RGA2_set_reg_rop_info(u8 *base, struct rga2_req *msg)
bRGA_PAT_CON = (RK_U32 *)(base + RGA2_PAT_CON_OFFSET);
if(msg->rop_mode == 0) {
rop_code0 = rga2_ROP3_code[(msg->rop_code & 0xff)];
rop_code0 = RGA2_ROP3_code[(msg->rop_code & 0xff)];
}
else if(msg->rop_mode == 1) {
rop_code0 = rga2_ROP3_code[(msg->rop_code & 0xff)];
rop_code0 = RGA2_ROP3_code[(msg->rop_code & 0xff)];
}
else if(msg->rop_mode == 2) {
rop_code0 = rga2_ROP3_code[(msg->rop_code & 0xff)];
rop_code1 = rga2_ROP3_code[(msg->rop_code & 0xff00)>>8];
rop_code0 = RGA2_ROP3_code[(msg->rop_code & 0xff)];
rop_code1 = RGA2_ROP3_code[(msg->rop_code & 0xff00)>>8];
}
*bRGA_ROP_CTRL0 = rop_code0;
@@ -965,11 +964,12 @@ static void format_name_convert(uint32_t *df, uint32_t sf)
void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req)
{
u16 alpha_mode_0, alpha_mode_1;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
if (req_rga->render_mode & RGA_BUF_GEM_TYPE_MASK)
req->buf_type = RGA_BUF_GEM_TYPE_MASK & RGA_BUF_GEM_TYPE_DMA;
req_rga->render_mode &= (~RGA_BUF_GEM_TYPE_MASK);
#endif
if (req_rga->render_mode == 6)
req->render_mode = update_palette_table_mode;
@@ -1188,12 +1188,12 @@ static void memcpy_img_info(struct rga_img_info_t *dst, struct rga_img_info_32_t
void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req)
{
u16 alpha_mode_0, alpha_mode_1;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
if (req_rga->render_mode & RGA_BUF_GEM_TYPE_MASK)
req->buf_type = RGA_BUF_GEM_TYPE_MASK & RGA_BUF_GEM_TYPE_DMA;
req_rga->render_mode &= (~RGA_BUF_GEM_TYPE_MASK);
#endif
if (req_rga->render_mode == 6)
req->render_mode = update_palette_table_mode;
else if (req_rga->render_mode == 7)

2
drivers/video/rockchip/rga2/rga2_rop.h
View File

@@ -2,7 +2,7 @@
#ifndef __RGA_ROP_H__
#define __RGA_ROP_H__
unsigned int rga2_ROP3_code[256] =
unsigned int RGA2_ROP3_code[256] =
{
0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0
0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,