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osd: add mali-afbc decode error statistics
PD#165090: osd: add mali-afbc decode error statistics Change-Id: Idb3c37944d3a0ac48422ab901416279fc458b00b Signed-off-by: pengcheng chen <pengcheng.chen@amlogic.com>
This commit is contained in:
committed by
Yixun Lan
parent
4d33a9e50a
commit
101c8a57b2
@@ -719,6 +719,7 @@ struct hw_para_s {
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u32 hdr_used;
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u32 basic_urgent;
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u32 two_ports;
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u32 afbc_err_cnt;
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struct hw_debug_s osd_debug;
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int out_fence_fd;
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int in_fd[HW_OSD_COUNT];
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@@ -341,7 +341,8 @@ static void osd_debug_dump_register_all(void)
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}
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if (osd_hw.osd_meson_dev.cpu_id >= __MESON_CPU_MAJOR_ID_G12B) {
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if (osd_hw.osd_meson_dev.has_viu2) {
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if (osd_hw.osd_meson_dev.has_viu2 &&
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osd_hw.powered[OSD4]) {
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reg = VPP2_MISC;
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osd_log_info("reg[0x%x]: 0x%08x\n",
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reg, osd_reg_read(reg));
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@@ -2898,6 +2898,17 @@ static ssize_t store_osd_rotate(
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return count;
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}
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static ssize_t show_afbc_err_cnt(
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struct device *device, struct device_attribute *attr,
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char *buf)
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{
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u32 err_cnt;
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osd_get_afbc_err_cnt(&err_cnt);
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return snprintf(buf, PAGE_SIZE, "%d\n", err_cnt);
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}
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static inline int str2lower(char *str)
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{
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while (*str != '\0') {
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@@ -3102,7 +3113,8 @@ static struct device_attribute osd_attrs[] = {
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NULL, store_osd_single_step_mode),
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__ATTR(osd_single_step, 0220,
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NULL, store_osd_single_step),
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__ATTR(afbc_err_cnt, 0444,
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show_afbc_err_cnt, NULL),
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};
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static struct device_attribute osd_attrs_viu2[] = {
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@@ -1401,8 +1401,10 @@ static bool mali_afbc_get_error(void)
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status = VSYNCOSD_RD_MPEG_REG(VPU_MAFBC_IRQ_RAW_STATUS);
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if (status & 0x3c) {
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osd_log_dbg("afbc error happened\n");
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osd_hw.afbc_err_cnt++;
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error = true;
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}
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status = VSYNCOSD_WR_MPEG_REG(VPU_MAFBC_IRQ_CLEAR, 0x3f);
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return error;
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}
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static u32 osd_get_hw_reset_flag(void)
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@@ -1449,9 +1451,8 @@ static u32 osd_get_hw_reset_flag(void)
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if (afbc_enable &&
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osd_hw.afbc_force_reset)
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hw_reset_flag |= HW_RESET_MALI_AFBCD_REGS;
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if (afbc_enable &&
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osd_hw.afbc_status_err_reset &&
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mali_afbc_get_error())
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if (afbc_enable && mali_afbc_get_error() &&
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osd_hw.afbc_status_err_reset)
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hw_reset_flag |= HW_RESET_MALI_AFBCD_REGS;
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}
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break;
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@@ -2938,6 +2939,11 @@ void osd_set_rotate(u32 index, u32 osd_rotate)
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osd_wait_vsync_hw();
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}
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void osd_get_afbc_err_cnt(u32 *err_cnt)
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{
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*err_cnt = osd_hw.afbc_err_cnt;
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}
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int osd_get_capbility(u32 index)
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{
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u32 capbility = 0;
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@@ -4442,10 +4448,15 @@ static void osd_update_disp_osd_reverse(u32 index)
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remove_from_update_list(index, DISP_OSD_REVERSE);
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}
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static int get_viu2_src_format(void)
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{
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return RGBA;
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}
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static void osd_update_disp_osd_rotate(u32 index)
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{
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u32 rotate_en = osd_hw.osd_rotate[index];
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u32 src_fmt = RGBA;
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u32 src_fmt;
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u32 x_start, x_end, y_start, y_end;
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u32 src_width, src_height;
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u32 rot_hsize, blk_vsize, rd_blk_hsize;
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@@ -4459,6 +4470,7 @@ static void osd_update_disp_osd_rotate(u32 index)
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if (osd_hw.osd_meson_dev.cpu_id < __MESON_CPU_MAJOR_ID_G12B)
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return;
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src_fmt = get_viu2_src_format();
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src_data.x = 0;
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src_data.y = 0;
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src_data.w = osd_hw.fb_gem[index].xres;
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@@ -7331,6 +7343,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe,
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osd_hw.osd_deband_enable = 1;
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osd_hw.out_fence_fd = -1;
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osd_hw.blend_bypass = 0;
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osd_hw.afbc_err_cnt = 0;
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if (osd_hw.osd_meson_dev.osd_ver == OSD_SIMPLE) {
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data32 = osd_reg_read(
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hw_osd_reg_array[OSD1].osd_fifo_ctrl_stat);
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@@ -200,4 +200,5 @@ void osd_set_single_step(u32 osd_single_step);
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void output_save_info(void);
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void osd_get_rotate(u32 index, u32 *osd_rotate);
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void osd_set_rotate(u32 index, u32 osd_rotate);
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void osd_get_afbc_err_cnt(u32 *err_cnt);
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#endif
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@@ -342,7 +342,7 @@ static inline u32 is_rdma_reg(u32 addr)
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{
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u32 rdma_en = 1;
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if ((addr >= 0x1e10) && (addr <= 0x1e50))
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if ((addr >= VIU2_OSD1_CTRL_STAT) && (addr <= VIU2_OSD1_BLK3_CFG_W4))
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rdma_en = 0;
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else
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rdma_en = 1;
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