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drm/msm/a5xx: Always set an OPP supported hardware value

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[ Upstream commit 0478b4fc5f ]

If the opp table specifies opp-supported-hw as a property but the driver
has not set a supported hardware value the OPP subsystem will reject
all the table entries.

Set a "default" value that will match the default table entries but not
conflict with any possible real bin values. Also fix a small memory leak
and free the buffer allocated by nvmem_cell_read().

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Jordan Crouse
2020-02-14 11:36:44 -07:00
committed by Greg Kroah-Hartman
parent 45e618016a
commit 102bdec1d1
1 changed files with 20 additions and 7 deletions
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27
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
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@@ -1474,18 +1474,31 @@ static const struct adreno_gpu_funcs funcs = {
static void check_speed_bin(struct device *dev)
{
struct nvmem_cell *cell;
u32 bin, val;
u32 val;
/*
* If the OPP table specifies a opp-supported-hw property then we have
* to set something with dev_pm_opp_set_supported_hw() or the table
* doesn't get populated so pick an arbitrary value that should
* ensure the default frequencies are selected but not conflict with any
* actual bins
*/
val = 0x80;
cell = nvmem_cell_get(dev, "speed_bin");
/* If a nvmem cell isn't defined, nothing to do */
if (IS_ERR(cell))
return;
if (!IS_ERR(cell)) {
void *buf = nvmem_cell_read(cell, NULL);
bin = *((u32 *) nvmem_cell_read(cell, NULL));
nvmem_cell_put(cell);
if (!IS_ERR(buf)) {
u8 bin = *((u8 *) buf);
val = (1 << bin);
val = (1 << bin);
kfree(buf);
}
nvmem_cell_put(cell);
}
dev_pm_opp_set_supported_hw(dev, &val, 1);
}