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video: tegra: add utility function to compute framebuffer stride
framebuffers will generally not be exactly width * bpp / 8 bytes wide; on tegra, linearly-addressed framebuffers will generally be rounded up so that the stride is a multiple of 16B (so that they are compatible with rendering from the hardware engines), and tiled framebuffers will be a multiple of the tile width (64B). add a utility function to tegra_dc to compute the correct stride given a width, bpp and pixel layout, and use this in set_par. Change-Id: I803a55b49c12476f20d5644707899c3fe1336c2d Signed-off-by: Gary King <gking@nvidia.com>
This commit is contained in:
committed by
Rebecca Schultz Zavin
parent
93fa4f2a2d
commit
10c751b8f5
@@ -25,6 +25,15 @@
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#define TEGRA_MAX_DC 2
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#define DC_N_WINDOWS 3
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#define TEGRA_DC_PITCH_ATOM 16
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#define TEGRA_DC_TILED_ATOM 16
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enum tegra_win_layout {
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TEGRA_WIN_LAYOUT_PITCH,
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TEGRA_WIN_LAYOUT_TILED,
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TEGRA_WIN_LAYOUT_LINEAR_TILED,
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};
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struct tegra_dc_mode {
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int pclk;
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int h_ref_to_sync;
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@@ -95,6 +104,7 @@ struct tegra_dc_win {
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unsigned out_w;
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unsigned out_h;
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unsigned z;
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enum tegra_win_layout layout;
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int dirty;
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struct tegra_dc *dc;
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@@ -163,4 +173,7 @@ int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n);
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int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode);
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ssize_t tegra_dc_compute_stride(int xres, int bpp,
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enum tegra_win_layout layout);
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#endif
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@@ -325,6 +325,20 @@ struct tegra_dc *tegra_dc_get_dc(unsigned idx)
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}
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EXPORT_SYMBOL(tegra_dc_get_dc);
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ssize_t tegra_dc_compute_stride(int xres, int bpp, enum tegra_win_layout layout)
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{
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unsigned int raw_stride = (xres * bpp) / 8;
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unsigned int k, n = 0;
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if (layout == TEGRA_WIN_LAYOUT_PITCH)
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return ALIGN(raw_stride, TEGRA_DC_PITCH_ATOM);
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else if (layout == TEGRA_WIN_LAYOUT_TILED)
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return ALIGN(raw_stride, TEGRA_DC_TILED_ATOM);
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else
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return -EINVAL;
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}
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EXPORT_SYMBOL(tegra_dc_compute_stride);
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struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
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{
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if (win >= dc->n_windows)
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@@ -113,7 +113,10 @@ static int tegra_fb_set_par(struct fb_info *info)
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default:
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return -EINVAL;
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}
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info->fix.line_length = var->xres * var->bits_per_pixel / 8;
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info->fix.line_length = tegra_dc_compute_stride(var->xres,
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var->bits_per_pixel, TEGRA_WIN_LAYOUT_PITCH);
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tegra_fb->win->stride = info->fix.line_length;
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if (var->pixclock) {
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struct tegra_dc_mode mode;
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@@ -371,7 +374,9 @@ struct tegra_fb_info *tegra_fb_register(struct nvhost_device *ndev,
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win->z = 0;
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win->phys_addr = fb_phys;
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win->virt_addr = fb_base;
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win->stride = fb_data->xres * fb_data->bits_per_pixel / 8;
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win->layout = TEGRA_WIN_LAYOUT_PITCH;
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win->stride = tegra_dc_compute_stride(fb_data->xres,
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fb_data->bits_per_pixel, win->layout);
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win->flags = TEGRA_WIN_FLAG_ENABLED;
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if (fb_mem)
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