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audio: add clk tuning_enable/start_enable control in dts [1/1]

Browse Source 
PD#SWPL-8306

Problem:
speaker without audio on S400. sideeffect of SWPL-7680

Solution:
add control interface in dts to enable clk tuning
and start clk before codec init

Verify:
verify on S400

Change-Id: Ic9f4e7b13b7d4ced18852346cdc7cf5f48e510dc
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
This commit is contained in:
Zhe Wang
2019-05-14 14:14:11 +08:00
committed by Luke Go
parent 25c54d3ed0
commit 114b99730d
17 changed files with 161 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm/boot/dts/amlogic/sm1_s905d3_ac200.dts
View File

@@ -1124,6 +1124,12 @@
*/
samesource_sel = <3>;
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
@@ -1164,6 +1170,9 @@
pinctrl-names = "spdif_pins";
pinctrl-0 = <&spdifout &spdifin>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
spdifb: spdif@1 {

3
arch/arm/boot/dts/amlogic/sm1_s905d3_ac202.dts
View File

@@ -1269,6 +1269,9 @@
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
spdifb: spdif@1 {

9
arch/arm/boot/dts/amlogic/sm1_s905d3_skt.dts
View File

@@ -1122,6 +1122,12 @@
*/
samesource_sel = <3>;
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <0>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
@@ -1162,6 +1168,9 @@
pinctrl-names = "spdif_pins";
pinctrl-0 = <&spdifout &spdifin>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
spdifb: spdif@1 {

9
arch/arm/boot/dts/amlogic/sm1_s905x3_ac213.dts
View File

@@ -1117,6 +1117,12 @@
*/
samesource_sel = <3>;
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
@@ -1156,6 +1162,9 @@
pinctrl-names = "spdif_pins";
pinctrl-0 = <&spdifout &spdifin>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
spdifb: spdif@1 {

7
arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
View File

@@ -1298,6 +1298,11 @@
acodec_adc = <1>;
mclk_pad = <0>; /* 0: mclk_0; 1: mclk_1 */
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
/* !!!For --TV platform-- ONLY */
@@ -1430,6 +1435,8 @@
asrc_id = <0>;
auto_asrc = <0>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};

9
arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts
View File

@@ -991,6 +991,12 @@
acodec_adc = <1>;
mclk_pad = <0>; /* 0: mclk_0; 1: mclk_1 */
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
/* !!!For --TV platform-- ONLY */
@@ -1123,6 +1129,9 @@
asrc_id = <0>;
auto_asrc = <0>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};

7
arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
View File

@@ -1556,6 +1556,11 @@
acodec_adc = <1>;
mclk_pad = <0>; /* 0: mclk_0; 1: mclk_1 */
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
/* !!!For --TV platform-- ONLY */
@@ -1688,6 +1693,8 @@
asrc_id = <0>;
auto_asrc = <0>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};

9
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts
View File

@@ -1124,6 +1124,12 @@
*/
samesource_sel = <3>;
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
@@ -1164,6 +1170,9 @@
pinctrl-names = "spdif_pins";
pinctrl-0 = <&spdifout /* &spdifin */>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
spdifb: spdif@1 {

9
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac202.dts
View File

@@ -1173,6 +1173,12 @@
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
@@ -1265,6 +1271,9 @@
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
spdifb: spdif@1 {

3
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac202_1g.dts
View File

@@ -1266,6 +1266,9 @@
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
spdifb: spdif@1 {

9
arch/arm64/boot/dts/amlogic/sm1_s905d3_skt.dts
View File

@@ -1120,6 +1120,12 @@
*/
samesource_sel = <3>;
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <0>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
@@ -1160,6 +1166,9 @@
pinctrl-names = "spdif_pins";
pinctrl-0 = <&spdifout &spdifin>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
spdifb: spdif@1 {

9
arch/arm64/boot/dts/amlogic/sm1_s905x3_ac213.dts
View File

@@ -1194,6 +1194,12 @@
*/
samesource_sel = <3>;
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
@@ -1232,6 +1238,9 @@
pinctrl-names = "spdif_pins";
pinctrl-0 = <&spdifout &spdifin>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};
spdifb: spdif@1 {

7
arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
View File

@@ -1489,6 +1489,11 @@
acodec_adc = <1>;
mclk_pad = <0>; /* 0: mclk_0; 1: mclk_1 */
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
/* !!!For --TV platform-- ONLY */
@@ -1621,6 +1626,8 @@
asrc_id = <0>;
auto_asrc = <0>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};

7
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
View File

@@ -1364,6 +1364,11 @@
acodec_adc = <1>;
mclk_pad = <0>; /* 0: mclk_0; 1: mclk_1 */
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
/* !!!For --TV platform-- ONLY */
@@ -1496,6 +1501,8 @@
asrc_id = <0>;
auto_asrc = <0>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};

7
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
View File

@@ -1358,6 +1358,11 @@
acodec_adc = <1>;
mclk_pad = <0>; /* 0: mclk_0; 1: mclk_1 */
/*enable default mclk(12.288M), before extern codec start*/
start_clk_enable = <1>;
/*tdm clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
/* !!!For --TV platform-- ONLY */
@@ -1490,6 +1495,8 @@
asrc_id = <0>;
auto_asrc = <0>;
/*spdif clk tuning enable*/
clk_tuning_enable = <1>;
status = "okay";
};

20
sound/soc/amlogic/auge/spdif.c
View File

@@ -483,7 +483,9 @@ static const struct snd_kcontrol_new snd_spdif_controls[] = {
0, aml_get_hdmi_out_audio,
aml_set_hdmi_out_audio),
#endif
};
static const struct snd_kcontrol_new snd_spdif_clk_controls[] = {
SOC_SINGLE_EXT("SPDIF CLK Fine Setting",
0, 0, 2000000, 0,
spdif_clk_get,
@@ -1071,6 +1073,15 @@ static int aml_dai_spdif_probe(struct snd_soc_dai *cpu_dai)
pr_err("%s, failed add snd spdif controls\n", __func__);
}
if (p_spdif->clk_tuning_enable == 1) {
ret = snd_soc_add_dai_controls(cpu_dai,
snd_spdif_clk_controls,
ARRAY_SIZE(snd_spdif_clk_controls));
if (ret < 0)
pr_err("%s, failed add snd spdif clk controls\n",
__func__);
}
return 0;
}
@@ -1608,6 +1619,15 @@ static int aml_spdif_parse_of(struct platform_device *pdev)
return PTR_ERR(p_spdif->clk_spdifout);
}
ret = of_property_read_u32(pdev->dev.of_node,
"clk_tuning_enable",
&p_spdif->clk_tuning_enable);
if (ret < 0)
p_spdif->clk_tuning_enable = 0;
else
pr_info("Spdif id %d tuning clk enable:%d\n",
p_spdif->id, p_spdif->clk_tuning_enable);
return 0;
}

38
sound/soc/amlogic/auge/tdm.c
View File

@@ -209,21 +209,19 @@ static const struct soc_enum i2sin_clk_enum[] = {
i2sin_clk),
};
static const struct snd_kcontrol_new snd_tdm_controls[] = {
SOC_ENUM_EXT("I2SIn CLK", i2sin_clk_enum,
tdmin_clk_get,
NULL),
};
static const struct snd_kcontrol_new snd_tdm_clk_controls[] = {
SOC_SINGLE_EXT("TDM MCLK Fine Setting",
0, 0, 2000000, 0,
tdm_clk_get,
tdm_clk_set),
};
static irqreturn_t aml_tdm_ddr_isr(int irq, void *devid)
{
struct snd_pcm_substream *substream = (struct snd_pcm_substream *)devid;
@@ -1322,7 +1320,16 @@ static int aml_dai_tdm_probe(struct snd_soc_dai *cpu_dai)
ret = snd_soc_add_dai_controls(cpu_dai, snd_tdm_controls,
ARRAY_SIZE(snd_tdm_controls));
if (ret < 0)
pr_err("%s, failed add snd spdif controls\n", __func__);
pr_err("%s, failed add snd tdm controls\n", __func__);
if (p_tdm->clk_tuning_enable == 1) {
ret = snd_soc_add_dai_controls(cpu_dai,
snd_tdm_clk_controls,
ARRAY_SIZE(snd_tdm_clk_controls));
if (ret < 0)
pr_err("%s, failed add snd tdm clk controls\n",
__func__);
}
/* config ddr arb */
aml_tdm_arb_config(p_tdm->actrl);
@@ -1730,14 +1737,17 @@ static int aml_tdm_platform_probe(struct platform_device *pdev)
/*return PTR_ERR(p_tdm->pin_ctl);*/
}
/* mclk pad ctrl */
ret = of_property_read_u32(node, "mclk_pad",
&p_tdm->mclk_pad);
ret = of_property_read_u32(node, "start_clk_enable",
&p_tdm->start_clk_enable);
if (ret < 0)
p_tdm->mclk_pad = -1; /* not use mclk in defalut. */
p_tdm->start_clk_enable = 0;
else
pr_info("TDM id %d output clk enable:%d\n",
p_tdm->id, p_tdm->start_clk_enable);
/*set default clk for output*/
aml_set_default_tdm_clk(p_tdm);
if (p_tdm->start_clk_enable == 1)
aml_set_default_tdm_clk(p_tdm);
p_tdm->dev = dev;
/* For debug to disable share buffer */
@@ -1755,6 +1765,14 @@ static int aml_tdm_platform_probe(struct platform_device *pdev)
return ret;
}
ret = of_property_read_u32(node, "clk_tuning_enable",
&p_tdm->clk_tuning_enable);
if (ret < 0)
p_tdm->clk_tuning_enable = 0;
else
pr_info("TDM id %d tuning clk enable:%d\n",
p_tdm->id, p_tdm->clk_tuning_enable);
return devm_snd_soc_register_platform(dev, &aml_tdm_platform);
}