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rk30: gpio: pin base linear
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@@ -19,7 +19,7 @@
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#define GPIO_LS_SYNC 0x60
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#define NUM_GROUP 32
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#define MAX_BANK 6
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#define MAX_BANK 7
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#define PIN_BASE NR_GIC_IRQS
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@@ -239,22 +239,22 @@
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#define RK30_PIN4_PD6 (4*NUM_GROUP + PIN_BASE + 30)
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#define RK30_PIN4_PD7 (4*NUM_GROUP + PIN_BASE + 31)
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#define RK30_PIN6_PA0 (5*NUM_GROUP + PIN_BASE + 0)
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#define RK30_PIN6_PA1 (5*NUM_GROUP + PIN_BASE + 1)
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#define RK30_PIN6_PA2 (5*NUM_GROUP + PIN_BASE + 2)
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#define RK30_PIN6_PA3 (5*NUM_GROUP + PIN_BASE + 3)
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#define RK30_PIN6_PA4 (5*NUM_GROUP + PIN_BASE + 4)
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#define RK30_PIN6_PA5 (5*NUM_GROUP + PIN_BASE + 5)
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#define RK30_PIN6_PA6 (5*NUM_GROUP + PIN_BASE + 6)
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#define RK30_PIN6_PA7 (5*NUM_GROUP + PIN_BASE + 7)
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#define RK30_PIN6_PB0 (5*NUM_GROUP + PIN_BASE + 8)
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#define RK30_PIN6_PB1 (5*NUM_GROUP + PIN_BASE + 9)
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#define RK30_PIN6_PB2 (5*NUM_GROUP + PIN_BASE + 10)
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#define RK30_PIN6_PB3 (5*NUM_GROUP + PIN_BASE + 11)
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#define RK30_PIN6_PB4 (5*NUM_GROUP + PIN_BASE + 12)
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#define RK30_PIN6_PB5 (5*NUM_GROUP + PIN_BASE + 13)
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#define RK30_PIN6_PB6 (5*NUM_GROUP + PIN_BASE + 14)
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#define RK30_PIN6_PB7 (5*NUM_GROUP + PIN_BASE + 15)
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#define RK30_PIN6_PA0 (6*NUM_GROUP + PIN_BASE + 0)
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#define RK30_PIN6_PA1 (6*NUM_GROUP + PIN_BASE + 1)
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#define RK30_PIN6_PA2 (6*NUM_GROUP + PIN_BASE + 2)
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#define RK30_PIN6_PA3 (6*NUM_GROUP + PIN_BASE + 3)
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#define RK30_PIN6_PA4 (6*NUM_GROUP + PIN_BASE + 4)
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#define RK30_PIN6_PA5 (6*NUM_GROUP + PIN_BASE + 5)
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#define RK30_PIN6_PA6 (6*NUM_GROUP + PIN_BASE + 6)
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#define RK30_PIN6_PA7 (6*NUM_GROUP + PIN_BASE + 7)
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#define RK30_PIN6_PB0 (6*NUM_GROUP + PIN_BASE + 8)
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#define RK30_PIN6_PB1 (6*NUM_GROUP + PIN_BASE + 9)
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#define RK30_PIN6_PB2 (6*NUM_GROUP + PIN_BASE + 10)
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#define RK30_PIN6_PB3 (6*NUM_GROUP + PIN_BASE + 11)
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#define RK30_PIN6_PB4 (6*NUM_GROUP + PIN_BASE + 12)
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#define RK30_PIN6_PB5 (6*NUM_GROUP + PIN_BASE + 13)
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#define RK30_PIN6_PB6 (6*NUM_GROUP + PIN_BASE + 14)
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#define RK30_PIN6_PB7 (6*NUM_GROUP + PIN_BASE + 15)
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#endif
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#if defined(CONFIG_SPI_FPGA_GPIO)
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@@ -95,7 +95,7 @@
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#define IRQ_ARM_PMU RK30XX_IRQ(103)
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#define NR_GIC_IRQS (5 * 32)
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#define NR_GPIO_IRQS (6 * 32)
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#define NR_GPIO_IRQS (7 * 32)
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#define NR_BOARD_IRQS 64
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#define NR_IRQS (NR_GIC_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
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@@ -89,7 +89,7 @@ static int rk30_gpiolib_request(struct gpio_chip *chip, unsigned offset);
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.pull_updown = rk30_gpiolib_pull_updown, \
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.dbg_show = rk30_gpiolib_dbg_show, \
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.to_irq = rk30_gpiolib_to_irq, \
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.base = ID < 6 ? PIN_BASE + ID*NUM_GROUP : PIN_BASE + 5*NUM_GROUP, \
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.base = PIN_BASE + ID*NUM_GROUP, \
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.ngpio = ID < 6 ? NUM_GROUP : 16, \
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}, \
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.id = ID, \
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@@ -426,11 +426,10 @@ static struct irq_chip rk30_gpio_irq_chip = {
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void __init rk30_gpio_init(void)
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{
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unsigned int i, j, pin;
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unsigned int i, j, pin, irqs = 0;
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struct rk30_gpio_bank *bank;
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bank = rk30_gpio_banks;
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pin = PIN_BASE;
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for (i = 0; i < ARRAY_SIZE(rk30_gpio_banks); i++, bank++) {
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spin_lock_init(&bank->lock);
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@@ -439,6 +438,7 @@ void __init rk30_gpio_init(void)
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gpiochip_add(&bank->chip);
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__raw_writel(0, bank->regbase + GPIO_INTEN);
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pin = bank->chip.base;
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for (j = 0; j < 32; j++) {
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unsigned int irq = gpio_to_irq(pin);
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if (pin > MAX_PIN)
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@@ -448,12 +448,13 @@ void __init rk30_gpio_init(void)
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irq_set_chip_and_handler(irq, &rk30_gpio_irq_chip, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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pin++;
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irqs++;
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}
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irq_set_handler_data(bank->irq, bank);
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irq_set_chained_handler(bank->irq, rk30_gpio_irq_handler);
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}
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printk("%s: %d gpio irqs in %d banks\n", __func__, pin - PIN_BASE, ARRAY_SIZE(rk30_gpio_banks));
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printk("%s: %d gpio irqs in %d banks\n", __func__, irqs, ARRAY_SIZE(rk30_gpio_banks));
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}
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#ifdef CONFIG_PM
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