shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip/rk628: workaround input mode positive polarity is not supported

Browse Source 
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: I41132b2320cac3d4738de6b4914d020b63579143
This commit is contained in:
Shunqing Chen
2020-11-13 14:27:19 +08:00
committed by Tao Huang
parent e8a4d211a2
commit 125ccf92ec
1 changed files with 24 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/gpu/drm/rockchip/rk628/rk628_post_process.c
View File

@@ -18,6 +18,11 @@
#include <drm/drm_of.h>
#include <drm/drmP.h>
enum rk628_mode_sync_pol {
MODE_FLAG_NSYNC,
MODE_FLAG_PSYNC,
};
struct rk628_post_process {
struct drm_bridge base;
struct drm_bridge *bridge;
@@ -31,6 +36,7 @@ struct rk628_post_process {
struct reset_control *rstc_clk_rx;
struct reset_control *rstc_vop;
struct rk628 *parent;
int sync_pol;
};
static inline struct rk628_post_process *bridge_to_pp(struct drm_bridge *bridge)
@@ -227,9 +233,9 @@ static void rk628_post_process_bridge_pre_enable(struct drm_bridge *bridge)
udelay(10);
regmap_update_bits(pp->grf, GRF_SYSTEM_CON0, SW_VSYNC_POL_MASK,
SW_VSYNC_POL(1));
SW_VSYNC_POL(pp->sync_pol));
regmap_update_bits(pp->grf, GRF_SYSTEM_CON0, SW_HSYNC_POL_MASK,
SW_HSYNC_POL(1));
SW_HSYNC_POL(pp->sync_pol));
rk628_post_process_scaler_init(pp, src, dst);
}
@@ -296,9 +302,15 @@ rk628_post_process_bridge_mode_fixup(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
struct drm_display_mode *adj)
{
/* Fixup sync polarities, both hsync and vsync are active high */
adj->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
adj->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
struct rk628_post_process *pp = bridge_to_pp(bridge);
if (pp->sync_pol == MODE_FLAG_NSYNC) {
adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
} else {
adj->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
adj->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
}
return true;
}
@@ -376,6 +388,7 @@ static int rk628_post_process_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct rk628_post_process *pp;
u32 bus_flags;
u32 val;
int ret;
if (!of_device_is_available(dev->of_node))
@@ -425,6 +438,12 @@ static int rk628_post_process_probe(struct platform_device *pdev)
return ret;
}
ret = of_property_read_u32(dev->of_node, "mode-sync-pol", &val);
if (ret < 0)
pp->sync_pol = MODE_FLAG_PSYNC;
else
pp->sync_pol = (!val ? MODE_FLAG_NSYNC : MODE_FLAG_PSYNC);
pp->base.funcs = &rk628_post_process_bridge_funcs;
pp->base.of_node = dev->of_node;
drm_bridge_add(&pp->base);