mirror of
https://github.com/hardkernel/linux.git
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support 3 usb ethernet: dm9620, ax8872b, sr9700 (2)
This commit is contained in:
胡卫国
550
drivers/net/usb/asix.h
Executable file
550
drivers/net/usb/asix.h
Executable file
@@ -0,0 +1,550 @@
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#ifndef __LINUX_USBNET_ASIX_H
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#define __LINUX_USBNET_ASIX_H
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/*
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* Turn on this flag if the implementation of your USB host controller
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* cannot handle non-double word aligned buffer.
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* When turn on this flag, driver will fixup egress packet aligned on double
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* word boundary before deliver to USB host controller. And will Disable the
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* function "skb_reserve (skb, NET_IP_ALIGN)" to retain the buffer aligned on
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* double word alignment for ingress packets.
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*/
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#define AX_FORCE_BUFF_ALIGN 1
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#define AX_MONITOR_MODE 0x01
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#define AX_MONITOR_LINK 0x02
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#define AX_MONITOR_MAGIC 0x04
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#define AX_MONITOR_HSFS 0x10
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/* AX88172 Medium Status Register values */
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#define AX_MEDIUM_FULL_DUPLEX 0x02
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#define AX_MEDIUM_TX_ABORT_ALLOW 0x04
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#define AX_MEDIUM_FLOW_CONTROL_EN 0x10
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#define AX_MCAST_FILTER_SIZE 8
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#define AX_MAX_MCAST 64
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#define AX_EEPROM_LEN 0x40
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#define AX_SWRESET_CLEAR 0x00
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#define AX_SWRESET_RR 0x01
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#define AX_SWRESET_RT 0x02
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#define AX_SWRESET_PRTE 0x04
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#define AX_SWRESET_PRL 0x08
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#define AX_SWRESET_BZ 0x10
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#define AX_SWRESET_IPRL 0x20
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#define AX_SWRESET_IPPD 0x40
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#define AX_SWRESET_IPOSC 0x0080
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#define AX_SWRESET_IPPSL_0 0x0100
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#define AX_SWRESET_IPPSL_1 0x0200
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#define AX_SWRESET_IPCOPS 0x0400
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#define AX_SWRESET_IPCOPSC 0x0800
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#define AX_SWRESET_AUTODETACH 0x1000
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#define AX_SWRESET_WOLLP 0x8000
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#define AX88772_IPG0_DEFAULT 0x15
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#define AX88772_IPG1_DEFAULT 0x0c
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#define AX88772_IPG2_DEFAULT 0x0E
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#define AX88772A_IPG0_DEFAULT 0x15
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#define AX88772A_IPG1_DEFAULT 0x16
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#define AX88772A_IPG2_DEFAULT 0x1A
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#define AX88772_MEDIUM_FULL_DUPLEX 0x0002
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#define AX88772_MEDIUM_RESERVED 0x0004
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#define AX88772_MEDIUM_RX_FC_ENABLE 0x0010
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#define AX88772_MEDIUM_TX_FC_ENABLE 0x0020
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#define AX88772_MEDIUM_PAUSE_FORMAT 0x0080
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#define AX88772_MEDIUM_RX_ENABLE 0x0100
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#define AX88772_MEDIUM_100MB 0x0200
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#define AX88772_MEDIUM_DEFAULT \
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(AX88772_MEDIUM_FULL_DUPLEX | AX88772_MEDIUM_RX_FC_ENABLE | \
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AX88772_MEDIUM_TX_FC_ENABLE | AX88772_MEDIUM_100MB | \
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AX88772_MEDIUM_RESERVED | AX88772_MEDIUM_RX_ENABLE )
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#define AX_CMD_SET_SW_MII 0x06
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#define AX_CMD_READ_MII_REG 0x07
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#define AX_CMD_WRITE_MII_REG 0x08
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#define AX_CMD_SET_HW_MII 0x0a
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#define AX_CMD_READ_EEPROM 0x0b
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#define AX_CMD_WRITE_EEPROM 0x0c
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#define AX_CMD_WRITE_EEPROM_EN 0x0d
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#define AX_CMD_WRITE_EEPROM_DIS 0x0e
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#define AX_CMD_WRITE_RX_CTL 0x10
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#define AX_CMD_READ_IPG012 0x11
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#define AX_CMD_WRITE_IPG0 0x12
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#define AX_CMD_WRITE_IPG1 0x13
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#define AX_CMD_WRITE_IPG2 0x14
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#define AX_CMD_WRITE_MULTI_FILTER 0x16
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#define AX_CMD_READ_NODE_ID 0x17
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#define AX_CMD_READ_PHY_ID 0x19
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#define AX_CMD_READ_MEDIUM_MODE 0x1a
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#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
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#define AX_CMD_READ_MONITOR_MODE 0x1c
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#define AX_CMD_WRITE_MONITOR_MODE 0x1d
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#define AX_CMD_WRITE_GPIOS 0x1f
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#define AX_CMD_SW_RESET 0x20
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#define AX_CMD_SW_PHY_STATUS 0x21
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#define AX_CMD_SW_PHY_SELECT 0x22
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#define AX_PHYSEL_PSEL (1 << 0)
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#define AX_PHYSEL_ASEL (1 << 1)
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#define AX_PHYSEL_SSMII (1 << 2)
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#define AX_PHYSEL_SSRMII (2 << 2)
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#define AX_PHYSEL_SSRRMII (3 << 2)
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#define AX_PHYSEL_SSEN (1 << 4)
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#define AX88772_CMD_READ_NODE_ID 0x13
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#define AX88772_CMD_WRITE_NODE_ID 0x14
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#define AX_CMD_READ_RXCOE_CTL 0x2b
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#define AX_CMD_WRITE_RXCOE_CTL 0x2c
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#define AX_CMD_READ_TXCOE_CTL 0x2d
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#define AX_CMD_WRITE_TXCOE_CTL 0x2e
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#define REG_LENGTH 2
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#define PHY_ID_MASK 0x1f
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#define AX_RXCOE_IPCE 0x0001
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#define AX_RXCOE_IPVE 0x0002
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#define AX_RXCOE_V6VE 0x0004
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#define AX_RXCOE_TCPE 0x0008
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#define AX_RXCOE_UDPE 0x0010
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#define AX_RXCOE_ICMP 0x0020
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#define AX_RXCOE_IGMP 0x0040
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#define AX_RXCOE_ICV6 0x0080
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#define AX_RXCOE_TCPV6 0x0100
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#define AX_RXCOE_UDPV6 0x0200
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#define AX_RXCOE_ICMV6 0x0400
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#define AX_RXCOE_IGMV6 0x0800
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#define AX_RXCOE_ICV6V6 0x1000
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#define AX_RXCOE_FOPC 0x8000
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#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)
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#define AX_RXCOE_DEF_CSUM (AX_RXCOE_IPCE | AX_RXCOE_IPVE | \
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AX_RXCOE_V6VE | AX_RXCOE_TCPE | \
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AX_RXCOE_UDPE | AX_RXCOE_ICV6 | \
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AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6)
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#else
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#define AX_RXCOE_DEF_CSUM (AX_RXCOE_IPCE | AX_RXCOE_IPVE | \
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AX_RXCOE_TCPE | AX_RXCOE_UDPE)
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#endif
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#define AX_RXCOE_64TE 0x0100
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#define AX_RXCOE_PPPOE 0x0200
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#define AX_RXCOE_RPCE 0x8000
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#define AX_TXCOE_IP 0x0001
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#define AX_TXCOE_TCP 0x0002
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#define AX_TXCOE_UDP 0x0004
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#define AX_TXCOE_ICMP 0x0008
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#define AX_TXCOE_IGMP 0x0010
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#define AX_TXCOE_ICV6 0x0020
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#define AX_TXCOE_TCPV6 0x0100
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#define AX_TXCOE_UDPV6 0x0200
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#define AX_TXCOE_ICMV6 0x0400
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#define AX_TXCOE_IGMV6 0x0800
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#define AX_TXCOE_ICV6V6 0x1000
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#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)
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#define AX_TXCOE_DEF_CSUM (AX_TXCOE_TCP | AX_TXCOE_UDP | \
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AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6)
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#else
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#define AX_TXCOE_DEF_CSUM (AX_TXCOE_TCP | AX_TXCOE_UDP)
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#endif
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#define AX_TXCOE_64TE 0x0001
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#define AX_TXCOE_PPPE 0x0002
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#define AX88772B_MAX_BULKIN_2K 0
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#define AX88772B_MAX_BULKIN_4K 1
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#define AX88772B_MAX_BULKIN_6K 2
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#define AX88772B_MAX_BULKIN_8K 3
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#define AX88772B_MAX_BULKIN_16K 4
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#define AX88772B_MAX_BULKIN_20K 5
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#define AX88772B_MAX_BULKIN_24K 6
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#define AX88772B_MAX_BULKIN_32K 7
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struct {unsigned short size, byte_cnt,threshold;} AX88772B_BULKIN_SIZE[] =
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{
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/* 2k */
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{2048, 0x8000, 0x8001},
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/* 4k */
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{4096, 0x8100, 0x8147},
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/* 6k */
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{6144, 0x8200, 0x81EB},
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/* 8k */
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{8192, 0x8300, 0x83D7},
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/* 16 */
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{16384, 0x8400, 0x851E},
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/* 20k */
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{20480, 0x8500, 0x8666},
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/* 24k */
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{24576, 0x8600, 0x87AE},
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/* 32k */
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{32768, 0x8700, 0x8A3D},
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};
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#define AX_RX_CTL_RH1M 0x0100 /* Enable RX-Header mode 0 */
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#define AX_RX_CTL_RH2M 0x0200 /* Enable IP header in receive buffer aligned on 32-bit aligment */
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#define AX_RX_CTL_RH3M 0x0400 /* checksum value in rx header 3 */
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#define AX_RX_HEADER_DEFAULT (AX_RX_CTL_RH1M | AX_RX_CTL_RH2M)
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#define AX_RX_CTL_MFB 0x0300 /* Maximum Frame size 16384bytes */
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#define AX_RX_CTL_START 0x0080 /* Ethernet MAC start */
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#define AX_RX_CTL_AP 0x0020 /* Accept physcial address from Multicast array */
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#define AX_RX_CTL_AM 0x0010
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#define AX_RX_CTL_AB 0x0008 /* Accetp Brocadcast frames*/
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#define AX_RX_CTL_SEP 0x0004 /* Save error packets */
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#define AX_RX_CTL_AMALL 0x0002 /* Accetp all multicast frames */
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#define AX_RX_CTL_PRO 0x0001 /* Promiscuous Mode */
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#define AX_RX_CTL_STOP 0x0000 /* Stop MAC */
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#define AX_MONITOR_MODE 0x01
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#define AX_MONITOR_LINK 0x02
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#define AX_MONITOR_MAGIC 0x04
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#define AX_MONITOR_HSFS 0x10
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#define AX_MCAST_FILTER_SIZE 8
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#define AX_MAX_MCAST 64
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#define AX_INTERRUPT_BUFSIZE 8
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#define AX_EEPROM_LEN 0x40
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#define AX_EEPROM_MAGIC 0xdeadbeef
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#define EEPROMMASK 0x7f
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/* GPIO REGISTER */
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#define AXGPIOS_GPO0EN 0X01 // 1 << 0
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#define AXGPIOS_GPO0 0X02 // 1 << 1
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#define AXGPIOS_GPO1EN 0X04 // 1 << 2
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#define AXGPIOS_GPO1 0X08 // 1 << 3
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#define AXGPIOS_GPO2EN 0X10 // 1 << 4
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#define AXGPIOS_GPO2 0X20 // 1 << 5
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#define AXGPIOS_RSE 0X80 // 1 << 7
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/* TX-header format */
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#define AX_TX_HDR_CPHI 0x4000
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#define AX_TX_HDR_DICF 0x8000
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// GMII register definitions
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#define GMII_PHY_CONTROL 0x00 // control reg
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#define GMII_PHY_STATUS 0x01 // status reg
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#define GMII_PHY_OUI 0x02 // most of the OUI bits
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#define GMII_PHY_MODEL 0x03 // model/rev bits, and rest of OUI
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#define GMII_PHY_ANAR 0x04 // AN advertisement reg
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#define GMII_PHY_ANLPAR 0x05 // AN Link Partner
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#define GMII_PHY_ANER 0x06 // AN expansion reg
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#define GMII_PHY_1000BT_CONTROL 0x09 // control reg for 1000BT
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#define GMII_PHY_1000BT_STATUS 0x0A // status reg for 1000BT
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// Bit definitions: GMII Control
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#define GMII_CONTROL_RESET 0x8000 // reset bit in control reg
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#define GMII_CONTROL_LOOPBACK 0x4000 // loopback bit in control reg
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#define GMII_CONTROL_10MB 0x0000 // 10 Mbit
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#define GMII_CONTROL_100MB 0x2000 // 100Mbit
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#define GMII_CONTROL_1000MB 0x0040 // 1000Mbit
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#define GMII_CONTROL_SPEED_BITS 0x2040 // speed bit mask
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#define GMII_CONTROL_ENABLE_AUTO 0x1000 // autonegotiate enable
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#define GMII_CONTROL_POWER_DOWN 0x0800
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#define GMII_CONTROL_ISOLATE 0x0400 // islolate bit
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#define GMII_CONTROL_START_AUTO 0x0200 // restart autonegotiate
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#define GMII_CONTROL_FULL_DUPLEX 0x0100
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// Bit definitions: GMII Status
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#define GMII_STATUS_100MB_MASK 0xE000 // any of these indicate 100 Mbit
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#define GMII_STATUS_10MB_MASK 0x1800 // either of these indicate 10 Mbit
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#define GMII_STATUS_AUTO_DONE 0x0020 // auto negotiation complete
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#define GMII_STATUS_AUTO 0x0008 // auto negotiation is available
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#define GMII_STATUS_LINK_UP 0x0004 // link status bit
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#define GMII_STATUS_EXTENDED 0x0001 // extended regs exist
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#define GMII_STATUS_100T4 0x8000 // capable of 100BT4
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#define GMII_STATUS_100TXFD 0x4000 // capable of 100BTX full duplex
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#define GMII_STATUS_100TX 0x2000 // capable of 100BTX
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#define GMII_STATUS_10TFD 0x1000 // capable of 10BT full duplex
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#define GMII_STATUS_10T 0x0800 // capable of 10BT
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// Bit definitions: Auto-Negotiation Advertisement
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#define GMII_ANAR_ASYM_PAUSE 0x0800 // support asymetric pause
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#define GMII_ANAR_PAUSE 0x0400 // support pause packets
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#define GMII_ANAR_100T4 0x0200 // support 100BT4
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#define GMII_ANAR_100TXFD 0x0100 // support 100BTX full duplex
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#define GMII_ANAR_100TX 0x0080 // support 100BTX half duplex
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#define GMII_ANAR_10TFD 0x0040 // support 10BT full duplex
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#define GMII_ANAR_10T 0x0020 // support 10BT half duplex
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#define GMII_SELECTOR_FIELD 0x001F // selector field.
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// Bit definitions: Auto-Negotiation Link Partner Ability
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#define GMII_ANLPAR_100T4 0x0200 // support 100BT4
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#define GMII_ANLPAR_100TXFD 0x0100 // support 100BTX full duplex
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#define GMII_ANLPAR_100TX 0x0080 // support 100BTX half duplex
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#define GMII_ANLPAR_10TFD 0x0040 // support 10BT full duplex
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#define GMII_ANLPAR_10T 0x0020 // support 10BT half duplex
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#define GMII_ANLPAR_PAUSE 0x0400 // support pause packets
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#define GMII_ANLPAR_ASYM_PAUSE 0x0800 // support asymetric pause
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#define GMII_ANLPAR_ACK 0x4000 // means LCB was successfully rx'd
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#define GMII_SELECTOR_8023 0x0001;
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// Bit definitions: 1000BaseT AUX Control
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#define GMII_1000_AUX_CTRL_MASTER_SLAVE 0x1000
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#define GMII_1000_AUX_CTRL_FD_CAPABLE 0x0200 // full duplex capable
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#define GMII_1000_AUX_CTRL_HD_CAPABLE 0x0100 // half duplex capable
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// Bit definitions: 1000BaseT AUX Status
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#define GMII_1000_AUX_STATUS_FD_CAPABLE 0x0800 // full duplex capable
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#define GMII_1000_AUX_STATUS_HD_CAPABLE 0x0400 // half duplex capable
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// Cicada MII Registers
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#define GMII_AUX_CTRL_STATUS 0x1C
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#define GMII_AUX_ANEG_CPLT 0x8000
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#define GMII_AUX_FDX 0x0020
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#define GMII_AUX_SPEED_1000 0x0010
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#define GMII_AUX_SPEED_100 0x0008
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#ifndef ADVERTISE_PAUSE_CAP
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#define ADVERTISE_PAUSE_CAP 0x0400
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#endif
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#ifndef MII_STAT1000
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#define MII_STAT1000 0x000A
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#endif
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#ifndef LPA_1000FULL
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#define LPA_1000FULL 0x0800
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#endif
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// medium mode register
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#define MEDIUM_GIGA_MODE 0x0001
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#define MEDIUM_FULL_DUPLEX_MODE 0x0002
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#define MEDIUM_TX_ABORT_MODE 0x0004
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#define MEDIUM_ENABLE_125MHZ 0x0008
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#define MEDIUM_ENABLE_RX_FLOWCTRL 0x0010
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#define MEDIUM_ENABLE_TX_FLOWCTRL 0x0020
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#define MEDIUM_ENABLE_JUMBO_FRAME 0x0040
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#define MEDIUM_CHECK_PAUSE_FRAME_MODE 0x0080
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#define MEDIUM_ENABLE_RECEIVE 0x0100
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#define MEDIUM_MII_100M_MODE 0x0200
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#define MEDIUM_ENABLE_JAM_PATTERN 0x0400
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#define MEDIUM_ENABLE_STOP_BACKPRESSURE 0x0800
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#define MEDIUM_ENABLE_SUPPER_MAC_SUPPORT 0x1000
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/* PHY mode */
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#define PHY_MODE_MARVELL 0
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#define PHY_MODE_CICADA_FAMILY 1
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#define PHY_MODE_CICADA_V1 1
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#define PHY_MODE_AGERE_FAMILY 2
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#define PHY_MODE_AGERE_V0 2
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#define PHY_MODE_CICADA_V2 5
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#define PHY_MODE_AGERE_V0_GMII 6
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#define PHY_MODE_CICADA_V2_ASIX 9
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#define PHY_MODE_VSC8601 10
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#define PHY_MODE_RTL8211CL 12
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#define PHY_MODE_RTL8211BN 13
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#define PHY_MODE_RTL8251CL 14
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#define PHY_MODE_ATTANSIC_V0 0x40
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#define PHY_MODE_ATTANSIC_FAMILY 0x40
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#define PHY_MODE_MAC_TO_MAC_GMII 0x7C
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/* */
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#define LED_MODE_MARVELL 0
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#define LED_MODE_CAMEO 1
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#define MARVELL_LED_CTRL 0x18
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#define MARVELL_MANUAL_LED 0x19
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#define PHY_IDENTIFIER 0x0002
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#define PHY_AGERE_IDENTIFIER 0x0282
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#define PHY_CICADA_IDENTIFIER 0x000f
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#define PHY_MARVELL_IDENTIFIER 0x0141
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#define PHY_MARVELL_STATUS 0x001b
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#define MARVELL_STATUS_HWCFG 0x0004 /* SGMII without clock */
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||||
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#define PHY_MARVELL_CTRL 0x0014
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#define MARVELL_CTRL_RXDELAY 0x0080
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#define MARVELL_CTRL_TXDELAY 0x0002
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||||
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||||
#define PHY_CICADA_EXTPAGE 0x001f
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||||
#define CICADA_EXTPAGE_EN 0x0001
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#define CICADA_EXTPAGE_DIS 0x0000
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||||
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||||
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||||
struct {unsigned short value, offset; } CICADA_FAMILY_HWINIT[] =
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||||
{
|
||||
{0x0001, 0x001f}, {0x1c25, 0x0017}, {0x2a30, 0x001f}, {0x234c, 0x0010},
|
||||
{0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0xa7fa, 0x0000},
|
||||
{0x0012, 0x0002}, {0x3002, 0x0001}, {0x87fa, 0x0000}, {0x52b5, 0x001f},
|
||||
{0xafac, 0x0000}, {0x000d, 0x0002}, {0x001c, 0x0001}, {0x8fac, 0x0000},
|
||||
{0x2a30, 0x001f}, {0x0012, 0x0008}, {0x2a30, 0x001f}, {0x0400, 0x0014},
|
||||
{0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0xa760, 0x0000},
|
||||
{0x0000, 0x0002}, {0xfaff, 0x0001}, {0x8760, 0x0000}, {0x52b5, 0x001f},
|
||||
{0xa760, 0x0000}, {0x0000, 0x0002}, {0xfaff, 0x0001}, {0x8760, 0x0000},
|
||||
{0x52b5, 0x001f}, {0xafae, 0x0000}, {0x0004, 0x0002}, {0x0671, 0x0001},
|
||||
{0x8fae, 0x0000}, {0x2a30, 0x001f}, {0x0012, 0x0008}, {0x0000, 0x001f},
|
||||
};
|
||||
|
||||
struct {unsigned short value, offset; } CICADA_V2_HWINIT[] =
|
||||
{
|
||||
{0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0x000f, 0x0002},
|
||||
{0x472a, 0x0001}, {0x8fa4, 0x0000}, {0x2a30, 0x001f}, {0x0212, 0x0008},
|
||||
{0x0000, 0x001f},
|
||||
};
|
||||
|
||||
struct {unsigned short value, offset; } CICADA_V2_ASIX_HWINIT[] =
|
||||
{
|
||||
{0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0x0012, 0x0002},
|
||||
{0x3002, 0x0001}, {0x87fa, 0x0000}, {0x52b5, 0x001f}, {0x000f, 0x0002},
|
||||
{0x472a, 0x0001}, {0x8fa4, 0x0000}, {0x2a30, 0x001f}, {0x0212, 0x0008},
|
||||
{0x0000, 0x001f},
|
||||
};
|
||||
|
||||
struct {unsigned short value, offset; } AGERE_FAMILY_HWINIT[] =
|
||||
{
|
||||
{0x0800, 0x0000}, {0x0007, 0x0012}, {0x8805, 0x0010}, {0xb03e, 0x0011},
|
||||
{0x8808, 0x0010}, {0xe110, 0x0011}, {0x8806, 0x0010}, {0xb03e, 0x0011},
|
||||
{0x8807, 0x0010}, {0xff00, 0x0011}, {0x880e, 0x0010}, {0xb4d3, 0x0011},
|
||||
{0x880f, 0x0010}, {0xb4d3, 0x0011}, {0x8810, 0x0010}, {0xb4d3, 0x0011},
|
||||
{0x8817, 0x0010}, {0x1c00, 0x0011}, {0x300d, 0x0010}, {0x0001, 0x0011},
|
||||
{0x0002, 0x0012},
|
||||
};
|
||||
|
||||
struct ax88178_data {
|
||||
u16 EepromData;
|
||||
u16 MediaLink;
|
||||
int UseGpio0;
|
||||
int UseRgmii;
|
||||
u8 PhyMode;
|
||||
u8 LedMode;
|
||||
u8 BuffaloOld;
|
||||
};
|
||||
|
||||
enum watchdog_state {
|
||||
AX_NOP = 0,
|
||||
CHK_LINK, /* Routine A */
|
||||
CHK_CABLE_EXIST, /* Called by A */
|
||||
CHK_CABLE_EXIST_AGAIN, /* Routine B */
|
||||
PHY_POWER_UP, /* Called by B */
|
||||
PHY_POWER_UP_BH,
|
||||
PHY_POWER_DOWN,
|
||||
CHK_CABLE_STATUS, /* Routine C */
|
||||
WAIT_AUTONEG_COMPLETE,
|
||||
AX_SET_RX_CFG,
|
||||
};
|
||||
|
||||
struct ax88772b_data {
|
||||
struct usbnet *dev;
|
||||
struct workqueue_struct *ax_work;
|
||||
struct work_struct check_link;
|
||||
unsigned long time_to_chk;
|
||||
u16 psc;
|
||||
u8 pw_enabled;
|
||||
u8 Event;
|
||||
u8 checksum;
|
||||
};
|
||||
|
||||
struct ax88772a_data {
|
||||
struct usbnet *dev;
|
||||
struct workqueue_struct *ax_work;
|
||||
struct work_struct check_link;
|
||||
unsigned long autoneg_start;
|
||||
#define AX88772B_WATCHDOG (6 * HZ)
|
||||
u8 Event;
|
||||
u8 TickToExpire;
|
||||
u8 DlyIndex;
|
||||
u8 DlySel;
|
||||
u16 EepromData;
|
||||
};
|
||||
|
||||
struct ax88772_data {
|
||||
struct usbnet *dev;
|
||||
struct workqueue_struct *ax_work;
|
||||
struct work_struct check_link;
|
||||
unsigned long autoneg_start;
|
||||
u8 Event;
|
||||
u8 TickToExpire;
|
||||
};
|
||||
|
||||
#define AX_RX_CHECKSUM 1
|
||||
#define AX_TX_CHECKSUM 2
|
||||
|
||||
/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
|
||||
struct ax8817x_data {
|
||||
u8 multi_filter[AX_MCAST_FILTER_SIZE];
|
||||
int (*resume) (struct usb_interface *intf);
|
||||
int (*suspend) (struct usb_interface *intf,
|
||||
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,10)
|
||||
pm_message_t message);
|
||||
#else
|
||||
u32 message);
|
||||
#endif
|
||||
};
|
||||
|
||||
struct ax88172_int_data {
|
||||
u16 res1;
|
||||
#define AX_INT_PPLS_LINK (1 << 0)
|
||||
#define AX_INT_SPLS_LINK (1 << 1)
|
||||
#define AX_INT_CABOFF_UNPLUG (1 << 7)
|
||||
u8 link;
|
||||
u16 res2;
|
||||
u8 status;
|
||||
u16 res3;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define AX_RXHDR_L4_ERR (1 << 8)
|
||||
#define AX_RXHDR_L3_ERR (1 << 9)
|
||||
|
||||
#define AX_RXHDR_L4_TYPE_UDP 1
|
||||
#define AX_RXHDR_L4_TYPE_ICMP 2
|
||||
#define AX_RXHDR_L4_TYPE_IGMP 3
|
||||
#define AX_RXHDR_L4_TYPE_TCP 4
|
||||
#define AX_RXHDR_L4_TYPE_TCMPV6 5
|
||||
#define AX_RXHDR_L4_TYPE_MASK 7
|
||||
|
||||
#define AX_RXHDR_L3_TYPE_IP 1
|
||||
#define AX_RXHDR_L3_TYPE_IPV6 2
|
||||
|
||||
struct ax88772b_rx_header {
|
||||
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||||
u16 len:11,
|
||||
res1:1,
|
||||
crc:1,
|
||||
mii:1,
|
||||
runt:1,
|
||||
mc_bc:1;
|
||||
|
||||
u16 len_bar:11,
|
||||
res2:5;
|
||||
|
||||
u8 vlan_ind:3,
|
||||
vlan_tag_striped:1,
|
||||
pri:3,
|
||||
res3:1;
|
||||
|
||||
u8 l4_csum_err:1,
|
||||
l3_csum_err:1,
|
||||
l4_type:3,
|
||||
l3_type:2,
|
||||
ce:1;
|
||||
#elif defined (__BIG_ENDIAN_BITFIELD)
|
||||
u16 mc_bc:1,
|
||||
runt:1,
|
||||
mii:1,
|
||||
crc:1,
|
||||
res1:1,
|
||||
len:11;
|
||||
|
||||
u16 res2:5,
|
||||
len_bar:11;
|
||||
|
||||
u8 res3:1,
|
||||
pri:3,
|
||||
vlan_tag_striped:1,
|
||||
vlan_ind:3;
|
||||
|
||||
u8 ce:1,
|
||||
l3_type:2,
|
||||
l4_type:3,
|
||||
l3_csum_err:1,
|
||||
l4_csum_err:1;
|
||||
#else
|
||||
#error "Please fix <asm/byteorder.h>"
|
||||
#endif
|
||||
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#endif /* __LINUX_USBNET_ASIX_H */
|
||||
|
||||
1380
drivers/net/usb/axusbnet.c
Executable file
1380
drivers/net/usb/axusbnet.c
Executable file
File diff suppressed because it is too large
Load Diff
211
drivers/net/usb/axusbnet.h
Executable file
211
drivers/net/usb/axusbnet.h
Executable file
@@ -0,0 +1,211 @@
|
||||
/*
|
||||
* USB Networking Link Interface
|
||||
*
|
||||
* Copyright (C) 2000-2005 by David Brownell <dbrownell@users.sourceforge.net>
|
||||
* Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_USB_USBNET_H
|
||||
#define __LINUX_USB_USBNET_H
|
||||
|
||||
#ifndef gfp_t
|
||||
#define gfp_t int
|
||||
#endif
|
||||
|
||||
/* interface from usbnet core to each USB networking link we handle */
|
||||
struct usbnet {
|
||||
/* housekeeping */
|
||||
struct usb_device *udev;
|
||||
struct usb_interface *intf;
|
||||
struct driver_info *driver_info;
|
||||
const char *driver_name;
|
||||
void *driver_priv;
|
||||
wait_queue_head_t *wait;
|
||||
// struct mutex phy_mutex;
|
||||
unsigned char suspend_count;
|
||||
|
||||
/* i/o info: pipes etc */
|
||||
unsigned in, out;
|
||||
struct usb_host_endpoint *status;
|
||||
unsigned maxpacket;
|
||||
struct timer_list delay;
|
||||
|
||||
/* protocol/interface state */
|
||||
struct net_device *net;
|
||||
struct net_device_stats stats;
|
||||
int msg_enable;
|
||||
unsigned long data [5];
|
||||
u32 xid;
|
||||
u32 hard_mtu; /* count any extra framing */
|
||||
size_t rx_urb_size; /* size for rx urbs */
|
||||
struct mii_if_info mii;
|
||||
|
||||
/* various kinds of pending driver work */
|
||||
struct sk_buff_head rxq;
|
||||
struct sk_buff_head txq;
|
||||
struct sk_buff_head done;
|
||||
struct sk_buff_head rxq_pause;
|
||||
struct urb *interrupt;
|
||||
struct tasklet_struct bh;
|
||||
|
||||
struct work_struct kevent;
|
||||
unsigned long flags;
|
||||
# define EVENT_TX_HALT 0
|
||||
# define EVENT_RX_HALT 1
|
||||
# define EVENT_RX_MEMORY 2
|
||||
# define EVENT_STS_SPLIT 3
|
||||
# define EVENT_LINK_RESET 4
|
||||
# define EVENT_RX_PAUSED 5
|
||||
|
||||
void *priv; /* point to minidriver private data */
|
||||
unsigned char rx_size;
|
||||
int asix_suspend;
|
||||
int intr_complete;
|
||||
wait_queue_head_t intr_wait;
|
||||
};
|
||||
|
||||
static inline struct usb_driver *driver_of(struct usb_interface *intf)
|
||||
{
|
||||
return to_usb_driver(intf->dev.driver);
|
||||
}
|
||||
|
||||
/* interface from the device/framing level "minidriver" to core */
|
||||
struct driver_info {
|
||||
char *description;
|
||||
|
||||
int flags;
|
||||
/* framing is CDC Ethernet, not writing ZLPs (hw issues), or optionally: */
|
||||
#define FLAG_FRAMING_NC 0x0001 /* guard against device dropouts */
|
||||
#define FLAG_FRAMING_GL 0x0002 /* genelink batches packets */
|
||||
#define FLAG_FRAMING_Z 0x0004 /* zaurus adds a trailer */
|
||||
#define FLAG_FRAMING_RN 0x0008 /* RNDIS batches, plus huge header */
|
||||
|
||||
#define FLAG_NO_SETINT 0x0010 /* device can't set_interface() */
|
||||
#define FLAG_ETHER 0x0020 /* maybe use "eth%d" names */
|
||||
|
||||
#define FLAG_FRAMING_AX 0x0040 /* AX88772/178 packets */
|
||||
#define FLAG_WLAN 0x0080 /* use "wlan%d" names */
|
||||
#define FLAG_AVOID_UNLINK_URBS 0x0100 /* don't unlink urbs at usbnet_stop() */
|
||||
#define FLAG_SEND_ZLP 0x0200 /* hw requires ZLPs are sent */
|
||||
#define FLAG_HW_IP_ALIGNMENT 0x0400 /* AX88772B support hardware IP alignment */
|
||||
|
||||
|
||||
/* init device ... can sleep, or cause probe() failure */
|
||||
int (*bind)(struct usbnet *, struct usb_interface *);
|
||||
|
||||
/* cleanup device ... can sleep, but can't fail */
|
||||
void (*unbind)(struct usbnet *, struct usb_interface *);
|
||||
|
||||
/* reset device ... can sleep */
|
||||
int (*reset)(struct usbnet *);
|
||||
|
||||
/* stop device ... can sleep */
|
||||
int (*stop)(struct usbnet *);
|
||||
|
||||
/* see if peer is connected ... can sleep */
|
||||
int (*check_connect)(struct usbnet *);
|
||||
|
||||
/* for status polling */
|
||||
void (*status)(struct usbnet *, struct urb *);
|
||||
|
||||
/* link reset handling, called from defer_kevent */
|
||||
int (*link_reset)(struct usbnet *);
|
||||
|
||||
/* fixup rx packet (strip framing) */
|
||||
int (*rx_fixup)(struct usbnet *dev, struct sk_buff *skb);
|
||||
|
||||
/* fixup tx packet (add framing) */
|
||||
struct sk_buff *(*tx_fixup)(struct usbnet *dev,
|
||||
struct sk_buff *skb, gfp_t flags);
|
||||
|
||||
/* early initialization code, can sleep. This is for minidrivers
|
||||
* having 'subminidrivers' that need to do extra initialization
|
||||
* right after minidriver have initialized hardware. */
|
||||
int (*early_init)(struct usbnet *dev);
|
||||
|
||||
/* called by minidriver when receiving indication */
|
||||
void (*indication)(struct usbnet *dev, void *ind, int indlen);
|
||||
|
||||
/* for new devices, use the descriptor-reading code instead */
|
||||
int in; /* rx endpoint */
|
||||
int out; /* tx endpoint */
|
||||
|
||||
unsigned long data; /* Misc driver specific data */
|
||||
};
|
||||
|
||||
/* Drivers that reuse some of the standard USB CDC infrastructure
|
||||
* (notably, using multiple interfaces according to the CDC
|
||||
* union descriptor) get some helper code.
|
||||
*/
|
||||
struct cdc_state {
|
||||
struct usb_cdc_header_desc *header;
|
||||
struct usb_cdc_union_desc *u;
|
||||
struct usb_cdc_ether_desc *ether;
|
||||
struct usb_interface *control;
|
||||
struct usb_interface *data;
|
||||
};
|
||||
|
||||
/* CDC and RNDIS support the same host-chosen packet filters for IN transfers */
|
||||
#define DEFAULT_FILTER (USB_CDC_PACKET_TYPE_BROADCAST \
|
||||
|USB_CDC_PACKET_TYPE_ALL_MULTICAST \
|
||||
|USB_CDC_PACKET_TYPE_PROMISCUOUS \
|
||||
|USB_CDC_PACKET_TYPE_DIRECTED)
|
||||
|
||||
|
||||
/* we record the state for each of our queued skbs */
|
||||
enum skb_state {
|
||||
illegal = 0,
|
||||
tx_start, tx_done,
|
||||
rx_start, rx_done, rx_cleanup
|
||||
};
|
||||
|
||||
struct skb_data { /* skb->cb is one of these */
|
||||
struct urb *urb;
|
||||
struct usbnet *dev;
|
||||
enum skb_state state;
|
||||
size_t length;
|
||||
};
|
||||
|
||||
#ifndef skb_queue_walk_safe
|
||||
#define skb_queue_walk_safe(queue, skb, tmp) \
|
||||
for (skb = (queue)->next, tmp = skb->next; \
|
||||
skb != (struct sk_buff *)(queue); \
|
||||
skb = tmp, tmp = skb->next)
|
||||
#endif
|
||||
|
||||
/* messaging support includes the interface name, so it must not be
|
||||
* used before it has one ... notably, in minidriver bind() calls.
|
||||
*/
|
||||
#ifdef DEBUG
|
||||
#define devdbg(usbnet, fmt, arg...) \
|
||||
printk("%s: " fmt "\n" , (usbnet)->net->name , ## arg)
|
||||
#else
|
||||
#define devdbg(usbnet, fmt, arg...) \
|
||||
({ if (0) printk("%s: " fmt "\n" , (usbnet)->net->name , \
|
||||
## arg); 0; })
|
||||
#endif
|
||||
|
||||
#define deverr(usbnet, fmt, arg...) \
|
||||
printk(KERN_ERR "%s: " fmt "\n" , (usbnet)->net->name , ## arg)
|
||||
#define devwarn(usbnet, fmt, arg...) \
|
||||
printk(KERN_WARNING "%s: " fmt "\n" , (usbnet)->net->name , ## arg)
|
||||
|
||||
#define devinfo(usbnet, fmt, arg...) \
|
||||
printk(KERN_INFO "%s: " fmt "\n" , (usbnet)->net->name , ## arg); \
|
||||
|
||||
|
||||
#endif /* __LINUX_USB_USBNET_H */
|
||||
1042
drivers/net/usb/dm9620.c
Executable file
1042
drivers/net/usb/dm9620.c
Executable file
File diff suppressed because it is too large
Load Diff
622
drivers/net/usb/sr9700.c
Executable file
622
drivers/net/usb/sr9700.c
Executable file
@@ -0,0 +1,622 @@
|
||||
/*
|
||||
* SR9700_android one chip USB 2.0 ethernet devices
|
||||
*
|
||||
* Author : jokeliujl <jokeliu@163.com>
|
||||
* Date : 2010-10-01
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
//#define DEBUG
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/usb.h>
|
||||
#include <linux/crc32.h>
|
||||
#include <linux/usb/usbnet.h>
|
||||
|
||||
#include "sr9700.h"
|
||||
|
||||
/* ------------------------------------------------------------------------------------------ */
|
||||
/* sr9700_android mac and phy operations */
|
||||
/* sr9700_android read some registers from MAC */
|
||||
static int qf_read(struct usbnet *dev, u8 reg, u16 length, void *data)
|
||||
{
|
||||
void *buf;
|
||||
int err = -ENOMEM;
|
||||
|
||||
devdbg(dev, "qf_read() reg=0x%02x length=%d", reg, length);
|
||||
|
||||
buf = kmalloc(length, GFP_KERNEL);
|
||||
if (!buf)
|
||||
goto out;
|
||||
|
||||
err = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
|
||||
QF_RD_REGS, QF_REQ_RD_REG,
|
||||
0, reg, buf, length, USB_CTRL_SET_TIMEOUT);
|
||||
if (err == length)
|
||||
memcpy(data, buf, length);
|
||||
else if (err >= 0)
|
||||
err = -EINVAL;
|
||||
kfree(buf);
|
||||
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
|
||||
/* sr9700_android write some registers to MAC */
|
||||
static int qf_write(struct usbnet *dev, u8 reg, u16 length, void *data)
|
||||
{
|
||||
void *buf = NULL;
|
||||
int err = -ENOMEM;
|
||||
|
||||
devdbg(dev, "qf_write() reg=0x%02x, length=%d", reg, length);
|
||||
|
||||
if (data) {
|
||||
buf = kmalloc(length, GFP_KERNEL);
|
||||
if (!buf)
|
||||
goto out;
|
||||
memcpy(buf, data, length);
|
||||
}
|
||||
|
||||
err = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
|
||||
QF_WR_REGS, QF_REQ_WR_REG,
|
||||
0, reg, buf, length, USB_CTRL_SET_TIMEOUT);
|
||||
kfree(buf);
|
||||
if (err >= 0 && err < length)
|
||||
err = -EINVAL;
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
|
||||
/* sr9700_android read one register from MAC */
|
||||
static int qf_read_reg(struct usbnet *dev, u8 reg, u8 *value)
|
||||
{
|
||||
return qf_read(dev, reg, 1, value);
|
||||
}
|
||||
|
||||
/* sr9700_android write one register to MAC */
|
||||
static int qf_write_reg(struct usbnet *dev, u8 reg, u8 value)
|
||||
{
|
||||
devdbg(dev, "qf_write_reg() reg=0x%02x, value=0x%02x", reg, value);
|
||||
return usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
|
||||
QF_WR_REG, QF_REQ_WR_REG,
|
||||
value, reg, NULL, 0, USB_CTRL_SET_TIMEOUT);
|
||||
}
|
||||
|
||||
/* async mode for writing registers or reg blocks */
|
||||
static void qf_write_async_callback(struct urb *urb)
|
||||
{
|
||||
struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context;
|
||||
|
||||
if (urb->status < 0)
|
||||
printk(KERN_DEBUG "qf_write_async_callback() failed with %d\n", urb->status);
|
||||
|
||||
kfree(req);
|
||||
usb_free_urb(urb);
|
||||
}
|
||||
|
||||
static void qf_write_async_helper(struct usbnet *dev, u8 reg, u8 value, u16 length, void *data)
|
||||
{
|
||||
struct usb_ctrlrequest *req;
|
||||
struct urb *urb;
|
||||
int status;
|
||||
|
||||
urb = usb_alloc_urb(0, GFP_ATOMIC);
|
||||
if (!urb) {
|
||||
deverr(dev, "Error allocating URB in qf_write_async_helper!");
|
||||
return;
|
||||
}
|
||||
|
||||
req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC);
|
||||
if (!req) {
|
||||
deverr(dev, "Failed to allocate memory for control request");
|
||||
usb_free_urb(urb);
|
||||
return;
|
||||
}
|
||||
|
||||
req->bRequestType = QF_REQ_WR_REG;
|
||||
req->bRequest = length ? QF_WR_REGS : QF_WR_REG;
|
||||
req->wValue = cpu_to_le16(value);
|
||||
req->wIndex = cpu_to_le16(reg);
|
||||
req->wLength = cpu_to_le16(length);
|
||||
|
||||
usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
|
||||
(void *)req, data, length,
|
||||
qf_write_async_callback, req);
|
||||
|
||||
status = usb_submit_urb(urb, GFP_ATOMIC);
|
||||
if (status < 0) {
|
||||
deverr(dev, "Error submitting the control message: status=%d",
|
||||
status);
|
||||
kfree(req);
|
||||
usb_free_urb(urb);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void qf_write_async(struct usbnet *dev, u8 reg, u16 length, void *data)
|
||||
{
|
||||
devdbg(dev, "qf_write_async() reg=0x%02x length=%d", reg, length);
|
||||
|
||||
qf_write_async_helper(dev, reg, 0, length, data);
|
||||
}
|
||||
|
||||
static void qf_write_reg_async(struct usbnet *dev, u8 reg, u8 value)
|
||||
{
|
||||
devdbg(dev, "qf_write_reg_async() reg=0x%02x value=0x%02x", reg, value);
|
||||
|
||||
qf_write_async_helper(dev, reg, value, 0, NULL);
|
||||
}
|
||||
|
||||
/* sr9700_android read one word from phy or eeprom */
|
||||
static int qf_share_read_word(struct usbnet *dev, int phy, u8 reg, __le16 *value)
|
||||
{
|
||||
int ret, i;
|
||||
|
||||
mutex_lock(&dev->phy_mutex);
|
||||
|
||||
qf_write_reg(dev, EPAR, phy ? (reg | 0x40) : reg);
|
||||
qf_write_reg(dev, EPCR, phy ? 0xc : 0x4);
|
||||
|
||||
for (i = 0; i < QF_SHARE_TIMEOUT; i++) {
|
||||
u8 tmp;
|
||||
|
||||
udelay(1);
|
||||
ret = qf_read_reg(dev, EPCR, &tmp);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
/* ready */
|
||||
if ((tmp & 1) == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (i >= QF_SHARE_TIMEOUT) {
|
||||
deverr(dev, "%s read timed out!", phy ? "phy" : "eeprom");
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
qf_write_reg(dev, EPCR, 0x0);
|
||||
ret = qf_read(dev, EPDR, 2, value);
|
||||
|
||||
devdbg(dev, "read shared %d 0x%02x returned 0x%04x, %d",
|
||||
phy, reg, *value, ret);
|
||||
|
||||
out:
|
||||
mutex_unlock(&dev->phy_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* write one word to phy or eeprom */
|
||||
static int qf_share_write_word(struct usbnet *dev, int phy, u8 reg, __le16 value)
|
||||
{
|
||||
int ret, i;
|
||||
|
||||
mutex_lock(&dev->phy_mutex);
|
||||
|
||||
ret = qf_write(dev, EPDR, 2, &value);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
qf_write_reg(dev, EPAR, phy ? (reg | 0x40) : reg);
|
||||
qf_write_reg(dev, EPCR, phy ? 0x1a : 0x12);
|
||||
|
||||
for (i = 0; i < QF_SHARE_TIMEOUT; i++) {
|
||||
u8 tmp;
|
||||
|
||||
udelay(1);
|
||||
ret = qf_read_reg(dev, EPCR, &tmp);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
/* ready */
|
||||
if ((tmp & 1) == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (i >= QF_SHARE_TIMEOUT) {
|
||||
deverr(dev, "%s write timed out!", phy ? "phy" : "eeprom");
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
qf_write_reg(dev, EPCR, 0x0);
|
||||
|
||||
out:
|
||||
mutex_unlock(&dev->phy_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qf_read_eeprom_word(struct usbnet *dev, u8 offset, void *value)
|
||||
{
|
||||
return qf_share_read_word(dev, 0, offset, value);
|
||||
}
|
||||
|
||||
|
||||
static int sr9700_android_get_eeprom_len(struct net_device *dev)
|
||||
{
|
||||
return QF_EEPROM_LEN;
|
||||
}
|
||||
|
||||
/* get sr9700_android eeprom information */
|
||||
static int sr9700_android_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, u8 * data)
|
||||
{
|
||||
struct usbnet *dev = netdev_priv(net);
|
||||
__le16 *ebuf = (__le16 *) data;
|
||||
int i;
|
||||
|
||||
/* access is 16bit */
|
||||
if ((eeprom->offset % 2) || (eeprom->len % 2))
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < eeprom->len / 2; i++) {
|
||||
if (qf_read_eeprom_word(dev, eeprom->offset / 2 + i, &ebuf[i]) < 0)
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* sr9700_android mii-phy register read by word */
|
||||
static int sr9700_android_mdio_read(struct net_device *netdev, int phy_id, int loc)
|
||||
{
|
||||
struct usbnet *dev = netdev_priv(netdev);
|
||||
|
||||
__le16 res;
|
||||
|
||||
if (phy_id) {
|
||||
devdbg(dev, "Only internal phy supported");
|
||||
return 0;
|
||||
}
|
||||
|
||||
qf_share_read_word(dev, 1, loc, &res);
|
||||
|
||||
devdbg(dev,
|
||||
"sr9700_android_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x",
|
||||
phy_id, loc, le16_to_cpu(res));
|
||||
|
||||
return le16_to_cpu(res);
|
||||
}
|
||||
|
||||
/* sr9700_android mii-phy register write by word */
|
||||
static void sr9700_android_mdio_write(struct net_device *netdev, int phy_id, int loc, int val)
|
||||
{
|
||||
struct usbnet *dev = netdev_priv(netdev);
|
||||
__le16 res = cpu_to_le16(val);
|
||||
|
||||
if (phy_id) {
|
||||
devdbg(dev, "Only internal phy supported");
|
||||
return;
|
||||
}
|
||||
|
||||
devdbg(dev,"sr9700_android_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x",
|
||||
phy_id, loc, val);
|
||||
|
||||
qf_share_write_word(dev, 1, loc, res);
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------------------------------*/
|
||||
|
||||
static void sr9700_android_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info)
|
||||
{
|
||||
/* Inherit standard device info */
|
||||
usbnet_get_drvinfo(net, info);
|
||||
info->eedump_len = QF_EEPROM_LEN;
|
||||
}
|
||||
|
||||
static u32 sr9700_android_get_link(struct net_device *net)
|
||||
{
|
||||
struct usbnet *dev = netdev_priv(net);
|
||||
int rc = 0;
|
||||
u8 value = 0;
|
||||
|
||||
#if 0
|
||||
rc = mii_link_ok(&dev->mii);
|
||||
#else
|
||||
qf_read_reg(dev, NSR, &value);
|
||||
if(value & NSR_LINKST) {
|
||||
rc = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int sr9700_android_ioctl(struct net_device *net, struct ifreq *rq, int cmd)
|
||||
{
|
||||
struct usbnet *dev = netdev_priv(net);
|
||||
|
||||
return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
|
||||
}
|
||||
|
||||
static const struct ethtool_ops sr9700_android_ethtool_ops = {
|
||||
.get_drvinfo = sr9700_android_get_drvinfo,
|
||||
.get_link = sr9700_android_get_link,
|
||||
.get_msglevel = usbnet_get_msglevel,
|
||||
.set_msglevel = usbnet_set_msglevel,
|
||||
.get_eeprom_len = sr9700_android_get_eeprom_len,
|
||||
.get_eeprom = sr9700_android_get_eeprom,
|
||||
.get_settings = usbnet_get_settings,
|
||||
.set_settings = usbnet_set_settings,
|
||||
.nway_reset = usbnet_nway_reset,
|
||||
};
|
||||
|
||||
static void sr9700_android_set_multicast(struct net_device *net)
|
||||
{
|
||||
struct usbnet *dev = netdev_priv(net);
|
||||
/* We use the 20 byte dev->data for our 8 byte filter buffer
|
||||
* to avoid allocating memory that is tricky to free later */
|
||||
u8 *hashes = (u8 *) & dev->data;
|
||||
u8 rx_ctl = 0x31; // enable, disable_long, disable_crc
|
||||
|
||||
memset(hashes, 0x00, QF_MCAST_SIZE);
|
||||
hashes[QF_MCAST_SIZE - 1] |= 0x80; /* broadcast address */
|
||||
|
||||
if (net->flags & IFF_PROMISC) {
|
||||
rx_ctl |= 0x02;
|
||||
} else if (net->flags & IFF_ALLMULTI || net->mc_count > QF_MCAST_MAX) {
|
||||
rx_ctl |= 0x04;
|
||||
} else if (net->mc_count) {
|
||||
struct dev_mc_list *mc_list = net->mc_list;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < net->mc_count; i++, mc_list = mc_list->next) {
|
||||
u32 crc = ether_crc(ETH_ALEN, mc_list->dmi_addr) >> 26;
|
||||
hashes[crc >> 3] |= 1 << (crc & 0x7);
|
||||
}
|
||||
}
|
||||
|
||||
qf_write_async(dev, MAR, QF_MCAST_SIZE, hashes);
|
||||
qf_write_reg_async(dev, RCR, rx_ctl);
|
||||
}
|
||||
|
||||
static int sr9700_android_set_mac_address(struct net_device *net, void *p)
|
||||
{
|
||||
struct sockaddr *addr = p;
|
||||
struct usbnet *dev = netdev_priv(net);
|
||||
|
||||
if (!is_valid_ether_addr(addr->sa_data)) {
|
||||
dev_err(&net->dev, "not setting invalid mac address %pM\n",
|
||||
addr->sa_data);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
memcpy(net->dev_addr, addr->sa_data, net->addr_len);
|
||||
qf_write_async(dev, PAR, 6, dev->net->dev_addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct net_device_ops sr9700_android_netdev_ops = {
|
||||
.ndo_open = usbnet_open,
|
||||
.ndo_stop = usbnet_stop,
|
||||
.ndo_start_xmit = usbnet_start_xmit,
|
||||
.ndo_tx_timeout = usbnet_tx_timeout,
|
||||
.ndo_change_mtu = usbnet_change_mtu,
|
||||
.ndo_validate_addr = eth_validate_addr,
|
||||
.ndo_do_ioctl = sr9700_android_ioctl,
|
||||
.ndo_set_multicast_list = sr9700_android_set_multicast,
|
||||
.ndo_set_mac_address = sr9700_android_set_mac_address,
|
||||
};
|
||||
|
||||
static int sr9700_android_bind(struct usbnet *dev, struct usb_interface *intf)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = usbnet_get_endpoints(dev, intf);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
dev->net->netdev_ops = &sr9700_android_netdev_ops;
|
||||
dev->net->ethtool_ops = &sr9700_android_ethtool_ops;
|
||||
dev->net->hard_header_len += QF_TX_OVERHEAD;
|
||||
dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
|
||||
dev->rx_urb_size =4096;// dev->net->mtu + ETH_HLEN + QF_RX_OVERHEAD;
|
||||
|
||||
dev->mii.dev = dev->net;
|
||||
dev->mii.mdio_read = sr9700_android_mdio_read;
|
||||
dev->mii.mdio_write = sr9700_android_mdio_write;
|
||||
dev->mii.phy_id_mask = 0x1f;
|
||||
dev->mii.reg_num_mask = 0x1f;
|
||||
|
||||
/* reset the sr9700_android */
|
||||
qf_write_reg(dev, NCR, 1);
|
||||
udelay(20);
|
||||
|
||||
/* read MAC */
|
||||
if (qf_read(dev, PAR, ETH_ALEN, dev->net->dev_addr) < 0) {
|
||||
printk(KERN_ERR "Error reading MAC address\n");
|
||||
ret = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* power up and reset phy */
|
||||
qf_write_reg(dev, PRR, 1);
|
||||
mdelay(20); // at least 10ms, here 20ms for safe
|
||||
qf_write_reg(dev, PRR, 0);
|
||||
udelay(2 * 1000); // at least 1ms, here 2ms for reading right register
|
||||
|
||||
/* receive broadcast packets */
|
||||
sr9700_android_set_multicast(dev->net);
|
||||
|
||||
sr9700_android_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
|
||||
sr9700_android_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
|
||||
mii_nway_restart(&dev->mii);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sr9700_android_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
|
||||
{
|
||||
u8 status;
|
||||
int len;
|
||||
|
||||
/* format:
|
||||
b0: rx status
|
||||
b1: packet length (incl crc) low
|
||||
b2: packet length (incl crc) high
|
||||
b3..n-4: packet data
|
||||
bn-3..bn: ethernet crc
|
||||
*/
|
||||
|
||||
if (unlikely(skb->len < QF_RX_OVERHEAD)) {
|
||||
dev_err(&dev->udev->dev, "unexpected tiny rx frame\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
status = skb->data[0];
|
||||
len = (skb->data[1] | (skb->data[2] << 8)) - 4;
|
||||
|
||||
if (unlikely(status & 0xbf)) {
|
||||
if (status & 0x01) dev->net->stats.rx_fifo_errors++;
|
||||
if (status & 0x02) dev->net->stats.rx_crc_errors++;
|
||||
if (status & 0x04) dev->net->stats.rx_frame_errors++;
|
||||
if (status & 0x20) dev->net->stats.rx_missed_errors++;
|
||||
if (status & 0x90) dev->net->stats.rx_length_errors++;
|
||||
return 0;
|
||||
}
|
||||
|
||||
skb_pull(skb, 3);
|
||||
skb_trim(skb, len);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static struct sk_buff *sr9700_android_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags)
|
||||
{
|
||||
int len;
|
||||
|
||||
/* format:
|
||||
b0: packet length low
|
||||
b1: packet length high
|
||||
b3..n: packet data
|
||||
*/
|
||||
|
||||
len = skb->len;
|
||||
|
||||
if (skb_headroom(skb) < QF_TX_OVERHEAD) {
|
||||
struct sk_buff *skb2;
|
||||
|
||||
skb2 = skb_copy_expand(skb, QF_TX_OVERHEAD, 0, flags);
|
||||
dev_kfree_skb_any(skb);
|
||||
skb = skb2;
|
||||
if (!skb)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
__skb_push(skb, QF_TX_OVERHEAD);
|
||||
|
||||
/* usbnet adds padding if length is a multiple of packet size
|
||||
if so, adjust length value in header */
|
||||
if ((skb->len % dev->maxpacket) == 0)
|
||||
len++;
|
||||
|
||||
skb->data[0] = len;
|
||||
skb->data[1] = len >> 8;
|
||||
|
||||
return skb;
|
||||
}
|
||||
|
||||
static void sr9700_android_status(struct usbnet *dev, struct urb *urb)
|
||||
{
|
||||
int link;
|
||||
u8 *buf;
|
||||
|
||||
/* format:
|
||||
b0: net status
|
||||
b1: tx status 1
|
||||
b2: tx status 2
|
||||
b3: rx status
|
||||
b4: rx overflow
|
||||
b5: rx count
|
||||
b6: tx count
|
||||
b7: gpr
|
||||
*/
|
||||
|
||||
if (urb->actual_length < 8)
|
||||
return;
|
||||
|
||||
buf = urb->transfer_buffer;
|
||||
|
||||
link = !!(buf[0] & 0x40);
|
||||
if (netif_carrier_ok(dev->net) != link) {
|
||||
if (link) {
|
||||
netif_carrier_on(dev->net);
|
||||
usbnet_defer_kevent (dev, EVENT_LINK_RESET);
|
||||
}
|
||||
else
|
||||
netif_carrier_off(dev->net);
|
||||
devdbg(dev, "Link Status is: %d", link);
|
||||
}
|
||||
}
|
||||
|
||||
static int sr9700_android_link_reset(struct usbnet *dev)
|
||||
{
|
||||
struct ethtool_cmd ecmd;
|
||||
|
||||
mii_check_media(&dev->mii, 1, 1);
|
||||
mii_ethtool_gset(&dev->mii, &ecmd);
|
||||
|
||||
devdbg(dev, "link_reset() speed: %d duplex: %d",
|
||||
ecmd.speed, ecmd.duplex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct driver_info sr9700_android_info = {
|
||||
.description = "SR9700_ANDROID USB Ethernet",
|
||||
.flags = FLAG_ETHER,
|
||||
.bind = sr9700_android_bind,
|
||||
.rx_fixup = sr9700_android_rx_fixup,
|
||||
.tx_fixup = sr9700_android_tx_fixup,
|
||||
.status = sr9700_android_status,
|
||||
.link_reset = sr9700_android_link_reset,
|
||||
.reset = sr9700_android_link_reset,
|
||||
};
|
||||
|
||||
static const struct usb_device_id products[] = {
|
||||
{
|
||||
USB_DEVICE(0x0fe6, 0x9700), /* SR9700_ANDROID device */
|
||||
.driver_info = (unsigned long)&sr9700_android_info,
|
||||
},
|
||||
{}, // END
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(usb, products);
|
||||
|
||||
static struct usb_driver sr9700_android_driver = {
|
||||
.name = "SR9700_android",
|
||||
.id_table = products,
|
||||
.probe = usbnet_probe,
|
||||
.disconnect = usbnet_disconnect,
|
||||
.suspend = usbnet_suspend,
|
||||
.resume = usbnet_resume,
|
||||
};
|
||||
|
||||
static int __init sr9700_android_init(void)
|
||||
{
|
||||
return usb_register(&sr9700_android_driver);
|
||||
}
|
||||
|
||||
static void __exit sr9700_android_exit(void)
|
||||
{
|
||||
usb_deregister(&sr9700_android_driver);
|
||||
}
|
||||
|
||||
module_init(sr9700_android_init);
|
||||
module_exit(sr9700_android_exit);
|
||||
|
||||
MODULE_AUTHOR("jokeliu <jokeliu@163.com>");
|
||||
MODULE_DESCRIPTION("SR9700 one chip USB 2.0 ethernet devices on android platform");
|
||||
MODULE_LICENSE("GPL");
|
||||
153
drivers/net/usb/sr9700.h
Executable file
153
drivers/net/usb/sr9700.h
Executable file
@@ -0,0 +1,153 @@
|
||||
/*
|
||||
* Copyright (c) 2009 jokeliu@163.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* Author : jokeliujl <jokeliu@163.com>
|
||||
* Date : 2010-10-01
|
||||
*/
|
||||
|
||||
/* sr9700 spec. register table on android platform */
|
||||
/* Registers */
|
||||
#define NCR 0x00
|
||||
#define NSR 0x01
|
||||
#define TCR 0x02
|
||||
#define TSR1 0x03
|
||||
#define TSR2 0x04
|
||||
#define RCR 0x05
|
||||
#define RSR 0x06
|
||||
#define ROCR 0x07
|
||||
#define BPTR 0x08
|
||||
#define FCTR 0x09
|
||||
#define FCR 0x0A
|
||||
#define EPCR 0x0B
|
||||
#define EPAR 0x0C
|
||||
#define EPDR 0x0D // 0x0D ~ 0x0E
|
||||
#define WCR 0x0F
|
||||
#define PAR 0x10
|
||||
#define MAR 0x16
|
||||
#define PRR 0x1F
|
||||
#define TWPAL 0x20
|
||||
#define TWPAH 0x21
|
||||
#define TRPAL 0x22
|
||||
#define TRPAH 0x23
|
||||
#define RWPAL 0x24
|
||||
#define RWPAH 0x25
|
||||
#define RRPAL 0x26
|
||||
#define RRPAH 0x27
|
||||
#define VID 0x28
|
||||
#define PID 0x2A
|
||||
#define CHIPR 0x2C
|
||||
#define USBDA 0xF0
|
||||
#define RXC 0xF1
|
||||
#define TXC_USBS 0xF2
|
||||
#define USBC 0xF4
|
||||
|
||||
/* Bit definition for registers */
|
||||
// Network Control Reg
|
||||
#define NCR_RST (1 << 0)
|
||||
#define NCR_LBK (3 << 1)
|
||||
#define NCR_FDX (1 << 3)
|
||||
#define NCR_WAKEEN (1 << 6)
|
||||
// Network Status Reg
|
||||
#define NSR_RXRDY (1 << 0)
|
||||
#define NSR_RXOV (1 << 1)
|
||||
#define NSR_TX1END (1 << 2)
|
||||
#define NSR_TX2END (1 << 3)
|
||||
#define NSR_TXFULL (1 << 4)
|
||||
#define NSR_WAKEST (1 << 5)
|
||||
#define NSR_LINKST (1 << 6)
|
||||
#define NSR_SPEED (1 << 7)
|
||||
// Tx Control Reg
|
||||
#define TCR_CRC_DIS (1 << 1)
|
||||
#define TCR_PAD_DIS (1 << 2)
|
||||
#define TCR_LC_CARE (1 << 3)
|
||||
#define TCR_CRS_CARE (1 << 4)
|
||||
#define TCR_EXCECM (1 << 5)
|
||||
#define TCR_LF_EN (1 << 6)
|
||||
// Tx Status Reg for Packet 1
|
||||
#define TSR1_EC (1 << 2)
|
||||
#define TSR1_COL (1 << 3)
|
||||
#define TSR1_LC (1 << 4)
|
||||
#define TSR1_NC (1 << 5)
|
||||
#define TSR1_LOC (1 << 6)
|
||||
#define TSR1_TLF (1 << 7)
|
||||
// Tx Status Reg for Packet 2
|
||||
#define TSR2_EC (1 << 2)
|
||||
#define TSR2_COL (1 << 3)
|
||||
#define TSR2_LC (1 << 4)
|
||||
#define TSR2_NC (1 << 5)
|
||||
#define TSR2_LOC (1 << 6)
|
||||
#define TSR2_TLF (1 << 7)
|
||||
// Rx Control Reg
|
||||
#define RCR_RXEN (1 << 0)
|
||||
#define RCR_PRMSC (1 << 1)
|
||||
#define RCR_RUNT (1 << 2)
|
||||
#define RCR_ALL (1 << 3)
|
||||
#define RCR_DIS_CRC (1 << 4)
|
||||
#define RCR_DIS_LONG (1 << 5)
|
||||
// Rx Status Reg
|
||||
#define RSR_AE (1 << 2)
|
||||
#define RSR_MF (1 << 6)
|
||||
#define RSR_RF (1 << 7)
|
||||
// Recv Overflow Counter Reg
|
||||
#define ROCR_ROC (0x7F << 0)
|
||||
#define ROCR_RXFU (1 << 7)
|
||||
// Back Pressure Threshold Reg
|
||||
#define BPTR_JPT (0x0F << 0)
|
||||
#define BPTR_BPHW (0x0F << 4)
|
||||
// Flow Control Threshold Reg
|
||||
#define FCTR_LWOT (0x0F << 0)
|
||||
#define FCTR_HWOT (0x0F << 4)
|
||||
// rx/tx Flow Control Reg
|
||||
#define FCR_FLCE (1 << 0)
|
||||
#define FCR_BKPA (1 << 4)
|
||||
#define FCR_TXPEN (1 << 5)
|
||||
#define FCR_TXPF (1 << 6)
|
||||
#define FCR_TXP0 (1 << 7)
|
||||
// EEPROM & PHY Control Reg
|
||||
#define EPCR_ERRE (1 << 0)
|
||||
#define EPCR_ERPRW (1 << 1)
|
||||
#define EPCR_ERPRR (1 << 2)
|
||||
#define EPCR_EPOS (1 << 3)
|
||||
#define EPCR_WEP (1 << 4)
|
||||
// EEPROM & PHY Address Reg
|
||||
#define EPAR_EROA (0x3F << 0)
|
||||
#define EPAR_PHY_ADR (0x03 << 6)
|
||||
// Wakeup Control Reg
|
||||
#define WCR_MAGICST (1 << 0)
|
||||
#define WCR_LINKST (1 << 2)
|
||||
#define WCR_MAGICEN (1 << 3)
|
||||
#define WCR_LINKEN (1 << 5)
|
||||
// Phy Reset Reg
|
||||
#define PRR_PHY_RST (1 << 0)
|
||||
// USB Device Address Reg
|
||||
#define USBDA_USBFA (0x7F << 0)
|
||||
// TX packet Counter & USB Status Reg
|
||||
#define TXC_USBS_TXC0 (1 << 0)
|
||||
#define TXC_USBS_TXC1 (1 << 1)
|
||||
#define TXC_USBS_TXC2 (1 << 2)
|
||||
#define TXC_USBS_EP1RDY (1 << 5)
|
||||
#define TXC_USBS_SUSFLAG (1 << 6)
|
||||
#define TXC_USBS_RXFAULT (1 << 7)
|
||||
// USB Control Reg
|
||||
#define USBC_EP3NAK (1 << 4)
|
||||
#define USBC_EP3ACK (1 << 5)
|
||||
|
||||
/* Variables */
|
||||
#define QF_RD_REGS 0x00
|
||||
#define QF_WR_REGS 0x01
|
||||
#define QF_WR_REG 0x03
|
||||
#define QF_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
|
||||
#define QF_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
|
||||
|
||||
#define QF_SHARE_TIMEOUT 1000
|
||||
#define QF_EEPROM_LEN 256
|
||||
#define QF_MCAST_SIZE 8
|
||||
#define QF_MCAST_MAX 64
|
||||
#define QF_TX_OVERHEAD 2 // 2bytes header
|
||||
#define QF_RX_OVERHEAD 7 // 3bytes header + 4crc tail
|
||||
|
||||
/*----------------------------------------------------------------------------------------------*/
|
||||
Reference in New Issue
Block a user