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clk: rockchip: Add clock controller for the RK3576

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Add the clock tree definition for the new RK3576 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I85c05295394032485f146efbaf8aee9044685bfa
This commit is contained in:
Elaine Zhang
2023-05-18 16:26:44 +08:00
committed by Tao Huang
parent 081c3b4917
commit 12fe1aaf5b
4 changed files with 1903 additions and 0 deletions
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7
drivers/clk/rockchip/Kconfig
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@@ -128,6 +128,13 @@ config CLK_RK3568
help
Build the driver for RK3568 Clock Driver.
config CLK_RK3576
tristate "Rockchip RK3576 clock controller support"
depends on CPU_RK3576 || COMPILE_TEST
default y
help
Build the driver for RK3576 Clock Driver.
config CLK_RK3588
tristate "Rockchip RK3588 clock controller support"
depends on CPU_RK3588 || COMPILE_TEST

1
drivers/clk/rockchip/Makefile
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@@ -37,4 +37,5 @@ obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o
obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o
obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o

1843
drivers/clk/rockchip/clk-rk3576.c Normal file
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File diff suppressed because it is too large Load Diff

52
drivers/clk/rockchip/clk.h
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@@ -400,6 +400,58 @@ struct clk;
#define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
#define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
#define RK3576_PHP_CRU_BASE 0x8000
#define RK3576_SECURE_NS_CRU_BASE 0x10000
#define RK3576_PMU_CRU_BASE 0x20000
#define RK3576_BIGCORE_CRU_BASE 0x38000
#define RK3576_LITCORE_CRU_BASE 0x40000
#define RK3576_CCI_CRU_BASE 0x48000
#define RK3576_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3576_MODE_CON0 0x280
#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280)
#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280)
#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280)
#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
#define RK3576_GLB_CNT_TH 0xc00
#define RK3576_GLB_SRST_FST 0xc08
#define RK3576_GLB_SRST_SND 0xc0c
#define RK3576_GLB_RST_CON 0xc10
#define RK3576_GLB_RST_ST 0xc04
#define RK3576_SDIO_CON0 0xC24
#define RK3576_SDIO_CON1 0xC28
#define RK3576_SDMMC_CON0 0xC30
#define RK3576_SDMMC_CON1 0xC34
#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300)
#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800)
#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00)
#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300)
#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800)
#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00)
#define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x300)
#define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x800)
#define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0xa00)
#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300)
#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800)
#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00)
#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300)
#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800)
#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00)
#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE)
#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300)
#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800)
#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00)
#define RK3576_NON_SECURE_GATING_CON00 0xc48
#define RK3588_PHP_CRU_BASE 0x8000
#define RK3588_PMU_CRU_BASE 0x30000
#define RK3588_BIGCORE0_CRU_BASE 0x50000