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Revert "spi: microchip-core: switch to use modern name"

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This reverts commit b39ec657ac which is
commit 8f8bf52ed5b76fc7958b0fbe3131540aecdff8ac upstream.

It breaks the Android kernel abi and can be brought back in the future
in an abi-safe way if it is really needed.

Bug: 161946584
Change-Id: Id0361c629d7c4941f132ac93f035f05fc5bf5099
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman
2024-09-12 15:08:39 +00:00
parent 3dc93ab587
commit 1353c19161
1 changed files with 37 additions and 37 deletions
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74
drivers/spi/spi-microchip-core.c
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@@ -257,7 +257,7 @@ static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, int bt)
static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
{
u32 reg;
struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
struct mchp_corespi *corespi = spi_master_get_devdata(spi->master);
reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);
reg &= ~BIT(spi->chip_select);
@@ -268,11 +268,11 @@ static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)
static int mchp_corespi_setup(struct spi_device *spi)
{
struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
struct mchp_corespi *corespi = spi_master_get_devdata(spi->master);
u32 reg;
/*
* Active high targets need to be specifically set to their inactive
* Active high slaves need to be specifically set to their inactive
* states during probe by adding them to the "control group" & thus
* driving their select line low.
*/
@@ -284,7 +284,7 @@ static int mchp_corespi_setup(struct spi_device *spi)
return 0;
}
static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *spi)
static void mchp_corespi_init(struct spi_master *master, struct mchp_corespi *spi)
{
unsigned long clk_hz;
u32 control = mchp_corespi_read(spi, REG_CONTROL);
@@ -298,7 +298,7 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *
/* max. possible spi clock rate is the apb clock rate */
clk_hz = clk_get_rate(spi->clk);
host->max_speed_hz = clk_hz;
master->max_speed_hz = clk_hz;
/*
* The controller must be configured so that it doesn't remove Chip
@@ -318,7 +318,7 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *
/*
* It is required to enable direct mode, otherwise control over the chip
* select is relinquished to the hardware. SSELOUT is enabled too so we
* can deal with active high targets.
* can deal with active high slaves.
*/
mchp_corespi_write(spi, REG_SLAVE_SELECT, SSELOUT | SSEL_DIRECT);
@@ -383,8 +383,8 @@ static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int
static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)
{
struct spi_controller *host = dev_id;
struct mchp_corespi *spi = spi_controller_get_devdata(host);
struct spi_master *master = dev_id;
struct mchp_corespi *spi = spi_master_get_devdata(master);
u32 intfield = mchp_corespi_read(spi, REG_MIS) & 0xf;
bool finalise = false;
@@ -408,7 +408,7 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)
if (intfield & INT_RX_CHANNEL_OVERFLOW) {
mchp_corespi_write(spi, REG_INT_CLEAR, INT_RX_CHANNEL_OVERFLOW);
finalise = true;
dev_err(&host->dev,
dev_err(&master->dev,
"%s: RX OVERFLOW: rxlen: %d, txlen: %d\n", __func__,
spi->rx_len, spi->tx_len);
}
@@ -416,13 +416,13 @@ static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)
if (intfield & INT_TX_CHANNEL_UNDERRUN) {
mchp_corespi_write(spi, REG_INT_CLEAR, INT_TX_CHANNEL_UNDERRUN);
finalise = true;
dev_err(&host->dev,
dev_err(&master->dev,
"%s: TX UNDERFLOW: rxlen: %d, txlen: %d\n", __func__,
spi->rx_len, spi->tx_len);
}
if (finalise)
spi_finalize_current_transfer(host);
spi_finalize_current_transfer(master);
return IRQ_HANDLED;
}
@@ -464,16 +464,16 @@ static int mchp_corespi_calculate_clkgen(struct mchp_corespi *spi,
return 0;
}
static int mchp_corespi_transfer_one(struct spi_controller *host,
static int mchp_corespi_transfer_one(struct spi_master *master,
struct spi_device *spi_dev,
struct spi_transfer *xfer)
{
struct mchp_corespi *spi = spi_controller_get_devdata(host);
struct mchp_corespi *spi = spi_master_get_devdata(master);
int ret;
ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz);
if (ret) {
dev_err(&host->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz);
dev_err(&master->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz);
return ret;
}
@@ -494,11 +494,11 @@ static int mchp_corespi_transfer_one(struct spi_controller *host,
return 1;
}
static int mchp_corespi_prepare_message(struct spi_controller *host,
static int mchp_corespi_prepare_message(struct spi_master *master,
struct spi_message *msg)
{
struct spi_device *spi_dev = msg->spi;
struct mchp_corespi *spi = spi_controller_get_devdata(host);
struct mchp_corespi *spi = spi_master_get_devdata(master);
mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);
mchp_corespi_set_mode(spi, spi_dev->mode);
@@ -508,32 +508,32 @@ static int mchp_corespi_prepare_message(struct spi_controller *host,
static int mchp_corespi_probe(struct platform_device *pdev)
{
struct spi_controller *host;
struct spi_master *master;
struct mchp_corespi *spi;
struct resource *res;
u32 num_cs;
int ret = 0;
host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));
if (!host)
master = devm_spi_alloc_master(&pdev->dev, sizeof(*spi));
if (!master)
return dev_err_probe(&pdev->dev, -ENOMEM,
"unable to allocate host for SPI controller\n");
"unable to allocate master for SPI controller\n");
platform_set_drvdata(pdev, host);
platform_set_drvdata(pdev, master);
if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))
num_cs = MAX_CS;
host->num_chipselect = num_cs;
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
host->setup = mchp_corespi_setup;
host->bits_per_word_mask = SPI_BPW_MASK(8);
host->transfer_one = mchp_corespi_transfer_one;
host->prepare_message = mchp_corespi_prepare_message;
host->set_cs = mchp_corespi_set_cs;
host->dev.of_node = pdev->dev.of_node;
master->num_chipselect = num_cs;
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
master->setup = mchp_corespi_setup;
master->bits_per_word_mask = SPI_BPW_MASK(8);
master->transfer_one = mchp_corespi_transfer_one;
master->prepare_message = mchp_corespi_prepare_message;
master->set_cs = mchp_corespi_set_cs;
master->dev.of_node = pdev->dev.of_node;
spi = spi_controller_get_devdata(host);
spi = spi_master_get_devdata(master);
spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(spi->regs))
@@ -546,7 +546,7 @@ static int mchp_corespi_probe(struct platform_device *pdev)
spi->irq);
ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt,
IRQF_SHARED, dev_name(&pdev->dev), host);
IRQF_SHARED, dev_name(&pdev->dev), master);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"could not request irq\n");
@@ -561,25 +561,25 @@ static int mchp_corespi_probe(struct platform_device *pdev)
return dev_err_probe(&pdev->dev, ret,
"failed to enable clock\n");
mchp_corespi_init(host, spi);
mchp_corespi_init(master, spi);
ret = devm_spi_register_controller(&pdev->dev, host);
ret = devm_spi_register_master(&pdev->dev, master);
if (ret) {
mchp_corespi_disable(spi);
clk_disable_unprepare(spi->clk);
return dev_err_probe(&pdev->dev, ret,
"unable to register host for SPI controller\n");
"unable to register master for SPI controller\n");
}
dev_info(&pdev->dev, "Registered SPI controller %d\n", host->bus_num);
dev_info(&pdev->dev, "Registered SPI controller %d\n", master->bus_num);
return 0;
}
static int mchp_corespi_remove(struct platform_device *pdev)
{
struct spi_controller *host = platform_get_drvdata(pdev);
struct mchp_corespi *spi = spi_controller_get_devdata(host);
struct spi_master *master = platform_get_drvdata(pdev);
struct mchp_corespi *spi = spi_master_get_devdata(master);
mchp_corespi_disable_ints(spi);
clk_disable_unprepare(spi->clk);