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pinctrl:modify bank0 reg_base

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luowei
2014-03-20 19:53:50 +08:00
parent d4a27bc6fc
commit 13ff4a4289
2 changed files with 6 additions and 6 deletions
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6
arch/arm/boot/dts/rk3288-pinctrl.dtsi
View File

@@ -17,9 +17,9 @@
gpio0: gpio0@ff750000 {
compatible = "rockchip,rk3288-gpio-bank0";
reg = <0xff750000 0x100>,
<0xff730080 0x10>,
<0xff730060 0x0c>,
<0xff73006c 0x0c>;
<0xff730084 0x10>,
<0xff730064 0x0c>,
<0xff730070 0x0c>;
reg-names = "base", "mux_bank0", "pull_bank0", "drv_bank0";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates17 4>;

6
drivers/pinctrl/pinctrl-rockchip.c
View File

@@ -616,7 +616,7 @@ static int rockchip_set_rk32_mux(struct rockchip_pin_bank *bank, int pin, int mu
case 0:
//pmu
reg = bank->reg_mux_bank0;
reg += RK3288_GRF_GPIO0_A_IOMUX;
//reg += RK3288_GRF_GPIO0_A_IOMUX;
bits = 2;
rk32_iomux_bit_op(bank, pin, mux, reg, bits);
break;
@@ -1055,7 +1055,7 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = pin_num % 8;
*bit *= 2;
} else {
*reg = info->reg_pull;
*reg = info->reg_pull - 0x10;
*reg += bank->bank_num * 0x10;
*reg += ((pin_num / 8) * 4);
@@ -1079,7 +1079,7 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = pin_num % 8;
*bit *= 2;
} else {
*reg = info->reg_drv;
*reg = info->reg_drv - 0x10;
*reg += bank->bank_num * 0x10;
*reg += ((pin_num / 8) * 4);