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clk: rockchip: rk3399: add 65M for PLL freq

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VPLL need 65M freq for some HDMI display.

Change-Id: I4f07c97282fb48fc504b54a07838ccb0bbb0355a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2016-06-21 15:18:00 +08:00
committed by zhangqing
parent be05bd7727
commit 1439310696
1 changed files with 1 additions and 0 deletions
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drivers/clk/rockchip/clk-rk3399.c
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@@ -102,6 +102,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
{ /* sentinel */ },