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vpp code style modify [1/1]

Browse Source 
PD#SWPL-59491

Problem:
vpp code style modify

Solution:
vpp code style modify

Verify:
sm1

Signed-off-by: yao liu <yao.liu@amlogic.com>
Change-Id: I0ff44f15d441413a70366d86cabaee69a73587f7
This commit is contained in:
yao liu
2021-10-19 11:35:17 +08:00
committed by Chris
parent 5e9e5f621b
commit 1473adce54
7 changed files with 225 additions and 9753 deletions
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8926
drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c
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File diff suppressed because it is too large Load Diff

594
drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.h
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@@ -17,188 +17,8 @@
#ifndef _AMDV_H_
#define _AMDV_H_
#define V1_5
#define V2_4
/* driver version */
#define DRIVER_VER "20181220"
#include <linux/types.h>
#define DEF_G2L_LUT_SIZE_2P 8
#define DEF_G2L_LUT_SIZE (1 << DEF_G2L_LUT_SIZE_2P)
#ifdef V2_4
#define EXT_MD_AVAIL_LEVEL_1 (1 << 0)
#define EXT_MD_AVAIL_LEVEL_2 (1 << 1)
#define EXT_MD_AVAIL_LEVEL_4 (1 << 2)
#define EXT_MD_AVAIL_LEVEL_5 (1 << 3)
#define EXT_MD_AVAIL_LEVEL_6 (1 << 4)
#define EXT_MD_AVAIL_LEVEL_255 (1 << 31)
#endif
#define PQ2G_LUT_SIZE (4 + 1024 * 4 + 16 * 3)
#define GM_LUT_HDR_SIZE (13 + 2*9)
#define LUT_DIM 17
#define GM_LUT_SIZE (3 * LUT_DIM * LUT_DIM * LUT_DIM * 2)
#define BACLIGHT_LUT_SIZE 4096
#define TUNING_LUT_ENTRIES 14
#define TUNINGMODE_FORCE_ABSOLUTE 0x1
#define TUNINGMODE_EXTLEVEL1_DISABLE 0x2
#define TUNINGMODE_EXTLEVEL2_DISABLE 0x4
#define TUNINGMODE_EXTLEVEL4_DISABLE 0x8
#define TUNINGMODE_EXTLEVEL5_DISABLE 0x10
#define TUNINGMODE_EL_FORCEDDISABLE 0x20
enum core1_switch_type {
NO_SWITCH = 0,
SWITCH_BEFORE_DVCORE_1,
SWITCH_BEFORE_DVCORE_2,
SWITCH_AFTER_DVCORE,
};
enum core3_switch_type {
CORE3_AFTER_WM = 0,
CORE3_AFTER_OSD1_HDR,
CORE3_AFTER_VD2_HDR,
};
/*! @brief Output CSC configuration.*/
# pragma pack(push, 1)
struct TgtOutCscCfg {
int32_t lms2RgbMat[3][3]; /**<@brief LMS to RGB matrix */
int32_t lms2RgbMatScale; /**<@brief LMS 2 RGB matrix scale */
uint8_t whitePoint[3]; /**<@brief White point */
uint8_t whitePointScale; /**<@brief White point scale */
int32_t reserved[3];
};
#pragma pack(pop)
/*! @brief Global dimming configuration.*/
# pragma pack(push, 1)
struct TgtGDCfg {
int32_t gdEnable;
uint32_t gdWMin;
uint32_t gdWMax;
uint32_t gdWMm;
uint32_t gdWDynRngSqrt;
uint32_t gdWeightMean;
uint32_t gdWeightStd;
uint32_t gdDelayMilliSec_hdmi;
int32_t gdRgb2YuvExt;
int32_t gdM33Rgb2Yuv[3][3];
int32_t gdM33Rgb2YuvScale2P;
int32_t gdRgb2YuvOffExt;
int32_t gdV3Rgb2YuvOff[3];
uint32_t gdUpBound;
uint32_t gdLowBound;
uint32_t lastMaxPq;
uint16_t gdWMinPq;
uint16_t gdWMaxPq;
uint16_t gdWMmPq;
uint16_t gdTriggerPeriod;
uint32_t gdTriggerLinThresh;
uint32_t gdDelayMilliSec_ott;
#ifdef V1_5
uint32_t reserved[6];
#else
uint32_t reserved[9];
#endif
};
#pragma pack(pop)
/*! @defgroup general Enumerations and data structures*/
# pragma pack(push, 1)
struct TargetDisplayConfig {
uint16_t gain;
uint16_t offset;
uint16_t gamma; /**<@brief Gamma */
uint16_t eotf;
uint16_t bitDepth; /**<@brief Bit Depth */
uint16_t rangeSpec;
uint16_t diagSize; /**<@brief Diagonal Size */
uint16_t maxPq;
uint16_t minPq;
uint16_t mSWeight;
uint16_t mSEdgeWeight;
int16_t minPQBias;
int16_t midPQBias;
int16_t maxPQBias;
int16_t trimSlopeBias;
int16_t trimOffsetBias;
int16_t trimPowerBias;
int16_t msWeightBias;
int16_t brightness; /**<@brief Brighness */
int16_t contrast; /**<@brief Contrast */
int16_t chromaWeightBias;
int16_t saturationGainBias;
uint16_t chromaWeight;
uint16_t saturationGain;
uint16_t crossTalk;
uint16_t tuningMode;
int16_t reserved0;
int16_t dbgExecParamsPrintPeriod;
int16_t dbgDmMdPrintPeriod;
int16_t dbgDmCfgPrintPeriod;
uint16_t maxPq_dupli;
uint16_t minPq_dupli;
int32_t keyWeight;
int32_t intensityVectorWeight;
int32_t chromaVectorWeight;
int16_t chip_fpga_lowcomplex;
int16_t midPQBiasLut[TUNING_LUT_ENTRIES];
int16_t saturationGainBiasLut[TUNING_LUT_ENTRIES];
int16_t chromaWeightBiasLut[TUNING_LUT_ENTRIES];
int16_t slopeBiasLut[TUNING_LUT_ENTRIES];
int16_t offsetBiasLut[TUNING_LUT_ENTRIES];
int16_t backlightBiasLut[TUNING_LUT_ENTRIES];
struct TgtGDCfg gdConfig;
#ifdef V1_5
uint8_t vsvdb[7];
uint8_t reserved1[5];
#endif
int32_t min_lin;
int32_t max_lin;
int16_t backlight_scaler;
int32_t min_lin_dupli;
int32_t max_lin_dupli;
struct TgtOutCscCfg ocscConfig;
#ifdef V1_5
int16_t reserved2;
#else
int16_t reserved00;
#endif
int16_t brightnessPreservation;
int32_t iintensityVectorWeight;
int32_t ichromaVectorWeight;
int16_t isaturationGainBias;
int16_t chip_12b_ocsc;
int16_t chip_512_tonecurve;
int16_t chip_nolvl5;
int16_t padding[8];
};
#pragma pack(pop)
/*! @brief PQ config main data structure.*/
struct pq_config_s {
unsigned char default_gm_lut[GM_LUT_HDR_SIZE + GM_LUT_SIZE];
unsigned char gd_gm_lut_min[GM_LUT_HDR_SIZE + GM_LUT_SIZE];
unsigned char gd_gm_lut_max[GM_LUT_HDR_SIZE + GM_LUT_SIZE];
unsigned char pq2gamma[sizeof(int32_t)*PQ2G_LUT_SIZE];
unsigned char backlight_lut[BACLIGHT_LUT_SIZE];
struct TargetDisplayConfig target_display_config;
};
enum input_mode_e {
INPUT_MODE_OTT = 0,
INPUT_MODE_HDMI = 1
};
struct ui_menu_params_s {
uint16_t u16BackLightUIVal;
uint16_t u16BrightnessUIVal;
uint16_t u16ContrastUIVal;
};
enum signal_format_e {
FORMAT_INVALID = -1,
FORMAT_DOVI = 0,
@@ -211,337 +31,6 @@ enum signal_format_e {
FORMAT_MVC = 7
};
enum priority_mode_e {
VIDEO_PRIORITY = 0,
GRAPHIC_PRIORITY = 1,
/* same as video priority, but will only switch to video*/
/* priority after scene refresh flag has been received */
VIDEO_PRIORITY_DELAYED = 2
};
enum cp_signal_range_e {
SIG_RANGE_SMPTE = 0, /* head range */
SIG_RANGE_FULL = 1, /* full range */
SIG_RANGE_SDI = 2 /* PQ */
};
enum graphics_format_e {
GF_SDR_YUV = 0, /* BT.709 YUV BT1886 */
GF_SDR_RGB = 1, /* BT.709 RGB BT1886 */
GF_HDR_YUV = 2, /* BT.2020 YUV PQ */
GF_HDR_RGB = 3 /* BT.2020 RGB PQ */
};
struct run_mode_s {
uint16_t width;
uint16_t height;
uint16_t el_width;
uint16_t el_height;
uint16_t hdmi_mode;
};
struct composer_register_ipcore_s {
/* offset 0xc8 */
uint32_t Composer_Mode;
uint32_t VDR_Resolution;
uint32_t Bit_Depth;
uint32_t Coefficient_Log2_Denominator;
uint32_t BL_Num_Pivots_Y;
uint32_t BL_Pivot[5];
uint32_t BL_Order;
uint32_t BL_Coefficient_Y[8][3];
uint32_t EL_NLQ_Offset_Y;
uint32_t EL_Coefficient_Y[3];
uint32_t Mapping_IDC_U;
uint32_t BL_Num_Pivots_U;
uint32_t BL_Pivot_U[3];
uint32_t BL_Order_U;
uint32_t BL_Coefficient_U[4][3];
uint32_t MMR_Coefficient_U[22][2];
uint32_t MMR_Order_U;
uint32_t EL_NLQ_Offset_U;
uint32_t EL_Coefficient_U[3];
uint32_t Mapping_IDC_V;
uint32_t BL_Num_Pivots_V;
uint32_t BL_Pivot_V[3];
uint32_t BL_Order_V;
uint32_t BL_Coefficient_V[4][3];
uint32_t MMR_Coefficient_V[22][2];
uint32_t MMR_Order_V;
uint32_t EL_NLQ_Offset_V;
uint32_t EL_Coefficient_V[3];
};
/** @brief DM registers for IPCORE 1 */
struct dm_register_ipcore_1_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Frame_Format_1;
uint32_t Frame_Format_2;
uint32_t Frame_Pixel_Def;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t EOTF;
/* uint32_t Sparam_1;*/
/* uint32_t Sparam_2;*/
/* uint32_t Sgamma; */
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
uint32_t C2D_Offset;
uint32_t Active_area_left_top;
uint32_t Active_area_bottom_right;
};
/** @brief DM registers for IPCORE 2 */
struct dm_register_ipcore_2_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t Frame_Format;
uint32_t EOTF;
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
uint32_t C2D_Offset;
uint32_t VDR_Resolution;
};
/** @brief DM registers for IPCORE 3 */
struct dm_register_ipcore_3_s {
uint32_t D2C_coefficient_1;
uint32_t D2C_coefficient_2;
uint32_t D2C_coefficient_3;
uint32_t D2C_coefficient_4;
uint32_t D2C_coefficient_5;
uint32_t B2A_Coefficient_1;
uint32_t B2A_Coefficient_2;
uint32_t B2A_Coefficient_3;
uint32_t B2A_Coefficient_4;
uint32_t B2A_Coefficient_5;
uint32_t Eotf_param_1;
uint32_t Eotf_param_2;
uint32_t IPT_Scale;
uint32_t IPT_Offset_1;
uint32_t IPT_Offset_2;
uint32_t IPT_Offset_3;
uint32_t Output_range_1;
uint32_t Output_range_2;
uint32_t RGB2YUV_coefficient_register1;
uint32_t RGB2YUV_coefficient_register2;
uint32_t RGB2YUV_coefficient_register3;
uint32_t RGB2YUV_coefficient_register4;
uint32_t RGB2YUV_coefficient_register5;
uint32_t RGB2YUV_offset_0;
uint32_t RGB2YUV_offset_1;
uint32_t RGB2YUV_offset_2;
};
/** @brief DM luts for IPCORE 1 and 2 */
struct dm_lut_ipcore_s {
uint32_t TmLutI[64*4];
uint32_t TmLutS[64*4];
uint32_t SmLutI[64*4];
uint32_t SmLutS[64*4];
uint32_t G2L[DEF_G2L_LUT_SIZE];
};
/** @brief hdmi metadata for IPCORE 3 */
struct md_reister_ipcore_3_s {
uint32_t raw_metadata[512];
uint32_t size;
};
struct hdr_10_infoframe_s {
uint8_t infoframe_type_code;
uint8_t infoframe_version_number;
uint8_t length_of_info_frame;
uint8_t data_byte_1;
uint8_t data_byte_2;
uint8_t display_primaries_x_0_LSB;
uint8_t display_primaries_x_0_MSB;
uint8_t display_primaries_y_0_LSB;
uint8_t display_primaries_y_0_MSB;
uint8_t display_primaries_x_1_LSB;
uint8_t display_primaries_x_1_MSB;
uint8_t display_primaries_y_1_LSB;
uint8_t display_primaries_y_1_MSB;
uint8_t display_primaries_x_2_LSB;
uint8_t display_primaries_x_2_MSB;
uint8_t display_primaries_y_2_LSB;
uint8_t display_primaries_y_2_MSB;
uint8_t white_point_x_LSB;
uint8_t white_point_x_MSB;
uint8_t white_point_y_LSB;
uint8_t white_point_y_MSB;
uint8_t max_display_mastering_luminance_LSB;
uint8_t max_display_mastering_luminance_MSB;
uint8_t min_display_mastering_luminance_LSB;
uint8_t min_display_mastering_luminance_MSB;
uint8_t max_content_light_level_LSB;
uint8_t max_content_light_level_MSB;
uint8_t max_frame_average_light_level_LSB;
uint8_t max_frame_average_light_level_MSB;
};
struct hdr10_param_s {
uint32_t min_display_mastering_luminance;
uint32_t max_display_mastering_luminance;
uint16_t Rx;
uint16_t Ry;
uint16_t Gx;
uint16_t Gy;
uint16_t Bx;
uint16_t By;
uint16_t Wx;
uint16_t Wy;
uint16_t max_content_light_level;
uint16_t max_pic_average_light_level;
};
#ifdef V2_4
struct ext_level_1_s {
uint8_t min_PQ_hi;
uint8_t min_PQ_lo;
uint8_t max_PQ_hi;
uint8_t max_PQ_lo;
uint8_t avg_PQ_hi;
uint8_t avg_PQ_lo;
};
struct ext_level_2_s {
uint8_t target_max_PQ_hi;
uint8_t target_max_PQ_lo;
uint8_t trim_slope_hi;
uint8_t trim_slope_lo;
uint8_t trim_offset_hi;
uint8_t trim_offset_lo;
uint8_t trim_power_hi;
uint8_t trim_power_lo;
uint8_t trim_chroma_weight_hi;
uint8_t trim_chroma_weight_lo;
uint8_t trim_saturation_gain_hi;
uint8_t trim_saturation_gain_lo;
uint8_t ms_weight_hi;
uint8_t ms_weight_lo;
};
struct ext_level_4_s {
uint8_t anchor_PQ_hi;
uint8_t anchor_PQ_lo;
uint8_t anchor_power_hi;
uint8_t anchor_power_lo;
};
struct ext_level_5_s {
uint8_t active_area_left_offset_hi;
uint8_t active_area_left_offset_lo;
uint8_t active_area_right_offset_hi;
uint8_t active_area_right_offset_lo;
uint8_t active_area_top_offset_hi;
uint8_t active_area_top_offset_lo;
uint8_t active_area_bottom_offset_hi;
uint8_t active_area_bottom_offset_lo;
};
struct ext_level_6_s {
uint8_t max_display_mastering_luminance_hi;
uint8_t max_display_mastering_luminance_lo;
uint8_t min_display_mastering_luminance_hi;
uint8_t min_display_mastering_luminance_lo;
uint8_t max_content_light_level_hi;
uint8_t max_content_light_level_lo;
uint8_t max_frame_average_light_level_hi;
uint8_t max_frame_average_light_level_lo;
};
struct ext_level_255_s {
uint8_t dm_run_mode;
uint8_t dm_run_version;
uint8_t dm_debug0;
uint8_t dm_debug1;
uint8_t dm_debug2;
uint8_t dm_debug3;
};
struct ext_md_s {
uint32_t available_level_mask;
struct ext_level_1_s level_1;
struct ext_level_2_s level_2;
struct ext_level_4_s level_4;
struct ext_level_5_s level_5;
struct ext_level_6_s level_6;
struct ext_level_255_s level_255;
};
#endif
struct dovi_setting_s {
struct composer_register_ipcore_s comp_reg;
struct dm_register_ipcore_1_s dm_reg1;
struct dm_register_ipcore_2_s dm_reg2;
struct dm_register_ipcore_3_s dm_reg3;
struct dm_lut_ipcore_s dm_lut1;
struct dm_lut_ipcore_s dm_lut2;
/* for dovi output */
struct md_reister_ipcore_3_s md_reg3;
/* for hdr10 output */
struct hdr_10_infoframe_s hdr_info;
/* current process */
enum signal_format_e src_format;
enum signal_format_e dst_format;
/* enhanced layer */
bool el_flag;
bool el_halfsize_flag;
/* frame width & height */
uint32_t video_width;
uint32_t video_height;
#ifdef V2_4
/* use for stb 2.4 */
enum graphics_format_e g_format;
uint32_t g_bitdepth;
uint32_t dovi2hdr10_nomapping;
uint32_t use_ll_flag;
uint32_t ll_rgb_desired;
uint32_t diagnostic_enable;
uint32_t diagnostic_mux_select;
uint32_t dovi_ll_enable;
uint32_t vout_width;
uint32_t vout_height;
u8 vsvdb_tbl[32];
struct ext_md_s ext_md;
uint32_t vsvdb_len;
uint32_t vsvdb_changed;
uint32_t mode_changed;
#endif
};
enum cpuID_e {
_CPU_MAJOR_ID_GXM,
_CPU_MAJOR_ID_TXLX,
@@ -562,89 +51,6 @@ struct amdolby_vision_port_t {
void *runtime;
};
extern int control_path(
enum signal_format_e in_format,
enum signal_format_e out_format,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
enum priority_mode_e set_priority,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
int set_graphic_min_lum, int set_graphic_max_lum,
int set_target_min_lum, int set_target_max_lum,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct dovi_setting_s *output);
struct tv_dovi_setting_s {
uint64_t core1_reg_lut[3754];
/* current process */
enum signal_format_e src_format;
enum signal_format_e dst_format;
/* enhanced layer */
bool el_flag;
bool el_halfsize_flag;
/* frame width & height */
uint32_t video_width;
uint32_t video_height;
enum input_mode_e input_mode;
};
extern int tv_control_path(
enum signal_format_e in_format,
enum input_mode_e in_mode,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
struct pq_config_s *pq_config,
struct ui_menu_params_s *menu_param,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct tv_dovi_setting_s *output);
extern void *metadata_parser_init(int flag);
extern int metadata_parser_reset(int flag);
extern int metadata_parser_process(
char *src_rpu, int rpu_len,
char *dst_comp, int *comp_len,
char *dst_md, int *md_len, bool src_eos);
extern void metadata_parser_release(void);
struct dolby_vision_func_s {
const char *version_info;
void * (*metadata_parser_init)(int flag);
int (*metadata_parser_reset)(int flag);
int (*metadata_parser_process)(
char *src_rpu, int rpu_len,
char *dst_comp, int *comp_len,
char *dst_md, int *md_len, bool src_eos);
void (*metadata_parser_release)(void);
int (*control_path)(
enum signal_format_e in_format,
enum signal_format_e out_format,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
enum priority_mode_e set_priority,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
int set_graphic_min_lum, int set_graphic_max_lum,
int set_target_min_lum, int set_target_max_lum,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct dovi_setting_s *output);
int (*tv_control_path)(
enum signal_format_e in_format,
enum input_mode_e in_mode,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
struct pq_config_s *pq_config,
struct ui_menu_params_s *menu_param,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct tv_dovi_setting_s *output);
};
extern int register_dv_functions(const struct dolby_vision_func_s *func);
extern int unregister_dv_functions(void);
#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val)
#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr)

133
drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h
View File

@@ -116,138 +116,5 @@
#define VPP_DOLBY_CTRL 0x1d93
#define VIU_SW_RESET 0x1a01
#define VPU_HDMI_FMT_CTRL 0x2743
#if 0
/* core 1 display manager 24 registers */
struct dm_register_ipcore_1_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Frame_Format_1;
uint32_t Frame_Format_2;
uint32_t Frame_Pixel_Def;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t EOTF;
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
};
/* core 1 composer 173 registers */
struct composer_register_ipcore_s {
uint32_t Composer_Mode;
uint32_t VDR_Resolution;
uint32_t Bit_Depth;
uint32_t Coefficient_Log2_Denominator;
uint32_t BL_Num_Pivots_Y;
uint32_t BL_Pivot[5];
uint32_t BL_Order;
uint32_t BL_Coefficient_Y[8][3];
uint32_t EL_NLQ_Offset_Y;
uint32_t EL_Coefficient_Y[3];
uint32_t Mapping_IDC_U;
uint32_t BL_Num_Pivots_U;
uint32_t BL_Pivot_U[3];
uint32_t BL_Order_U;
uint32_t BL_Coefficient_U[4][3];
uint32_t MMR_Coefficient_U[22][2];
uint32_t MMR_Order_U;
uint32_t EL_NLQ_Offset_U;
uint32_t EL_Coefficient_U[3];
uint32_t Mapping_IDC_V;
uint32_t BL_Num_Pivots_V;
uint32_t BL_Pivot_V[3];
uint32_t BL_Order_V;
uint32_t BL_Coefficient_V[4][3];
uint32_t MMR_Coefficient_V[22][2];
uint32_t MMR_Order_V;
uint32_t EL_NLQ_Offset_V;
uint32_t EL_Coefficient_V[3];
};
/* core 2 display manager 24 registers */
struct dm_register_ipcore_2_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t Frame_Format;
uint32_t EOTF;
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
uint32_t C2D_Offset;
uint32_t VDR_Resolution;
};
/* core 3 display manager 26 registers */
struct dm_register_ipcore_3_s {
uint32_t D2C_coefficient_1;
uint32_t D2C_coefficient_2;
uint32_t D2C_coefficient_3;
uint32_t D2C_coefficient_4;
uint32_t D2C_coefficient_5;
uint32_t B2A_Coefficient_1;
uint32_t B2A_Coefficient_2;
uint32_t B2A_Coefficient_3;
uint32_t B2A_Coefficient_4;
uint32_t B2A_Coefficient_5;
uint32_t Eotf_param_1;
uint32_t Eotf_param_2;
uint32_t IPT_Scale;
uint32_t IPT_Offset_1;
uint32_t IPT_Offset_2;
uint32_t IPT_Offset_3;
uint32_t Output_range_1;
uint32_t Output_range_2;
uint32_t RGB2YUV_coefficient_register1;
uint32_t RGB2YUV_coefficient_register2;
uint32_t RGB2YUV_coefficient_register3;
uint32_t RGB2YUV_coefficient_register4;
uint32_t RGB2YUV_coefficient_register5;
uint32_t RGB2YUV_offset_0;
uint32_t RGB2YUV_offset_1;
uint32_t RGB2YUV_offset_2;
};
/* lut 5 * 256 for core 1 and core 2 */
struct dm_lut_ipcore_s {
uint32_t TmLutI[64*4];
uint32_t TmLutS[64*4];
uint32_t SmLutI[64*4];
uint32_t SmLutS[64*4];
uint32_t G2L[256];
};
/* core 3 metadata 128 registers */
struct md_reister_ipcore_3_s {
uint32_t raw_metadata[128];
};
#endif
#endif

240
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/dv_emp_vsem.c
View File

@@ -54,9 +54,9 @@
#include "dv_emp_vsem.h"
#undef pr_fmt
#define pr_fmt(fmt) "dvemp: " fmt
#define pr_fmt(fmt) "emp: " fmt
static unsigned int crc32_lut[256] = {
static unsigned int crc32_lut_table[256] = {
0x00000000, 0x04c11db7, 0x09823b6e, 0x0d4326d9, 0x130476dc, 0x17c56b6b,
0x1a864db2, 0x1e475005, 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61,
0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd, 0x4c11db70, 0x48d0c6c7,
@@ -102,47 +102,44 @@ static unsigned int crc32_lut[256] = {
0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4
};
void SetByteField(unsigned char *meta_byte,
unsigned char field_value,
unsigned char field_mask)
void set_byte(unsigned char *meta,
unsigned char value,
unsigned char mask)
{
unsigned int count;
unsigned int test_val;
unsigned int set_val;
unsigned char test_mask;
test_mask = field_mask;
test_mask = mask;
count = 0;
while ((test_mask > 0) && (count < 8)) {
test_val = 1 << count;
if ((test_val & field_mask) == test_val) {
set_val = (field_value & 1);
field_value >>= 1;
if ((test_val & mask) == test_val) {
set_val = (value & 1);
value >>= 1;
if (set_val > 0)
*meta_byte |= 1 << count;
*meta |= 1 << count;
else
*meta_byte &= ~(1 << count);
*meta &= ~(1 << count);
test_mask &= ~(1 << count);
}
count++;
}
}
/* given metadata length, figure out how many packets are needed */
unsigned int vsem_get_num_packets(unsigned int metadata_len,
unsigned int *last_packet_len)
u32 get_vsem_pkt_num(u32 metadata_len, u32 *last_packet_len)
{
unsigned int num_packets = 1;
u32 num_packets = 1;
if (metadata_len == 0)
return 0;
/* how many packets are needed */
*last_packet_len = metadata_len;
if (*last_packet_len > VSEM_FIRST_PACKET_EDR_DATA_LEN) {
*last_packet_len -= VSEM_FIRST_PACKET_EDR_DATA_LEN;
while (*last_packet_len > VSEM_PACKET_BODY_LEN) {
*last_packet_len -= VSEM_PACKET_BODY_LEN;
if (*last_packet_len > VSEM_FIRST_PKT_EDR_DATA_SIZE) {
*last_packet_len -= VSEM_FIRST_PKT_EDR_DATA_SIZE;
while (*last_packet_len > VSEM_PKT_BODY_SIZE) {
*last_packet_len -= VSEM_PKT_BODY_SIZE;
num_packets++;
}
if (*last_packet_len > 0)
@@ -152,13 +149,13 @@ unsigned int vsem_get_num_packets(unsigned int metadata_len,
return num_packets;
}
unsigned int crc32(unsigned int crc, const void *buf, unsigned int size)
unsigned int get_crc32(u32 crc, const void *buf, u32 size)
{
const unsigned char *p = (unsigned char *)buf;
const u8 *p = (u8 *)buf;
crc = ~crc;
while (size) {
crc = (crc << 8) ^ crc32_lut[((crc >> 24) ^ *p) & 0xff];
crc = (crc << 8) ^ crc32_lut_table[((crc >> 24) ^ *p) & 0xff];
p++;
size--;
}
@@ -171,10 +168,10 @@ static int pack_vsemds(struct emp_edr_config *pconfig,
int metadata_len,
unsigned char data_version)
{
struct vsem_data_packet *cur_packet;
struct vsem_pkt *cur_pkt;
int count, acrc_loc, frt_loc;
unsigned int p;
unsigned int num_packets = 1;
unsigned int num_pkts = 1;
unsigned int last_packet_len = 0;
unsigned int cur_packet_len;
unsigned int crc;
@@ -183,128 +180,127 @@ static int pack_vsemds(struct emp_edr_config *pconfig,
unsigned char PB0;
unsigned char HB1;
edr_data_len = metadata_len + VSEM_CRC_LENGTH;
edr_data_len = metadata_len + VSEM_CRC_LEN;
pcrcfrt = NULL;
/* how many packets are needed */
num_packets = vsem_get_num_packets(edr_data_len, &last_packet_len);
if (num_packets > MAX_VSEM_NUM)
num_pkts = get_vsem_pkt_num(edr_data_len, &last_packet_len);
if (num_pkts > MAX_VSEM_NUM)
pr_info("vsem metada_len is too big\n");
/* allocate packets memory */
pconfig->num_packets = num_packets;
pconfig->num_packets = num_pkts;
if (pconfig->vsem_packets == NULL) {
pr_info("vsem_packets don't alloc\n");
return -1;
}
memset(pconfig->vsem_packets, 0,
sizeof(struct vsem_data_packet) * num_packets);
memset(pconfig->vsem_packets, 0, sizeof(struct vsem_pkt) * num_pkts);
/*compute CRC*/
crc = crc32(0, p_metadata, metadata_len);
crc = get_crc32(0, p_metadata, metadata_len);
/* process the first packet */
/* first pkt */
p = 0;
cur_packet = &pconfig->vsem_packets[p];
pcrc = cur_packet->PB;
cur_packet->packet_type = 0x7F;
cur_pkt = &pconfig->vsem_packets[p];
pcrc = cur_pkt->pb;
cur_pkt->pkt_type = 0x7F;
HB1 = 0;
SetByteField(&HB1, 1, FIELD_MASK_FIRST);
SetByteField(&HB1, 0, FIELD_MASK_LAST);
cur_packet->HB1 = HB1;
cur_packet->sequence_index = p;
set_byte(&HB1, 1, FIELD_FIRST);
set_byte(&HB1, 0, FIELD_LAST);
cur_pkt->hb1 = HB1;
cur_pkt->seq_index = p;
edr_data_len += 6; /* PB0~12 */
PB0 = 0;
SetByteField(&PB0, 1, FIELD_MASK_NEW);
SetByteField(&PB0, 1, FIELD_MASK_END);
SetByteField(&PB0, 2, FIELD_MASK_DS_TYPE);
SetByteField(&PB0, 1, FIELD_MASK_AFR);
SetByteField(&PB0, 1, FIELD_MASK_VFR);
SetByteField(&PB0, 1, FIELD_MASK_SYNC);
cur_packet->PB[0] = PB0;
cur_packet->PB[1] = 0x00; /* Reserved */
cur_packet->PB[2] = 0x00; /* Organization ID */
cur_packet->PB[3] = 0x00; /* Data Set Tag hi = 0 */
cur_packet->PB[4] = 0x00; /* Data Set Tag low = 0 */
cur_packet->PB[5] = edr_data_len >> 8; /* Data Set Length hi */
cur_packet->PB[6] = edr_data_len & 0xff; /* Data Set Length low */
cur_packet->PB[7] = 0x46; /* MD0 */
cur_packet->PB[8] = 0xD0; /* MD1 */
cur_packet->PB[9] = 0x00; /* MD2 */
cur_packet->PB[10] = data_version; /* data_version */
cur_packet->PB[11] = 0x00; /* Reserved */
cur_packet->PB[12] = 0x00; /* Reserved */
cur_packet_len = VSEM_FIRST_PACKET_EDR_DATA_LEN;
set_byte(&PB0, 1, FIELD_NEW);
set_byte(&PB0, 1, FIELD_END);
set_byte(&PB0, 2, FIELD_DS_TYPE);
set_byte(&PB0, 1, FIELD_AFR);
set_byte(&PB0, 1, FIELD_VFR);
set_byte(&PB0, 1, FIELD_SYNC);
cur_pkt->pb[0] = PB0;
cur_pkt->pb[1] = 0x00;
cur_pkt->pb[2] = 0x00;
cur_pkt->pb[3] = 0x00;
cur_pkt->pb[4] = 0x00;
cur_pkt->pb[5] = edr_data_len >> 8;
cur_pkt->pb[6] = edr_data_len & 0xff;
cur_pkt->pb[7] = 0x46;
cur_pkt->pb[8] = 0xD0;
cur_pkt->pb[9] = 0x00;
cur_pkt->pb[10] = data_version;
cur_pkt->pb[11] = 0x00;
cur_pkt->pb[12] = 0x00;
cur_packet_len = VSEM_FIRST_PKT_EDR_DATA_SIZE;
if (cur_packet_len > metadata_len)
cur_packet_len = metadata_len;
memcpy(&cur_packet->PB[13], p_metadata, cur_packet_len);
pcrc = &cur_packet->PB[13];
memcpy(&cur_pkt->pb[13], p_metadata, cur_packet_len);
pcrc = &cur_pkt->pb[13];
p_metadata += cur_packet_len;
metadata_len -= cur_packet_len;
num_packets--;
num_pkts--;
p++;
/* process following packets */
while (num_packets > 0) {
/*other pkts */
while (num_pkts > 0) {
if (p == 1)
frt_loc = 13 + cur_packet_len - 1;
else
frt_loc = cur_packet_len - 1;
pcrcfrt =
&pconfig->vsem_packets[p - 1].PB[frt_loc];
cur_packet = &pconfig->vsem_packets[p];
cur_packet->packet_type = 0x7F;
&pconfig->vsem_packets[p - 1].pb[frt_loc];
cur_pkt = &pconfig->vsem_packets[p];
cur_pkt->pkt_type = 0x7F;
HB1 = 0x00;
SetByteField(&HB1, 0, FIELD_MASK_FIRST);
if (num_packets == 1) {
SetByteField(&HB1, 1, FIELD_MASK_LAST);
set_byte(&HB1, 0, FIELD_FIRST);
if (num_pkts == 1) {
set_byte(&HB1, 1, FIELD_LAST);
cur_packet_len = last_packet_len;
} else {
SetByteField(&HB1, 0, FIELD_MASK_LAST);
cur_packet_len = VSEM_PACKET_BODY_LEN;
set_byte(&HB1, 0, FIELD_LAST);
cur_packet_len = VSEM_PKT_BODY_SIZE;
}
cur_packet->HB1 = HB1;
cur_packet->sequence_index = (unsigned char)p;
cur_pkt->hb1 = HB1;
cur_pkt->seq_index = (unsigned char)p;
if (metadata_len > 0) {
if (metadata_len >= cur_packet_len) {
memcpy(cur_packet->PB, p_metadata, cur_packet_len);
memcpy(cur_pkt->pb,
p_metadata, cur_packet_len);
metadata_len -= cur_packet_len;
p_metadata += cur_packet_len;
} else {
memcpy(cur_packet->PB, p_metadata, metadata_len);
memcpy(cur_pkt->pb,
p_metadata, metadata_len);
p_metadata += metadata_len;
metadata_len = 0;
}
}
pcrc = &cur_packet->PB[0];
num_packets--;
pcrc = &cur_pkt->pb[0];
num_pkts--;
p++;
}
/*write CRC*/
/*crc*/
acrc[0] = (crc & 0xff000000) >> 24;
acrc[1] = (crc & 0xff0000) >> 16;
acrc[2] = (crc & 0xff00) >> 8;
acrc[3] = crc & 0xff;
if (last_packet_len >= VSEM_CRC_LENGTH) {
pcrc += last_packet_len - VSEM_CRC_LENGTH;
if (last_packet_len >= VSEM_CRC_LEN) {
pcrc += last_packet_len - VSEM_CRC_LEN;
for (count = 0; count < 4; count++) {
pcrc[count] = acrc[count];
}
} else {
if (pcrcfrt != NULL) {
/*last packet*/
pcrc = &cur_packet->PB[0];
/*last pkt*/
pcrc = &cur_pkt->pb[0];
for (count = last_packet_len - 1;
count >= 0;
count--) {
/*VSEM_CRC_LENGTH - 1 - (last_packet_len - 1 - count)*/
acrc_loc = VSEM_CRC_LENGTH - last_packet_len + count;
/*LEN - 1 - (last_packet_len - 1 - count)*/
acrc_loc = VSEM_CRC_LEN -
last_packet_len + count;
pcrc[count] = acrc[acrc_loc];
}
/*the packet before last packet*/
pcrcfrt -= VSEM_CRC_LENGTH - last_packet_len;
/*the pkt before last pkt*/
pcrcfrt -= VSEM_CRC_LEN - last_packet_len;
pcrcfrt++;
for (count = 0;
count < VSEM_CRC_LENGTH - last_packet_len;
count < VSEM_CRC_LEN - last_packet_len;
count++) {
pcrcfrt[count] = acrc[count];
}
@@ -313,25 +309,25 @@ static int pack_vsemds(struct emp_edr_config *pconfig,
return 0;
}
static struct dv_emp_hdmi_cfg dv_emp_cfg_val;
static void hdmitx_set_dv_emp_pkt(struct emp_edr_config *pconfig)
static struct emp_hdmi_cfg emp_cfg_val;
static void hdmitx_set_emp_pkt(struct emp_edr_config *pconfig)
{
struct hdmitx_dev *hdev;
hdev = dv_emp_cfg_val.hdev;
hdev = emp_cfg_val.hdev;
hdev->hwop.cntlconfig(hdev, CONF_EMP_PHY_ADDR, pconfig->phys_ptr);
hdev->hwop.cntlconfig(hdev, CONF_EMP_NUMBER, pconfig->num_packets);
}
static void hdmitx_disable_dv_emp_pkt(void)
static void hdmitx_disable_emp_pkt(void)
{
struct hdmitx_dev *hdev;
hdev = dv_emp_cfg_val.hdev;
hdev = emp_cfg_val.hdev;
hdev->hwop.cntlconfig(hdev, CONF_EMP_NUMBER, 0);
}
static void hdmitx_emp_dv_infoframe(struct hdmitx_dev *hdev,
static void hdmitx_emp_infoframe(struct hdmitx_dev *hdev,
enum eotf_type type,
enum eotf_type type_save,
bool signal_sdr)
@@ -385,7 +381,7 @@ static void hdmitx_emp_dv_infoframe(struct hdmitx_dev *hdev,
}
}
int send_dv_emp(enum eotf_type type,
int send_emp(enum eotf_type type,
enum mode_type tunnel_mode,
struct dv_vsif_para *vsif_data,
unsigned char *p_vsem,
@@ -394,7 +390,7 @@ int send_dv_emp(enum eotf_type type,
{
struct emp_edr_config config;
int rv;
struct hdmitx_dev *hdev = dv_emp_cfg_val.hdev;
struct hdmitx_dev *hdev = emp_cfg_val.hdev;
unsigned char data_version = 0;
static enum eotf_type type_save = EOTF_T_NULL;
static bool vsem_flag = false;
@@ -417,12 +413,12 @@ int send_dv_emp(enum eotf_type type,
pr_info("EMP hdmitx_set_vsif_pkt: type = %d\n", type);
hdr_status_pos = 2;
hdev->hdmi_current_eotf_type = type;
hdmitx_emp_dv_infoframe(hdev, type, type_save, signal_sdr);
hdmitx_emp_infoframe(hdev, type, type_save, signal_sdr);
type_save = type;
if ((type != EOTF_T_DOLBYVISION) &&
(type != EOTF_T_LL_MODE)) {
if (vsem_flag == true) { /*exit from Dolby VS-EMDS*/
hdmitx_disable_dv_emp_pkt();
hdmitx_disable_emp_pkt();
} else { /*exit from Dolby VSIF*/
hdmitx_set_vsif_pkt(type, tunnel_mode, vsif_data, signal_sdr);
}
@@ -441,36 +437,36 @@ int send_dv_emp(enum eotf_type type,
dma_sync_single_for_cpu(
hdev->hdtx_dev,
dv_emp_cfg_val.pkts_phy_addr,
dv_emp_cfg_val.size,
emp_cfg_val.pkts_phy_addr,
emp_cfg_val.size,
DMA_TO_DEVICE);
config.num_packets = 0;
config.phys_ptr = dv_emp_cfg_val.pkts_phy_addr;
config.vsem_packets = dv_emp_cfg_val.p_pkts;
config.phys_ptr = emp_cfg_val.pkts_phy_addr;
config.vsem_packets = emp_cfg_val.p_pkts;
rv = pack_vsemds(&config, p_vsem, vsem_len, data_version);
if (rv != 0) {
pr_info("pack_vsem fail!\n");
return -1;
}
/*Disable Dolby VSIF send*/
/*Disable VSIF send*/
hdev->hwop.setpacket(HDMI_PACKET_VEND, NULL, NULL);
/*Enable Dolby VS-EMDS send*/
/*Enable VS-EMDS send*/
dma_sync_single_for_device(
hdev->hdtx_dev,
dv_emp_cfg_val.pkts_phy_addr,
dv_emp_cfg_val.size,
emp_cfg_val.pkts_phy_addr,
emp_cfg_val.size,
DMA_TO_DEVICE);
hdmitx_set_dv_emp_pkt(&config);
} else { /*Dolby VSIF or HDMI 14b VSIF*/
hdmitx_set_emp_pkt(&config);
} else {
vsem_flag = false;
/*Disable Dolby VS-EMDS send*/
hdmitx_disable_dv_emp_pkt();
/*Enable Dolby VSIF send*/
/*Disable VS-EMDS send*/
hdmitx_disable_emp_pkt();
/*Enable VSIF send*/
hdmitx_set_vsif_pkt(type, tunnel_mode, vsif_data, signal_sdr);
}
return 1;
}
EXPORT_SYMBOL(send_dv_emp);
EXPORT_SYMBOL(send_emp);
void vsem_init_cfg(struct hdmitx_dev *hdev)
{
@@ -478,7 +474,7 @@ void vsem_init_cfg(struct hdmitx_dev *hdev)
void *virt_ptr;
dma_addr_t paddr;
alloc_len = sizeof(struct vsem_data_packet) * MAX_VSEM_NUM;
alloc_len = sizeof(struct vsem_pkt) * MAX_VSEM_NUM;
alloc_size = (alloc_len + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
virt_ptr = kmalloc(alloc_size, GFP_KERNEL | GFP_DMA);
@@ -494,9 +490,9 @@ void vsem_init_cfg(struct hdmitx_dev *hdev)
return;
}
dv_emp_cfg_val.hdev = hdev;
dv_emp_cfg_val.p_pkts = (struct vsem_data_packet *)virt_ptr;
dv_emp_cfg_val.pkts_phy_addr = paddr;
dv_emp_cfg_val.size = alloc_size;
dv_emp_cfg_val.send_vsemds = send_dv_emp;
emp_cfg_val.hdev = hdev;
emp_cfg_val.p_pkts = (struct vsem_pkt *)virt_ptr;
emp_cfg_val.pkts_phy_addr = paddr;
emp_cfg_val.size = alloc_size;
emp_cfg_val.send_vsemds = send_emp;
}

45
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/dv_emp_vsem.h
View File

@@ -20,44 +20,41 @@
#ifndef _EDR_METADATA_OVER_HDMI_H_
#define _EDR_METADATA_OVER_HDMI_H_
#define VSEM_CRC_LENGTH 4
#define VSIF_PAYLOAD_LEN 24
#define VSEM_PACKET_BODY_LEN 28
#define VSEM_FIRST_PACKET_EDR_DATA_LEN 15
#define VSEM_PKT_BODY_SIZE 28
#define VSEM_FIRST_PKT_EDR_DATA_SIZE 15
#define VSEM_CRC_LEN 4
struct vsem_data_packet {
unsigned char packet_type;
unsigned char HB1;
unsigned char sequence_index;
unsigned char PB[VSEM_PACKET_BODY_LEN];
struct vsem_pkt {
unsigned char pkt_type;
unsigned char hb1;
unsigned char seq_index;
unsigned char pb[VSEM_PKT_BODY_SIZE];
unsigned char padding;
};
#define MAX_VSEM_NUM 128
#define MAX_VSEM_SIZE (MAX_VSEM_NUM * sizeof(struct vsem_data_packet))
#define MAX_VSEM_SIZE (MAX_VSEM_NUM * sizeof(struct vsem_pkt))
/* header field masks */
/* second header byte */
#define FIELD_MASK_FIRST 0x80
#define FIELD_MASK_LAST 0x40
#define FIELD_FIRST 0x80
#define FIELD_LAST 0x40
/* packet field masks */
/* first packet byte */
#define FIELD_MASK_NEW 0x80
#define FIELD_MASK_END 0x40
#define FIELD_MASK_DS_TYPE 0x30
#define FIELD_MASK_AFR 0x08
#define FIELD_MASK_VFR 0x04
#define FIELD_MASK_SYNC 0x02
#define FIELD_NEW 0x80
#define FIELD_END 0x40
#define FIELD_DS_TYPE 0x30
#define FIELD_AFR 0x08
#define FIELD_VFR 0x04
#define FIELD_SYNC 0x02
struct emp_edr_config {
struct vsem_data_packet *vsem_packets;
struct vsem_pkt *vsem_packets;
unsigned long phys_ptr;
unsigned int num_packets;
};
struct dv_emp_hdmi_cfg {
struct emp_hdmi_cfg {
struct hdmitx_dev *hdev;
struct vsem_data_packet *p_pkts;
struct vsem_pkt *p_pkts;
dma_addr_t pkts_phy_addr;
size_t size;
int (*send_vsemds)(enum eotf_type type,

38
include/linux/amlogic/media/amdolbyvision/dolby_vision.h
View File

@@ -18,9 +18,6 @@
#ifndef _DV_H_
#define _DV_H_
#define V1_5
#define V2_4
#include <linux/types.h>
#include <linux/amlogic/media/vout/vinfo.h>
#include <linux/amlogic/media/vfm/vframe.h>
@@ -49,10 +46,13 @@
/* else bypass Dolby Vision */
#define DOLBY_VISION_FORCE_OUTPUT_MODE 2
#define MUTE_TYPE_NONE 0
#define MUTE_TYPE_YUV 1
#define MUTE_TYPE_RGB 2
#define MUTE_TYPE_IPT 3
#define MD_BUF_SIZE 1024
#define COMP_BUF_SIZE 8196
#define DV_SEI 0x01000000
#define DV_AV1_SEI 0x14000000
#define HDR10P 0x02000000
void enable_dolby_vision(int enable);
bool is_dolby_vision_enable(void);
@@ -80,9 +80,6 @@ void dolby_vision_update_pq_config(
char *pq_config_buf);
int dolby_vision_update_setting(void);
bool is_dolby_vision_stb_mode(void);
void tv_dolby_vision_crc_clear(int flag);
char *tv_dolby_vision_get_crc(u32 *len);
void tv_dolby_vision_insert_crc(bool print);
int dolby_vision_check_hdr10(struct vframe_s *vf);
int dolby_vision_check_hlg(struct vframe_s *vf);
int dolby_vision_check_hdr10plus(struct vframe_s *vf);
@@ -94,8 +91,6 @@ int dolby_vision_parse_metadata(
bool bypass_release, bool drop_flag);
void dolby_vision_update_vsvdb_config(
char *vsvdb_buf, u32 tbl_size);
void tv_dolby_vision_el_info(void);
int enable_rgb_to_yuv_matrix_for_dvll(
int32_t on, uint32_t *coeff_orig, uint32_t bits);
@@ -108,8 +103,23 @@ bool is_dolby_vision_el_disable(void);
bool is_dovi_dual_layer_frame(struct vframe_s *vf);
void dolby_vision_set_provider(char *prov_name);
int dolby_vision_check_mvc(struct vframe_s *vf);
bool for_dolby_vision_video_effect(void);
int get_dolby_vision_hdr_policy(void);
int get_dv_support_info(void);
void dv_vf_light_reg_provider(void);
void dv_vf_light_unreg_provider(void);
void dolby_vision_update_backlight(void);
int dolby_vision_update_src_format(struct vframe_s *vf, u8 toggle_mode);
int parse_sei_and_meta_ext
(struct vframe_s *vf,
char *aux_buf,
int aux_size,
int *total_comp_size,
int *total_md_size,
void *fmt,
int *ret_flags,
char *md_buf,
char *comp_buf);
void dolby_vision_clear_buf(void);
bool is_dv_control_backlight(void);
#endif

2
include/linux/amlogic/media/vout/vinfo.h
View File

@@ -264,7 +264,7 @@ struct vout_device_s {
unsigned int size);
};
extern int send_dv_emp(enum eotf_type type,
int send_emp(enum eotf_type type,
enum mode_type tunnel_mode,
struct dv_vsif_para *vsif_data,
unsigned char *p_vsem,