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ODROID-N2: clk: Update pll table to support 1.992GHz

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Change-Id: Idb3565bb3e9f17950b9320c50fb5faf6564d1ef9
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Joy Cho
2019-06-04 14:08:22 +09:00
committed by Dongjin Kim
parent 987b4949fd
commit 14a5bf4602
1 changed files with 1 additions and 0 deletions
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drivers/amlogic/clk/g12a/g12a.h
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@@ -156,6 +156,7 @@ static const struct pll_rate_table g12a_pll_rate_table[] = {
PLL_RATE(1896000000ULL, 158, 1, 1), /*DCO=3792M*/
PLL_RATE(1908000000ULL, 159, 1, 1), /*DCO=3816M*/
PLL_RATE(1920000000ULL, 160, 1, 1), /*DCO=3840M*/
PLL_RATE(1992000000ULL, 166, 1, 1), /*DCO=3984M*/
PLL_RATE(2004000000ULL, 167, 1, 1), /*DCO=4008M*/
PLL_RATE(2016000000ULL, 168, 1, 1), /*DCO=4032M*/
PLL_RATE(2100000000ULL, 175, 1, 1), /*DCO=4200M*/