clk: rockchip: Add clock controller for the RK3528

Add the clock tree definition for the new RK3528 SoC.

gmac1 clocks are all controlled by GRF, but CRU helps to abstract
these two clocks for gmac1 since the clock source is from CRU.

The io-in clocks are module phy output clock, gating child
clocks by disabling phy output but not CRU gate.

Add gmac0 clocks.
They are all orphans if clk_gmac0_io_i is not registered by
GMAC driver. But it's fine that GMAC driver only get it but
not to set/get rate.

Add CLK_SET_RATE_PARENT for mclk_sai_i2s0/1.
Allowed to change parent rate.

Add CLK_SET_RATE_NO_REPARENT for dclk_vop0.
dclk_vop0 is often used for HDMI, it prefers parent clock from
clk_hdmiphy_pixel_io for better clock quality and any rate.
It assigns clk_hdmiphy_pixel_io as parent in dts and hope not to
change parent any more.

Add CLK_SET_RATE_PARENT for aclk_gpu.
Allow aclk_gpu and aclk_gpu_mali to change parent rate.

Add CLK_SET_RATE_PARENT for aclk_rkvdec_pvtmux_root.
Allow aclk_rkvdec_pvtmux_root and aclk_rkvdec to change parent rate.

set aclk_m_core = core_clk/2.
aclk_m_core signoff is 550M, but we set div=2 for better
performance.

Add CLK_IS_CRITICAL for clk_32k.
Mainly for pvtpll during reboot stage.

Add CLK_IS_CRITICAL for all IOC clocks.
IOC doesn't share clock with GRF. The iomux can't be changed if they
are disabled.

Disable aclk_{vpu,vpu_l,vo}_root rate change
They are all shared by multiple modules, disable rate change
by modules.

Don't register clk_uart_jtag
It's for force jtag uart delay counter. It must be open
for box product without tf card but with uart0.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I09745b6a31484d6a27f04e608268d9738c1fe224

drivers/clk/rockchip/Kconfig

@@ -107,6 +107,13 @@ config CLK_RK3399
 	help
 	  Build the driver for RK3399 Clock Driver.
 
+config CLK_RK3528
+	tristate "Rockchip RK3528 clock controller support"
+	depends on CPU_RK3528 || COMPILE_TEST
+	default y
+	help
+	  Build the driver for RK3528 Clock Driver.
+
 config CLK_RK3568
 	tristate "Rockchip RK3568 clock controller support"
 	depends on CPU_RK3568 || COMPILE_TEST

drivers/clk/rockchip/Makefile

@@ -33,5 +33,6 @@ obj-$(CONFIG_CLK_RK3308)        += clk-rk3308.o
 obj-$(CONFIG_CLK_RK3328)        += clk-rk3328.o
 obj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o
 obj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o
+obj-$(CONFIG_CLK_RK3528)        += clk-rk3528.o
 obj-$(CONFIG_CLK_RK3568)        += clk-rk3568.o
 obj-$(CONFIG_CLK_RK3588)	+= clk-rk3588.o

drivers/clk/rockchip/clk.h

@@ -304,6 +304,34 @@ struct clk;
 #define RK3399_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x100)
 #define RK3399_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x110)
 
+#define RK3528_PMU_CRU_BASE		0x10000
+#define RK3528_PCIE_CRU_BASE		0x20000
+#define RK3528_DDRPHY_CRU_BASE		0x28000
+#define RK3528_VPU_GRF_BASE		0x40000
+#define RK3528_VO_GRF_BASE		0x60000
+#define RK3528_SDMMC_CON0		(RK3528_VO_GRF_BASE + 0x24)
+#define RK3528_SDMMC_CON1		(RK3528_VO_GRF_BASE + 0x28)
+#define RK3528_SDIO0_CON0		(RK3528_VPU_GRF_BASE + 0x4)
+#define RK3528_SDIO0_CON1		(RK3528_VPU_GRF_BASE + 0x8)
+#define RK3528_SDIO1_CON0		(RK3528_VPU_GRF_BASE + 0xc)
+#define RK3528_SDIO1_CON1		(RK3528_VPU_GRF_BASE + 0x10)
+#define RK3528_PLL_CON(x)		RK2928_PLL_CON(x)
+#define RK3528_PCIE_PLL_CON(x)		((x) * 0x4 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_PLL_CON(x)	((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_MODE_CON			0x280
+#define RK3528_CLKSEL_CON(x)		((x) * 0x4 + 0x300)
+#define RK3528_CLKGATE_CON(x)		((x) * 0x4 + 0x800)
+#define RK3528_SOFTRST_CON(x)		((x) * 0x4 + 0xa00)
+#define RK3528_PMU_CLKSEL_CON(x)	((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
+#define RK3528_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
+#define RK3528_PCIE_CLKSEL_CON(x)	((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
+#define RK3528_PCIE_CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_DDRPHY_MODE_CON		(0x280 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_GLB_CNT_TH		0xc00
+#define RK3528_GLB_SRST_FST		0xc08
+#define RK3528_GLB_SRST_SND		0xc0c
+
 #define RK3568_PLL_CON(x)		RK2928_PLL_CON(x)
 #define RK3568_MODE_CON0		0xc0
 #define RK3568_MISC_CON0		0xc4