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dv: fix black screen when connecting dv TV [1/1]
PD#SWPL-7778 Problem: black sreen when connecting dv TV Solution: close post matrix open tm2 dv flag Verify: T962E2 Change-Id: I828b32d7bf2ef35c3f236ad9bf15964272d06dd2 Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>
This commit is contained in:
@@ -497,7 +497,7 @@
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gamma_en = <1>;/*1:enabel ;0:disable*/
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wb_en = <1>;/*1:enabel ;0:disable*/
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cm_en = <0>;/*1:enabel ;0:disable*/
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wb_sel = <1>;/*1:mtx ;0:gainoff*/
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wb_sel = <0>;/*1:mtx ;0:gainoff*/
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vlock_en = <1>;/*1:enable;0:disable*/
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vlock_mode = <0x4>;
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/* vlock work mode:
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@@ -493,7 +493,7 @@
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gamma_en = <1>;/*1:enabel ;0:disable*/
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wb_en = <1>;/*1:enabel ;0:disable*/
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cm_en = <0>;/*1:enabel ;0:disable*/
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wb_sel = <1>;/*1:mtx ;0:gainoff*/
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wb_sel = <0>;/*1:mtx ;0:gainoff*/
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vlock_en = <1>;/*1:enable;0:disable*/
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vlock_mode = <0x4>;
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/* vlock work mode:
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@@ -491,7 +491,7 @@
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gamma_en = <1>;/*1:enabel ;0:disable*/
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wb_en = <1>;/*1:enabel ;0:disable*/
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cm_en = <0>;/*1:enabel ;0:disable*/
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wb_sel = <1>;/*1:mtx ;0:gainoff*/
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wb_sel = <0>;/*1:mtx ;0:gainoff*/
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vlock_en = <1>;/*1:enable;0:disable*/
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vlock_mode = <0x4>;
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/* vlock work mode:
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@@ -492,7 +492,7 @@
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gamma_en = <1>;/*1:enabel ;0:disable*/
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wb_en = <1>;/*1:enabel ;0:disable*/
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cm_en = <0>;/*1:enabel ;0:disable*/
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wb_sel = <1>;/*1:mtx ;0:gainoff*/
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wb_sel = <0>;/*1:mtx ;0:gainoff*/
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vlock_en = <1>;/*1:enable;0:disable*/
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vlock_mode = <0x4>;
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/* vlock work mode:
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@@ -1139,14 +1139,14 @@ bool is_meson_tvmode(void)
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return false;
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}
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static u32 addr_map(u32 adr)
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{
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u32 CORE1_BASE = 0;
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u32 CORE1_1_BASE = 0;
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u32 CORE2A_BASE = 0;
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u32 CORE3_BASE = 0;
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u32 CORETV_BASE = 0;
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static u32 CORE1_BASE;
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static u32 CORE1_1_BASE;
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static u32 CORE2A_BASE;
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static u32 CORE3_BASE;
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static u32 CORETV_BASE;
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static void dolby_vision_addr(void)
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{
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if (is_meson_gxm() || is_meson_g12()) {
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CORE1_BASE = 0x3300;
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CORE2A_BASE = 0x3400;
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@@ -1162,6 +1162,9 @@ static u32 addr_map(u32 adr)
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CORE3_BASE = 0x3600;
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CORETV_BASE = 0x4300;
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}
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}
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static u32 addr_map(u32 adr)
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{
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if (adr & CORE1_OFFSET)
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adr = (adr & 0xffff) + CORE1_BASE;
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@@ -2371,7 +2374,6 @@ static int dolby_core3_set(
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VSYNC_WR_DV_REG(DOLBY_CORE3_REG_START + 1, cur_dv_mode);
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VSYNC_WR_DV_REG(DOLBY_CORE3_REG_START + 1, cur_dv_mode);
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/* for delay */
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if (dm_count == 0)
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count = 26;
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else
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@@ -2408,7 +2410,7 @@ static int dolby_core3_set(
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if ((dolby_vision_flags & FLAG_CERTIFICAION)
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&& !(dolby_vision_flags & FLAG_DISABLE_CRC))
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VSYNC_WR_DV_REG(0x36fb, 1);
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VSYNC_WR_DV_REG(DOLBY_CORE3_CRC_CTRL, 1);
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/* enable core3 */
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VSYNC_WR_DV_REG(DOLBY_CORE3_SWAP_CTRL0, (dolby_enable << 0));
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return 0;
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@@ -6022,10 +6024,8 @@ int dolby_vision_process(struct vframe_s *vf, u32 display_size,
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if (!is_meson_box() && !is_meson_txlx() && !is_meson_tm2())
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return -1;
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if ((dolby_vision_enable == 1) && (tv_mode == 1)) {
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if ((dolby_vision_enable == 1) && (tv_mode == 1))
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amdolby_vision_wakeup_queue();
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pr_dolby_dbg("wake up dv status queue\n");
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}
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if (dolby_vision_flags & FLAG_CERTIFICAION) {
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if (vf) {
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@@ -6059,13 +6059,13 @@ int dolby_vision_process(struct vframe_s *vf, u32 display_size,
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ott_mode =
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(tv_dovi_setting->input_mode !=
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INPUT_MODE_HDMI);
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if ((is_meson_txlx_stbmode()
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|| is_meson_box()
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|| force_stb_mode)
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if ((is_meson_txlx_stbmode() ||
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is_meson_tm2_stbmode() ||
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is_meson_box() || force_stb_mode)
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&& (setting_update_count == 1)
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&& (crc_read_delay == 1)) {
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/* work around to enable crc for frame 0 */
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VSYNC_WR_DV_REG(0x36fb, 1);
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VSYNC_WR_DV_REG(DOLBY_CORE3_CRC_CTRL, 1);
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crc_read_delay++;
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} else {
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crc_read_delay++;
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@@ -6945,7 +6945,7 @@ static int amdolby_vision_probe(struct platform_device *pdev)
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ret = PTR_ERR(devp->dev);
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goto fail_create_device;
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}
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dolby_vision_addr();
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dolby_vision_init_receiver(pdev);
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init_waitqueue_head(&devp->dv_queue);
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pr_info("%s: ok\n", __func__);
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@@ -3912,7 +3912,7 @@ static struct osd_device_data_s osd_tm2 = {
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.has_deband = 1,
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.has_lut = 1,
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.has_rdma = 1,
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.has_dolby_vision = 0,
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.has_dolby_vision = 1,
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.osd_fifo_len = 64, /* fifo len 64*8 = 512 */
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.vpp_fifo_len = 0xfff,/* 2048 */
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.dummy_data = 0x00808000,
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