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drm/rockchip: vop: add vop full series of vop support

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The series of vop is:
IP version    chipname
3.1           rk3288
3.2           rk3368
3.4           rk3366
3.5           rk3399 big
3.6           rk3399 lit
3.7           rk322x

The IP version is from VERSION_INFO register

major version: used for IP structure, Vop full framework is 3,
vop little framework is 2.
minor version: on same structure, newer design vop will bigger then
old one.

Change-Id: I032cb3d74cd01440274d3efeefa747e6028c1689
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
This commit is contained in:
Mark Yao
2016-07-22 18:44:26 +08:00
committed by Gerrit Code Review
parent 06ad8234d0
commit 17f3b4e9bb
4 changed files with 825 additions and 415 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@@ -37,34 +37,55 @@
#include "rockchip_drm_fb.h"
#include "rockchip_drm_vop.h"
#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
vop_mask_write(x, off, mask, shift, v, write_mask, true)
#define VOP_REG_SUPPORT(vop, reg) \
(!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
reg.begin_minor <= VOP_MINOR(vop->data->version) && \
reg.end_minor >= VOP_MINOR(vop->data->version) && \
reg.mask))
#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
vop_mask_write(x, off, mask, shift, v, write_mask, false)
#define VOP_WIN_SUPPORT(vop, win, name) \
VOP_REG_SUPPORT(vop, win->phy->name)
#define REG_SET(x, off, reg, v, mode) \
__REG_SET_##mode(x, off + reg.offset, \
reg.mask, reg.shift, v, reg.write_mask)
#define REG_SET_MASK(x, off, reg, mask, v, mode) \
__REG_SET_##mode(x, off + reg.offset, \
mask, reg.shift, v, reg.write_mask)
#define VOP_CTRL_SUPPORT(vop, win, name) \
VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
#define VOP_INTR_SUPPORT(vop, win, name) \
VOP_REG_SUPPORT(vop, vop->data->intr->name)
#define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
#define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
do { \
if (VOP_REG_SUPPORT(vop, reg)) \
__REG_SET(vop, off + reg.offset, mask, reg.shift, \
v, reg.write_mask, relaxed); \
else \
dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
} while(0)
#define REG_SET(x, name, off, reg, v, relaxed) \
_REG_SET(x, name, off, reg, reg.mask, v, relaxed)
#define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
_REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
#define VOP_WIN_SET(x, win, name, v) \
REG_SET(x, win->offset, VOP_WIN_NAME(win, name), v, RELAXED)
REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
#define VOP_SCL_SET(x, win, name, v) \
REG_SET(x, win->offset, win->phy->scl->name, v, RELAXED)
REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
#define VOP_SCL_SET_EXT(x, win, name, v) \
REG_SET(x, win->offset, win->phy->scl->ext->name, v, RELAXED)
REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
#define VOP_CTRL_SET(x, name, v) \
REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
#define VOP_INTR_GET(vop, name) \
vop_read_reg(vop, 0, &vop->data->ctrl->name)
#define VOP_INTR_SET(vop, name, mask, v) \
REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
mask, v, false)
#define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
int i, reg = 0, mask = 0; \
@@ -79,6 +100,9 @@
#define VOP_INTR_GET_TYPE(vop, name, type) \
vop_get_intr_type(vop, &vop->data->intr->name, type)
#define VOP_CTRL_GET(x, name) \
vop_read_reg(x, 0, vop->data->ctrl->name)
#define VOP_WIN_GET(x, win, name) \
vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
@@ -88,9 +112,6 @@
#define VOP_WIN_GET_YRGBADDR(vop, win) \
vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
#define VOP_WIN_SUPPORT(win, name) \
(win->phy->name.mask ? true : false)
#define to_vop(x) container_of(x, struct vop, crtc)
#define to_vop_win(x) container_of(x, struct vop_win, base)
#define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
@@ -1376,10 +1397,10 @@ static int vop_plane_init(struct vop *vop, struct vop_win *win,
drm_object_attach_property(&win->base.base,
vop->plane_zpos_prop, win->win_id);
if (VOP_WIN_SUPPORT(win, xmirror))
if (VOP_WIN_SUPPORT(vop, win, xmirror))
rotations |= BIT(DRM_REFLECT_X);
if (VOP_WIN_SUPPORT(win, ymirror))
if (VOP_WIN_SUPPORT(vop, win, ymirror))
rotations |= BIT(DRM_REFLECT_Y);
if (rotations) {
@@ -1509,8 +1530,6 @@ static void vop_destroy_crtc(struct vop *vop)
static int vop_initial(struct vop *vop)
{
const struct vop_data *vop_data = vop->data;
const struct vop_reg_data *init_table = vop_data->init_table;
struct reset_control *ahb_rst;
int i, ret;
@@ -1564,13 +1583,12 @@ static int vop_initial(struct vop *vop)
memcpy(vop->regsbak, vop->regs, vop->len);
for (i = 0; i < vop_data->table_size; i++)
vop_writel(vop, init_table[i].offset, init_table[i].value);
VOP_CTRL_SET(vop, global_regdone_en, 1);
for (i = 0; i < vop->num_wins; i++) {
struct vop_win *win = &vop->win[i];
VOP_WIN_SET(vop, win, enable, 0);
VOP_WIN_SET(vop, win, gate, 1);
}
vop_cfg_done(vop);

82
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -15,6 +15,14 @@
#ifndef _ROCKCHIP_DRM_VOP_H
#define _ROCKCHIP_DRM_VOP_H
/*
* major: IP major vertion, used for IP structure
* minor: big feature change under same structure
*/
#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
#define VOP_MAJOR(version) ((version) >> 8)
#define VOP_MINOR(version) ((version) & 0xff)
enum vop_data_format {
VOP_FMT_ARGB8888 = 0,
VOP_FMT_RGB888,
@@ -30,37 +38,58 @@ struct vop_reg_data {
};
struct vop_reg {
uint32_t offset;
uint32_t shift;
uint32_t mask;
bool write_mask;
uint32_t offset:12;
uint32_t shift:5;
uint32_t begin_minor:4;
uint32_t end_minor:4;
uint32_t major:3;
uint32_t write_mask:1;
};
struct vop_ctrl {
struct vop_reg standby;
struct vop_reg data_blank;
struct vop_reg gate_en;
struct vop_reg mmu_en;
struct vop_reg htotal_pw;
struct vop_reg hact_st_end;
struct vop_reg vtotal_pw;
struct vop_reg vact_st_end;
struct vop_reg vact_st_end_f1;
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
struct vop_reg vpost_st_end_f1;
struct vop_reg dsp_interlace;
struct vop_reg global_regdone_en;
struct vop_reg auto_gate_en;
struct vop_reg post_lb_mode;
struct vop_reg dsp_layer_sel;
struct vop_reg overlay_mode;
struct vop_reg core_dclk_div;
struct vop_reg p2i_en;
struct vop_reg rgb_en;
struct vop_reg edp_en;
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
struct vop_reg out_mode;
struct vop_reg dsp_layer_sel;
struct vop_reg dither_down;
struct vop_reg dither_up;
struct vop_reg pin_pol;
struct vop_reg rgb_pin_pol;
struct vop_reg hdmi_pin_pol;
struct vop_reg edp_pin_pol;
struct vop_reg mipi_pin_pol;
struct vop_reg htotal_pw;
struct vop_reg hact_st_end;
struct vop_reg vtotal_pw;
struct vop_reg vact_st_end;
struct vop_reg hpost_st_end;
struct vop_reg vpost_st_end;
struct vop_reg dither_up;
struct vop_reg dither_down;
struct vop_reg dsp_data_swap;
struct vop_reg dsp_ccir656_avg;
struct vop_reg dsp_black;
struct vop_reg dsp_blank;
struct vop_reg dsp_outzero;
struct vop_reg dsp_lut_en;
struct vop_reg out_mode;
struct vop_reg xmirror;
struct vop_reg ymirror;
struct vop_reg dsp_background;
struct vop_reg cfg_done;
};
@@ -68,6 +97,7 @@ struct vop_ctrl {
struct vop_intr {
const int *intrs;
uint32_t nintrs;
struct vop_reg line_flag_num;
struct vop_reg enable;
struct vop_reg clear;
struct vop_reg status;
@@ -111,6 +141,7 @@ struct vop_win_phy {
const uint32_t *data_formats;
uint32_t nformats;
struct vop_reg gate;
struct vop_reg enable;
struct vop_reg format;
struct vop_reg xmirror;
@@ -128,6 +159,8 @@ struct vop_win_phy {
struct vop_reg src_alpha_ctl;
struct vop_reg alpha_mode;
struct vop_reg alpha_en;
struct vop_reg key_color;
struct vop_reg key_en;
};
struct vop_win_data {
@@ -147,6 +180,7 @@ struct vop_data {
const struct vop_intr *intr;
const struct vop_win_data *win;
unsigned int win_size;
uint32_t version;
u64 feature;
};
@@ -155,9 +189,23 @@ struct vop_data {
#define FS_INTR (1 << 1)
#define LINE_FLAG_INTR (1 << 2)
#define BUS_ERROR_INTR (1 << 3)
#define FS_NEW_INTR (1 << 4)
#define ADDR_SAME_INTR (1 << 5)
#define LINE_FLAG1_INTR (1 << 6)
#define WIN0_EMPTY_INTR (1 << 7)
#define WIN1_EMPTY_INTR (1 << 8)
#define WIN2_EMPTY_INTR (1 << 9)
#define WIN3_EMPTY_INTR (1 << 10)
#define HWC_EMPTY_INTR (1 << 11)
#define POST_BUF_EMPTY_INTR (1 << 12)
#define PWM_GEN_INTR (1 << 13)
#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
LINE_FLAG_INTR | BUS_ERROR_INTR)
LINE_FLAG_INTR | BUS_ERROR_INTR | \
FS_NEW_INTR | LINE_FLAG1_INTR | \
WIN0_EMPTY_INTR | WIN1_EMPTY_INTR | \
WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | \
HWC_EMPTY_INTR | POST_BUF_EMPTY_INTR)
#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
#define FS_INTR_EN(x) ((x) << 5)

361
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -20,17 +20,26 @@
#include "rockchip_drm_vop.h"
#include "rockchip_vop_reg.h"
#define VOP_REG(off, _mask, s) \
#define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
_begin_minor, _end_minor) \
{.offset = off, \
.mask = _mask, \
.shift = s, \
.write_mask = false,}
.write_mask = _write_mask, \
.major = _major, \
.begin_minor = _begin_minor, \
.end_minor = _end_minor,}
#define VOP_REG(off, _mask, s) \
VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
#define VOP_REG_MASK(off, _mask, s) \
{.offset = off, \
.mask = _mask, \
.shift = s, \
.write_mask = true,}
VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
#define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
VOP_REG_VER_MASK(off, _mask, s, false, \
_major, _begin_minor, _end_minor)
static const uint32_t formats_win_full[] = {
DRM_FORMAT_XRGB8888,
@@ -96,6 +105,8 @@ static const struct vop_win_phy rk3288_win01_data = {
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
.xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
.ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
@@ -103,13 +114,14 @@ static const struct vop_win_phy rk3288_win01_data = {
.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
};
static const struct vop_win_phy rk3288_win23_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
.gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
.enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
@@ -153,40 +165,47 @@ static const struct vop_win_phy *rk3288_area_data[] = {
static const struct vop_ctrl rk3288_ctrl_data = {
.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
.dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
};
.vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
.dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
.auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
.dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
.post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
.global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
.overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
.core_dclk_div = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 4, 3, 4, -1),
.p2i_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 5, 3, 4, -1),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
.pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
.rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
.hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
.edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
.mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
static const struct vop_reg_data rk3288_init_reg_table[] = {
{RK3288_SYS_CTRL, 0x00c00000},
{RK3288_DSP_CTRL0, 0x00000000},
{RK3288_WIN0_CTRL0, 0x00000080},
{RK3288_WIN1_CTRL0, 0x00000080},
/*
* Bit[0] is win2/3 gate en bit, there is no power consume with this
* bit enable. the bit's function similar with area plane enable bit,
* So default enable this bit, then We can control win2/3 area plane
* with its enable bit.
*/
{RK3288_WIN2_CTRL0, 0x00000001},
{RK3288_WIN3_CTRL0, 0x00000001},
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
.dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
.dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
.dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
.xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
.ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
};
/*
@@ -226,195 +245,170 @@ static const struct vop_intr rk3288_vop_intr = {
};
static const struct vop_data rk3288_vop = {
.version = VOP_VERSION(3, 1),
.feature = VOP_FEATURE_OUTPUT_10BIT,
.init_table = rk3288_init_reg_table,
.table_size = ARRAY_SIZE(rk3288_init_reg_table),
.intr = &rk3288_vop_intr,
.ctrl = &rk3288_ctrl_data,
.win = rk3288_vop_win_data,
.win_size = ARRAY_SIZE(rk3288_vop_win_data),
};
static const struct vop_ctrl rk3399_ctrl_data = {
.standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
.gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
.rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
.mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
.dsp_layer_sel = VOP_REG(RK3399_DSP_CTRL1, 0xff, 8),
.dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
.dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
.data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
.rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
.hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
.edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
.mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
.htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
.cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
};
static const int rk3399_vop_intrs[] = {
static const int rk3368_vop_intrs[] = {
FS_INTR,
0, 0,
FS_NEW_INTR,
ADDR_SAME_INTR,
LINE_FLAG_INTR,
0,
LINE_FLAG1_INTR,
BUS_ERROR_INTR,
0, 0, 0, 0, 0, 0, 0,
WIN0_EMPTY_INTR,
WIN1_EMPTY_INTR,
WIN2_EMPTY_INTR,
WIN3_EMPTY_INTR,
HWC_EMPTY_INTR,
POST_BUF_EMPTY_INTR,
PWM_GEN_INTR,
DSP_HOLD_VALID_INTR,
};
static const struct vop_intr rk3399_vop_intr = {
.intrs = rk3399_vop_intrs,
.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
.status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
.enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
.clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
static const struct vop_intr rk3368_vop_intr = {
.intrs = rk3368_vop_intrs,
.nintrs = ARRAY_SIZE(rk3368_vop_intrs),
.status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
.enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
.clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
};
static const struct vop_reg_data rk3399_init_reg_table[] = {
{RK3399_SYS_CTRL, 0x2000f800},
{RK3399_DSP_CTRL0, 0x00000000},
{RK3399_WIN0_CTRL0, 0x00000080},
{RK3399_WIN1_CTRL0, 0x00000080},
/*
* Bit[0] is win2/3 gate en bit, there is no power consume with this
* bit enable. the bit's function similar with area plane enable bit,
* So default enable this bit, then We can control win2/3 area plane
* with its enable bit.
*/
{RK3399_WIN2_CTRL0, 0x00000001},
{RK3399_WIN3_CTRL0, 0x00000001},
};
static const struct vop_win_phy rk3399_win01_data = {
.scl = &rk3288_win_full_scl,
.data_formats = formats_win_full,
.nformats = ARRAY_SIZE(formats_win_full),
.enable = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3399_WIN0_CTRL0, 0x7, 1),
.xmirror = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 21),
.ymirror = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 22),
.rb_swap = VOP_REG(RK3399_WIN0_CTRL0, 0x1, 12),
.act_info = VOP_REG(RK3399_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3399_WIN0_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3399_WIN0_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3399_WIN0_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3399_WIN0_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3399_WIN0_VIR, 0x3fff, 0),
.uv_vir = VOP_REG(RK3399_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3399_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3399_WIN0_DST_ALPHA_CTRL, 0xff, 0),
};
static const struct vop_win_phy rk3399_win23_data = {
static const struct vop_win_phy rk3368_win23_data = {
.data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite),
.enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 4),
.format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 5),
.ymirror = VOP_REG(RK3399_WIN2_CTRL1, 0x1, 15),
.rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 20),
.dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO0, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3399_WIN2_DSP_ST0, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3399_WIN2_MST0, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3399_WIN2_VIR0_1, 0x1fff, 0),
.src_alpha_ctl = VOP_REG(RK3399_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3399_WIN2_DST_ALPHA_CTRL, 0xff, 0),
.gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
.ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
.src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
};
static const struct vop_win_phy rk3399_area1_data = {
.enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 8),
.format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 9),
.rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 23),
.dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO1, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3399_WIN2_DSP_ST1, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3399_WIN2_MST1, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3399_WIN2_VIR0_1, 0x1fff, 16),
static const struct vop_win_phy rk3368_area1_data = {
.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
};
static const struct vop_win_phy rk3399_area2_data = {
.enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 12),
.format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 13),
.rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 26),
.dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO2, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3399_WIN2_DSP_ST2, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3399_WIN2_MST2, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3399_WIN2_VIR2_3, 0x1fff, 0),
static const struct vop_win_phy rk3368_area2_data = {
.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
};
static const struct vop_win_phy rk3399_area3_data = {
.enable = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 16),
.format = VOP_REG(RK3399_WIN2_CTRL0, 0x3, 17),
.rb_swap = VOP_REG(RK3399_WIN2_CTRL0, 0x1, 29),
.dsp_info = VOP_REG(RK3399_WIN2_DSP_INFO3, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3399_WIN2_DSP_ST3, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3399_WIN2_MST3, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3399_WIN2_VIR2_3, 0x1fff, 16),
static const struct vop_win_phy rk3368_area3_data = {
.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
};
static const struct vop_win_phy *rk3399_area_data[] = {
&rk3399_area1_data,
&rk3399_area2_data,
&rk3399_area3_data
static const struct vop_win_phy *rk3368_area_data[] = {
&rk3368_area1_data,
&rk3368_area2_data,
&rk3368_area3_data
};
static const struct vop_win_data rk3399_vop_win_data[] = {
{ .base = 0x00, .phy = &rk3399_win01_data,
static const struct vop_win_data rk3368_vop_win_data[] = {
{ .base = 0x00, .phy = &rk3288_win01_data,
.type = DRM_PLANE_TYPE_PRIMARY },
{ .base = 0x40, .phy = &rk3399_win01_data,
{ .base = 0x40, .phy = &rk3288_win01_data,
.type = DRM_PLANE_TYPE_OVERLAY },
{ .base = 0x00, .phy = &rk3399_win23_data,
{ .base = 0x00, .phy = &rk3368_win23_data,
.type = DRM_PLANE_TYPE_OVERLAY,
.area = rk3399_area_data,
.area_size = ARRAY_SIZE(rk3399_area_data), },
{ .base = 0x50, .phy = &rk3399_win23_data,
.area = rk3368_area_data,
.area_size = ARRAY_SIZE(rk3368_area_data), },
{ .base = 0x50, .phy = &rk3368_win23_data,
.type = DRM_PLANE_TYPE_CURSOR,
.area = rk3399_area_data,
.area_size = ARRAY_SIZE(rk3399_area_data), },
.area = rk3368_area_data,
.area_size = ARRAY_SIZE(rk3368_area_data), },
};
static const struct vop_data rk3368_vop = {
.version = VOP_VERSION(3, 2),
.feature = VOP_FEATURE_OUTPUT_10BIT,
.intr = &rk3368_vop_intr,
.ctrl = &rk3288_ctrl_data,
.win = rk3368_vop_win_data,
.win_size = ARRAY_SIZE(rk3368_vop_win_data),
};
static const struct vop_intr rk3366_vop_intr = {
.intrs = rk3368_vop_intrs,
.nintrs = ARRAY_SIZE(rk3368_vop_intrs),
.status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
.enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
.clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
};
static const struct vop_data rk3366_vop = {
.version = VOP_VERSION(3, 4),
.feature = VOP_FEATURE_OUTPUT_10BIT,
.intr = &rk3366_vop_intr,
.ctrl = &rk3288_ctrl_data,
.win = rk3368_vop_win_data,
.win_size = ARRAY_SIZE(rk3368_vop_win_data),
};
static const struct vop_data rk3399_vop_big = {
.version = VOP_VERSION(3, 5),
.feature = VOP_FEATURE_OUTPUT_10BIT,
.init_table = rk3399_init_reg_table,
.table_size = ARRAY_SIZE(rk3399_init_reg_table),
.intr = &rk3399_vop_intr,
.ctrl = &rk3399_ctrl_data,
/*
* rk3399 vop big windows register layout is same as rk3288.
*/
.win = rk3399_vop_win_data,
.win_size = ARRAY_SIZE(rk3399_vop_win_data),
.intr = &rk3366_vop_intr,
.ctrl = &rk3288_ctrl_data,
.win = rk3368_vop_win_data,
.win_size = ARRAY_SIZE(rk3368_vop_win_data),
};
static const struct vop_win_data rk3399_vop_lit_win_data[] = {
{ .base = 0x00, .phy = &rk3399_win01_data,
{ .base = 0x00, .phy = &rk3288_win01_data,
.type = DRM_PLANE_TYPE_PRIMARY },
{ .phy = NULL },
{ .base = 0x00, .phy = &rk3288_win23_data,
.type = DRM_PLANE_TYPE_CURSOR},
{ .base = 0x00, .phy = &rk3368_win23_data,
.type = DRM_PLANE_TYPE_CURSOR,
.area = rk3368_area_data,
.area_size = ARRAY_SIZE(rk3368_area_data), },
{ .phy = NULL },
};
static const struct vop_data rk3399_vop_lit = {
.init_table = rk3399_init_reg_table,
.table_size = ARRAY_SIZE(rk3399_init_reg_table),
.intr = &rk3399_vop_intr,
.ctrl = &rk3399_ctrl_data,
/*
* rk3399 vop lit windows register layout is same as rk3288,
* but cut off the win1 and win3 windows.
*/
.version = VOP_VERSION(3, 6),
.intr = &rk3366_vop_intr,
.ctrl = &rk3288_ctrl_data,
.win = rk3399_vop_lit_win_data,
.win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
};
static const struct vop_data rk322x_vop = {
.version = VOP_VERSION(3, 7),
.feature = VOP_FEATURE_OUTPUT_10BIT,
.intr = &rk3366_vop_intr,
.ctrl = &rk3288_ctrl_data,
.win = rk3368_vop_win_data,
.win_size = ARRAY_SIZE(rk3368_vop_win_data),
};
static const struct vop_scl_regs rk3066_win_scl = {
.scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
.scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
@@ -489,13 +483,8 @@ static const struct vop_ctrl rk3036_ctrl_data = {
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
};
static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
{RK3036_DSP_CTRL1, 0x00000000},
};
static const struct vop_data rk3036_vop = {
.init_table = rk3036_vop_init_reg_table,
.table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
.version = VOP_VERSION(2, 2),
.ctrl = &rk3036_ctrl_data,
.intr = &rk3036_intr,
.win = rk3036_vop_win_data,
@@ -503,14 +492,20 @@ static const struct vop_data rk3036_vop = {
};
static const struct of_device_id vop_driver_dt_match[] = {
{ .compatible = "rockchip,rk3288-vop",
.data = &rk3288_vop },
{ .compatible = "rockchip,rk3036-vop",
.data = &rk3036_vop },
{ .compatible = "rockchip,rk3288-vop",
.data = &rk3288_vop },
{ .compatible = "rockchip,rk3368-vop",
.data = &rk3368_vop },
{ .compatible = "rockchip,rk3366-vop",
.data = &rk3366_vop },
{ .compatible = "rockchip,rk3399-vop-big",
.data = &rk3399_vop_big },
{ .compatible = "rockchip,rk3399-vop-lit",
.data = &rk3399_vop_lit },
{ .compatible = "rockchip,rk322x-vop",
.data = &rk322x_vop },
{},
};
MODULE_DEVICE_TABLE(of, vop_driver_dt_match);

729
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -122,197 +122,546 @@
#define RK3288_DSP_VACT_ST_END_F1 0x019c
/* register definition end */
/* rk3368 register definition */
#define RK3368_REG_CFG_DONE 0x0000
#define RK3368_VERSION_INFO 0x0004
#define RK3368_SYS_CTRL 0x0008
#define RK3368_SYS_CTRL1 0x000c
#define RK3368_DSP_CTRL0 0x0010
#define RK3368_DSP_CTRL1 0x0014
#define RK3368_DSP_BG 0x0018
#define RK3368_MCU_CTRL 0x001c
#define RK3368_LINE_FLAG 0x0020
#define RK3368_INTR_EN 0x0024
#define RK3368_INTR_CLEAR 0x0028
#define RK3368_INTR_STATUS 0x002c
#define RK3368_WIN0_CTRL0 0x0030
#define RK3368_WIN0_CTRL1 0x0034
#define RK3368_WIN0_COLOR_KEY 0x0038
#define RK3368_WIN0_VIR 0x003c
#define RK3368_WIN0_YRGB_MST 0x0040
#define RK3368_WIN0_CBR_MST 0x0044
#define RK3368_WIN0_ACT_INFO 0x0048
#define RK3368_WIN0_DSP_INFO 0x004c
#define RK3368_WIN0_DSP_ST 0x0050
#define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054
#define RK3368_WIN0_SCL_FACTOR_CBR 0x0058
#define RK3368_WIN0_SCL_OFFSET 0x005c
#define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060
#define RK3368_WIN0_DST_ALPHA_CTRL 0x0064
#define RK3368_WIN0_FADING_CTRL 0x0068
#define RK3368_WIN0_CTRL2 0x006c
#define RK3368_WIN1_CTRL0 0x0070
#define RK3368_WIN1_CTRL1 0x0074
#define RK3368_WIN1_COLOR_KEY 0x0078
#define RK3368_WIN1_VIR 0x007c
#define RK3368_WIN1_YRGB_MST 0x0080
#define RK3368_WIN1_CBR_MST 0x0084
#define RK3368_WIN1_ACT_INFO 0x0088
#define RK3368_WIN1_DSP_INFO 0x008c
#define RK3368_WIN1_DSP_ST 0x0090
#define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094
#define RK3368_WIN1_SCL_FACTOR_CBR 0x0098
#define RK3368_WIN1_SCL_OFFSET 0x009c
#define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0
#define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4
#define RK3368_WIN1_FADING_CTRL 0x00a8
#define RK3368_WIN1_CTRL2 0x00ac
#define RK3368_WIN2_CTRL0 0x00b0
#define RK3368_WIN2_CTRL1 0x00b4
#define RK3368_WIN2_VIR0_1 0x00b8
#define RK3368_WIN2_VIR2_3 0x00bc
#define RK3368_WIN2_MST0 0x00c0
#define RK3368_WIN2_DSP_INFO0 0x00c4
#define RK3368_WIN2_DSP_ST0 0x00c8
#define RK3368_WIN2_COLOR_KEY 0x00cc
#define RK3368_WIN2_MST1 0x00d0
#define RK3368_WIN2_DSP_INFO1 0x00d4
#define RK3368_WIN2_DSP_ST1 0x00d8
#define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc
#define RK3368_WIN2_MST2 0x00e0
#define RK3368_WIN2_DSP_INFO2 0x00e4
#define RK3368_WIN2_DSP_ST2 0x00e8
#define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec
#define RK3368_WIN2_MST3 0x00f0
#define RK3368_WIN2_DSP_INFO3 0x00f4
#define RK3368_WIN2_DSP_ST3 0x00f8
#define RK3368_WIN2_FADING_CTRL 0x00fc
#define RK3368_WIN3_CTRL0 0x0100
#define RK3368_WIN3_CTRL1 0x0104
#define RK3368_WIN3_VIR0_1 0x0108
#define RK3368_WIN3_VIR2_3 0x010c
#define RK3368_WIN3_MST0 0x0110
#define RK3368_WIN3_DSP_INFO0 0x0114
#define RK3368_WIN3_DSP_ST0 0x0118
#define RK3368_WIN3_COLOR_KEY 0x011c
#define RK3368_WIN3_MST1 0x0120
#define RK3368_WIN3_DSP_INFO1 0x0124
#define RK3368_WIN3_DSP_ST1 0x0128
#define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c
#define RK3368_WIN3_MST2 0x0130
#define RK3368_WIN3_DSP_INFO2 0x0134
#define RK3368_WIN3_DSP_ST2 0x0138
#define RK3368_WIN3_DST_ALPHA_CTRL 0x013c
#define RK3368_WIN3_MST3 0x0140
#define RK3368_WIN3_DSP_INFO3 0x0144
#define RK3368_WIN3_DSP_ST3 0x0148
#define RK3368_WIN3_FADING_CTRL 0x014c
#define RK3368_HWC_CTRL0 0x0150
#define RK3368_HWC_CTRL1 0x0154
#define RK3368_HWC_MST 0x0158
#define RK3368_HWC_DSP_ST 0x015c
#define RK3368_HWC_SRC_ALPHA_CTRL 0x0160
#define RK3368_HWC_DST_ALPHA_CTRL 0x0164
#define RK3368_HWC_FADING_CTRL 0x0168
#define RK3368_HWC_RESERVED1 0x016c
#define RK3368_POST_DSP_HACT_INFO 0x0170
#define RK3368_POST_DSP_VACT_INFO 0x0174
#define RK3368_POST_SCL_FACTOR_YRGB 0x0178
#define RK3368_POST_RESERVED 0x017c
#define RK3368_POST_SCL_CTRL 0x0180
#define RK3368_POST_DSP_VACT_INFO_F1 0x0184
#define RK3368_DSP_HTOTAL_HS_END 0x0188
#define RK3368_DSP_HACT_ST_END 0x018c
#define RK3368_DSP_VTOTAL_VS_END 0x0190
#define RK3368_DSP_VACT_ST_END 0x0194
#define RK3368_DSP_VS_ST_END_F1 0x0198
#define RK3368_DSP_VACT_ST_END_F1 0x019c
#define RK3368_PWM_CTRL 0x01a0
#define RK3368_PWM_PERIOD_HPR 0x01a4
#define RK3368_PWM_DUTY_LPR 0x01a8
#define RK3368_PWM_CNT 0x01ac
#define RK3368_BCSH_COLOR_BAR 0x01b0
#define RK3368_BCSH_BCS 0x01b4
#define RK3368_BCSH_H 0x01b8
#define RK3368_BCSH_CTRL 0x01bc
#define RK3368_CABC_CTRL0 0x01c0
#define RK3368_CABC_CTRL1 0x01c4
#define RK3368_CABC_CTRL2 0x01c8
#define RK3368_CABC_CTRL3 0x01cc
#define RK3368_CABC_GAUSS_LINE0_0 0x01d0
#define RK3368_CABC_GAUSS_LINE0_1 0x01d4
#define RK3368_CABC_GAUSS_LINE1_0 0x01d8
#define RK3368_CABC_GAUSS_LINE1_1 0x01dc
#define RK3368_CABC_GAUSS_LINE2_0 0x01e0
#define RK3368_CABC_GAUSS_LINE2_1 0x01e4
#define RK3368_FRC_LOWER01_0 0x01e8
#define RK3368_FRC_LOWER01_1 0x01ec
#define RK3368_FRC_LOWER10_0 0x01f0
#define RK3368_FRC_LOWER10_1 0x01f4
#define RK3368_FRC_LOWER11_0 0x01f8
#define RK3368_FRC_LOWER11_1 0x01fc
#define RK3368_IFBDC_CTRL 0x0200
#define RK3368_IFBDC_TILES_NUM 0x0204
#define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208
#define RK3368_IFBDC_BASE_ADDR 0x020c
#define RK3368_IFBDC_MB_SIZE 0x0210
#define RK3368_IFBDC_CMP_INDEX_INIT 0x0214
#define RK3368_IFBDC_VIR 0x0220
#define RK3368_IFBDC_DEBUG0 0x0230
#define RK3368_IFBDC_DEBUG1 0x0234
#define RK3368_LATENCY_CTRL0 0x0250
#define RK3368_RD_MAX_LATENCY_NUM0 0x0254
#define RK3368_RD_LATENCY_THR_NUM0 0x0258
#define RK3368_RD_LATENCY_SAMP_NUM0 0x025c
#define RK3368_WIN0_DSP_BG 0x0260
#define RK3368_WIN1_DSP_BG 0x0264
#define RK3368_WIN2_DSP_BG 0x0268
#define RK3368_WIN3_DSP_BG 0x026c
#define RK3368_SCAN_LINE_NUM 0x0270
#define RK3368_CABC_DEBUG0 0x0274
#define RK3368_CABC_DEBUG1 0x0278
#define RK3368_CABC_DEBUG2 0x027c
#define RK3368_DBG_REG_000 0x0280
#define RK3368_DBG_REG_001 0x0284
#define RK3368_DBG_REG_002 0x0288
#define RK3368_DBG_REG_003 0x028c
#define RK3368_DBG_REG_004 0x0290
#define RK3368_DBG_REG_005 0x0294
#define RK3368_DBG_REG_006 0x0298
#define RK3368_DBG_REG_007 0x029c
#define RK3368_DBG_REG_008 0x02a0
#define RK3368_DBG_REG_016 0x02c0
#define RK3368_DBG_REG_017 0x02c4
#define RK3368_DBG_REG_018 0x02c8
#define RK3368_DBG_REG_019 0x02cc
#define RK3368_DBG_REG_020 0x02d0
#define RK3368_DBG_REG_021 0x02d4
#define RK3368_DBG_REG_022 0x02d8
#define RK3368_DBG_REG_023 0x02dc
#define RK3368_DBG_REG_028 0x02f0
#define RK3368_MMU_DTE_ADDR 0x0300
#define RK3368_MMU_STATUS 0x0304
#define RK3368_MMU_COMMAND 0x0308
#define RK3368_MMU_PAGE_FAULT_ADDR 0x030c
#define RK3368_MMU_ZAP_ONE_LINE 0x0310
#define RK3368_MMU_INT_RAWSTAT 0x0314
#define RK3368_MMU_INT_CLEAR 0x0318
#define RK3368_MMU_INT_MASK 0x031c
#define RK3368_MMU_INT_STATUS 0x0320
#define RK3368_MMU_AUTO_GATING 0x0324
#define RK3368_WIN2_LUT_ADDR 0x0400
#define RK3368_WIN3_LUT_ADDR 0x0800
#define RK3368_HWC_LUT_ADDR 0x0c00
#define RK3368_GAMMA_LUT_ADDR 0x1000
#define RK3368_CABC_GAMMA_LUT_ADDR 0x1800
#define RK3368_MCU_BYPASS_WPORT 0x2200
#define RK3368_MCU_BYPASS_RPORT 0x2300
/* rk3368 register definition end */
#define RK3366_REG_CFG_DONE 0x0000
#define RK3366_VERSION_INFO 0x0004
#define RK3366_SYS_CTRL 0x0008
#define RK3366_SYS_CTRL1 0x000c
#define RK3366_DSP_CTRL0 0x0010
#define RK3366_DSP_CTRL1 0x0014
#define RK3366_DSP_BG 0x0018
#define RK3366_MCU_CTRL 0x001c
#define RK3366_WB_CTRL0 0x0020
#define RK3366_WB_CTRL1 0x0024
#define RK3366_WB_YRGB_MST 0x0028
#define RK3366_WB_CBR_MST 0x002c
#define RK3366_WIN0_CTRL0 0x0030
#define RK3366_WIN0_CTRL1 0x0034
#define RK3366_WIN0_COLOR_KEY 0x0038
#define RK3366_WIN0_VIR 0x003c
#define RK3366_WIN0_YRGB_MST 0x0040
#define RK3366_WIN0_CBR_MST 0x0044
#define RK3366_WIN0_ACT_INFO 0x0048
#define RK3366_WIN0_DSP_INFO 0x004c
#define RK3366_WIN0_DSP_ST 0x0050
#define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054
#define RK3366_WIN0_SCL_FACTOR_CBR 0x0058
#define RK3366_WIN0_SCL_OFFSET 0x005c
#define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060
#define RK3366_WIN0_DST_ALPHA_CTRL 0x0064
#define RK3366_WIN0_FADING_CTRL 0x0068
#define RK3366_WIN0_CTRL2 0x006c
#define RK3366_WIN1_CTRL0 0x0070
#define RK3366_WIN1_CTRL1 0x0074
#define RK3366_WIN1_COLOR_KEY 0x0078
#define RK3366_WIN1_VIR 0x007c
#define RK3366_WIN1_YRGB_MST 0x0080
#define RK3366_WIN1_CBR_MST 0x0084
#define RK3366_WIN1_ACT_INFO 0x0088
#define RK3366_WIN1_DSP_INFO 0x008c
#define RK3366_WIN1_DSP_ST 0x0090
#define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094
#define RK3366_WIN1_SCL_FACTOR_CBR 0x0098
#define RK3366_WIN1_SCL_OFFSET 0x009c
#define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0
#define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4
#define RK3366_WIN1_FADING_CTRL 0x00a8
#define RK3366_WIN1_CTRL2 0x00ac
#define RK3366_WIN2_CTRL0 0x00b0
#define RK3366_WIN2_CTRL1 0x00b4
#define RK3366_WIN2_VIR0_1 0x00b8
#define RK3366_WIN2_VIR2_3 0x00bc
#define RK3366_WIN2_MST0 0x00c0
#define RK3366_WIN2_DSP_INFO0 0x00c4
#define RK3366_WIN2_DSP_ST0 0x00c8
#define RK3366_WIN2_COLOR_KEY 0x00cc
#define RK3366_WIN2_MST1 0x00d0
#define RK3366_WIN2_DSP_INFO1 0x00d4
#define RK3366_WIN2_DSP_ST1 0x00d8
#define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc
#define RK3366_WIN2_MST2 0x00e0
#define RK3366_WIN2_DSP_INFO2 0x00e4
#define RK3366_WIN2_DSP_ST2 0x00e8
#define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec
#define RK3366_WIN2_MST3 0x00f0
#define RK3366_WIN2_DSP_INFO3 0x00f4
#define RK3366_WIN2_DSP_ST3 0x00f8
#define RK3366_WIN2_FADING_CTRL 0x00fc
#define RK3366_WIN3_CTRL0 0x0100
#define RK3366_WIN3_CTRL1 0x0104
#define RK3366_WIN3_VIR0_1 0x0108
#define RK3366_WIN3_VIR2_3 0x010c
#define RK3366_WIN3_MST0 0x0110
#define RK3366_WIN3_DSP_INFO0 0x0114
#define RK3366_WIN3_DSP_ST0 0x0118
#define RK3366_WIN3_COLOR_KEY 0x011c
#define RK3366_WIN3_MST1 0x0120
#define RK3366_WIN3_DSP_INFO1 0x0124
#define RK3366_WIN3_DSP_ST1 0x0128
#define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c
#define RK3366_WIN3_MST2 0x0130
#define RK3366_WIN3_DSP_INFO2 0x0134
#define RK3366_WIN3_DSP_ST2 0x0138
#define RK3366_WIN3_DST_ALPHA_CTRL 0x013c
#define RK3366_WIN3_MST3 0x0140
#define RK3366_WIN3_DSP_INFO3 0x0144
#define RK3366_WIN3_DSP_ST3 0x0148
#define RK3366_WIN3_FADING_CTRL 0x014c
#define RK3366_HWC_CTRL0 0x0150
#define RK3366_HWC_CTRL1 0x0154
#define RK3366_HWC_MST 0x0158
#define RK3366_HWC_DSP_ST 0x015c
#define RK3366_HWC_SRC_ALPHA_CTRL 0x0160
#define RK3366_HWC_DST_ALPHA_CTRL 0x0164
#define RK3366_HWC_FADING_CTRL 0x0168
#define RK3366_HWC_RESERVED1 0x016c
#define RK3366_POST_DSP_HACT_INFO 0x0170
#define RK3366_POST_DSP_VACT_INFO 0x0174
#define RK3366_POST_SCL_FACTOR_YRGB 0x0178
#define RK3366_POST_RESERVED 0x017c
#define RK3366_POST_SCL_CTRL 0x0180
#define RK3366_POST_DSP_VACT_INFO_F1 0x0184
#define RK3366_DSP_HTOTAL_HS_END 0x0188
#define RK3366_DSP_HACT_ST_END 0x018c
#define RK3366_DSP_VTOTAL_VS_END 0x0190
#define RK3366_DSP_VACT_ST_END 0x0194
#define RK3366_DSP_VS_ST_END_F1 0x0198
#define RK3366_DSP_VACT_ST_END_F1 0x019c
#define RK3366_PWM_CTRL 0x01a0
#define RK3366_PWM_PERIOD_HPR 0x01a4
#define RK3366_PWM_DUTY_LPR 0x01a8
#define RK3366_PWM_CNT 0x01ac
#define RK3366_BCSH_COLOR_BAR 0x01b0
#define RK3366_BCSH_BCS 0x01b4
#define RK3366_BCSH_H 0x01b8
#define RK3366_BCSH_CTRL 0x01bc
#define RK3366_CABC_CTRL0 0x01c0
#define RK3366_CABC_CTRL1 0x01c4
#define RK3366_CABC_CTRL2 0x01c8
#define RK3366_CABC_CTRL3 0x01cc
#define RK3366_CABC_GAUSS_LINE0_0 0x01d0
#define RK3366_CABC_GAUSS_LINE0_1 0x01d4
#define RK3366_CABC_GAUSS_LINE1_0 0x01d8
#define RK3366_CABC_GAUSS_LINE1_1 0x01dc
#define RK3366_CABC_GAUSS_LINE2_0 0x01e0
#define RK3366_CABC_GAUSS_LINE2_1 0x01e4
#define RK3366_FRC_LOWER01_0 0x01e8
#define RK3366_FRC_LOWER01_1 0x01ec
#define RK3366_FRC_LOWER10_0 0x01f0
#define RK3366_FRC_LOWER10_1 0x01f4
#define RK3366_FRC_LOWER11_0 0x01f8
#define RK3366_FRC_LOWER11_1 0x01fc
#define RK3366_INTR_EN0 0x0280
#define RK3366_INTR_CLEAR0 0x0284
#define RK3366_INTR_STATUS0 0x0288
#define RK3366_INTR_RAW_STATUS0 0x028c
#define RK3366_INTR_EN1 0x0290
#define RK3366_INTR_CLEAR1 0x0294
#define RK3366_INTR_STATUS1 0x0298
#define RK3366_INTR_RAW_STATUS1 0x029c
#define RK3366_LINE_FLAG 0x02a0
#define RK3366_VOP_STATUS 0x02a4
#define RK3366_BLANKING_VALUE 0x02a8
#define RK3366_WIN0_DSP_BG 0x02b0
#define RK3366_WIN1_DSP_BG 0x02b4
#define RK3366_WIN2_DSP_BG 0x02b8
#define RK3366_WIN3_DSP_BG 0x02bc
#define RK3366_WIN2_LUT_ADDR 0x0400
#define RK3366_WIN3_LUT_ADDR 0x0800
#define RK3366_HWC_LUT_ADDR 0x0c00
#define RK3366_GAMMA0_LUT_ADDR 0x1000
#define RK3366_GAMMA1_LUT_ADDR 0x1400
#define RK3366_CABC_GAMMA_LUT_ADDR 0x1800
#define RK3366_MCU_BYPASS_WPORT 0x2200
#define RK3366_MCU_BYPASS_RPORT 0x2300
#define RK3366_MMU_DTE_ADDR 0x2400
#define RK3366_MMU_STATUS 0x2404
#define RK3366_MMU_COMMAND 0x2408
#define RK3366_MMU_PAGE_FAULT_ADDR 0x240c
#define RK3366_MMU_ZAP_ONE_LINE 0x2410
#define RK3366_MMU_INT_RAWSTAT 0x2414
#define RK3366_MMU_INT_CLEAR 0x2418
#define RK3366_MMU_INT_MASK 0x241c
#define RK3366_MMU_INT_STATUS 0x2420
#define RK3366_MMU_AUTO_GATING 0x2424
/* rk3399 register definition */
#define RK3399_REG_CFG_DONE 0x00000
#define RK3399_VERSION_INFO 0x00004
#define RK3399_SYS_CTRL 0x00008
#define RK3399_SYS_CTRL1 0x0000c
#define RK3399_DSP_CTRL0 0x00010
#define RK3399_DSP_CTRL1 0x00014
#define RK3399_DSP_BG 0x00018
#define RK3399_MCU_CTRL 0x0001c
#define RK3399_WB_CTRL0 0x00020
#define RK3399_WB_CTRL1 0x00024
#define RK3399_WB_YRGB_MST 0x00028
#define RK3399_WB_CBR_MST 0x0002c
#define RK3399_WIN0_CTRL0 0x00030
#define RK3399_WIN0_CTRL1 0x00034
#define RK3399_WIN0_COLOR_KEY 0x00038
#define RK3399_WIN0_VIR 0x0003c
#define RK3399_WIN0_YRGB_MST 0x00040
#define RK3399_WIN0_CBR_MST 0x00044
#define RK3399_WIN0_ACT_INFO 0x00048
#define RK3399_WIN0_DSP_INFO 0x0004c
#define RK3399_WIN0_DSP_ST 0x00050
#define RK3399_WIN0_SCL_FACTOR_YRGB 0x00054
#define RK3399_WIN0_SCL_FACTOR_CBR 0x00058
#define RK3399_WIN0_SCL_OFFSET 0x0005c
#define RK3399_WIN0_SRC_ALPHA_CTRL 0x00060
#define RK3399_WIN0_DST_ALPHA_CTRL 0x00064
#define RK3399_WIN0_FADING_CTRL 0x00068
#define RK3399_WIN0_CTRL2 0x0006c
#define RK3399_WIN1_CTRL0 0x00070
#define RK3399_WIN1_CTRL1 0x00074
#define RK3399_WIN1_COLOR_KEY 0x00078
#define RK3399_WIN1_VIR 0x0007c
#define RK3399_WIN1_YRGB_MST 0x00080
#define RK3399_WIN1_CBR_MST 0x00084
#define RK3399_WIN1_ACT_INFO 0x00088
#define RK3399_WIN1_DSP_INFO 0x0008c
#define RK3399_WIN1_DSP_ST 0x00090
#define RK3399_WIN1_SCL_FACTOR_YRGB 0x00094
#define RK3399_WIN1_SCL_FACTOR_CBR 0x00098
#define RK3399_WIN1_SCL_OFFSET 0x0009c
#define RK3399_WIN1_SRC_ALPHA_CTRL 0x000a0
#define RK3399_WIN1_DST_ALPHA_CTRL 0x000a4
#define RK3399_WIN1_FADING_CTRL 0x000a8
#define RK3399_WIN1_CTRL2 0x000ac
#define RK3399_WIN2_CTRL0 0x000b0
#define RK3399_WIN2_CTRL1 0x000b4
#define RK3399_WIN2_VIR0_1 0x000b8
#define RK3399_WIN2_VIR2_3 0x000bc
#define RK3399_WIN2_MST0 0x000c0
#define RK3399_WIN2_DSP_INFO0 0x000c4
#define RK3399_WIN2_DSP_ST0 0x000c8
#define RK3399_WIN2_COLOR_KEY 0x000cc
#define RK3399_WIN2_MST1 0x000d0
#define RK3399_WIN2_DSP_INFO1 0x000d4
#define RK3399_WIN2_DSP_ST1 0x000d8
#define RK3399_WIN2_SRC_ALPHA_CTRL 0x000dc
#define RK3399_WIN2_MST2 0x000e0
#define RK3399_WIN2_DSP_INFO2 0x000e4
#define RK3399_WIN2_DSP_ST2 0x000e8
#define RK3399_WIN2_DST_ALPHA_CTRL 0x000ec
#define RK3399_WIN2_MST3 0x000f0
#define RK3399_WIN2_DSP_INFO3 0x000f4
#define RK3399_WIN2_DSP_ST3 0x000f8
#define RK3399_WIN2_FADING_CTRL 0x000fc
#define RK3399_WIN3_CTRL0 0x00100
#define RK3399_WIN3_CTRL1 0x00104
#define RK3399_WIN3_VIR0_1 0x00108
#define RK3399_WIN3_VIR2_3 0x0010c
#define RK3399_WIN3_MST0 0x00110
#define RK3399_WIN3_DSP_INFO0 0x00114
#define RK3399_WIN3_DSP_ST0 0x00118
#define RK3399_WIN3_COLOR_KEY 0x0011c
#define RK3399_WIN3_MST1 0x00120
#define RK3399_WIN3_DSP_INFO1 0x00124
#define RK3399_WIN3_DSP_ST1 0x00128
#define RK3399_WIN3_SRC_ALPHA_CTRL 0x0012c
#define RK3399_WIN3_MST2 0x00130
#define RK3399_WIN3_DSP_INFO2 0x00134
#define RK3399_WIN3_DSP_ST2 0x00138
#define RK3399_WIN3_DST_ALPHA_CTRL 0x0013c
#define RK3399_WIN3_MST3 0x00140
#define RK3399_WIN3_DSP_INFO3 0x00144
#define RK3399_WIN3_DSP_ST3 0x00148
#define RK3399_WIN3_FADING_CTRL 0x0014c
#define RK3399_HWC_CTRL0 0x00150
#define RK3399_HWC_CTRL1 0x00154
#define RK3399_HWC_MST 0x00158
#define RK3399_HWC_DSP_ST 0x0015c
#define RK3399_HWC_SRC_ALPHA_CTRL 0x00160
#define RK3399_HWC_DST_ALPHA_CTRL 0x00164
#define RK3399_HWC_FADING_CTRL 0x00168
#define RK3399_HWC_RESERVED1 0x0016c
#define RK3399_POST_DSP_HACT_INFO 0x00170
#define RK3399_POST_DSP_VACT_INFO 0x00174
#define RK3399_POST_SCL_FACTOR_YRGB 0x00178
#define RK3399_POST_RESERVED 0x0017c
#define RK3399_POST_SCL_CTRL 0x00180
#define RK3399_POST_DSP_VACT_INFO_F1 0x00184
#define RK3399_DSP_HTOTAL_HS_END 0x00188
#define RK3399_DSP_HACT_ST_END 0x0018c
#define RK3399_DSP_VTOTAL_VS_END 0x00190
#define RK3399_DSP_VACT_ST_END 0x00194
#define RK3399_DSP_VS_ST_END_F1 0x00198
#define RK3399_DSP_VACT_ST_END_F1 0x0019c
#define RK3399_PWM_CTRL 0x001a0
#define RK3399_PWM_PERIOD_HPR 0x001a4
#define RK3399_PWM_DUTY_LPR 0x001a8
#define RK3399_PWM_CNT 0x001ac
#define RK3399_BCSH_COLOR_BAR 0x001b0
#define RK3399_BCSH_BCS 0x001b4
#define RK3399_BCSH_H 0x001b8
#define RK3399_BCSH_CTRL 0x001bc
#define RK3399_CABC_CTRL0 0x001c0
#define RK3399_CABC_CTRL1 0x001c4
#define RK3399_CABC_CTRL2 0x001c8
#define RK3399_CABC_CTRL3 0x001cc
#define RK3399_CABC_GAUSS_LINE0_0 0x001d0
#define RK3399_CABC_GAUSS_LINE0_1 0x001d4
#define RK3399_CABC_GAUSS_LINE1_0 0x001d8
#define RK3399_CABC_GAUSS_LINE1_1 0x001dc
#define RK3399_CABC_GAUSS_LINE2_0 0x001e0
#define RK3399_CABC_GAUSS_LINE2_1 0x001e4
#define RK3399_FRC_LOWER01_0 0x001e8
#define RK3399_FRC_LOWER01_1 0x001ec
#define RK3399_FRC_LOWER10_0 0x001f0
#define RK3399_FRC_LOWER10_1 0x001f4
#define RK3399_FRC_LOWER11_0 0x001f8
#define RK3399_FRC_LOWER11_1 0x001fc
#define RK3399_AFBCD0_CTRL 0x00200
#define RK3399_AFBCD0_HDR_PTR 0x00204
#define RK3399_AFBCD0_PIC_SIZE 0x00208
#define RK3399_AFBCD0_STATUS 0x0020c
#define RK3399_AFBCD1_CTRL 0x00220
#define RK3399_AFBCD1_HDR_PTR 0x00224
#define RK3399_AFBCD1_PIC_SIZE 0x00228
#define RK3399_AFBCD1_STATUS 0x0022c
#define RK3399_AFBCD2_CTRL 0x00240
#define RK3399_AFBCD2_HDR_PTR 0x00244
#define RK3399_AFBCD2_PIC_SIZE 0x00248
#define RK3399_AFBCD2_STATUS 0x0024c
#define RK3399_AFBCD3_CTRL 0x00260
#define RK3399_AFBCD3_HDR_PTR 0x00264
#define RK3399_AFBCD3_PIC_SIZE 0x00268
#define RK3399_AFBCD3_STATUS 0x0026c
#define RK3399_INTR_EN0 0x00280
#define RK3399_INTR_CLEAR0 0x00284
#define RK3399_INTR_STATUS0 0x00288
#define RK3399_INTR_RAW_STATUS0 0x0028c
#define RK3399_INTR_EN1 0x00290
#define RK3399_INTR_CLEAR1 0x00294
#define RK3399_INTR_STATUS1 0x00298
#define RK3399_INTR_RAW_STATUS1 0x0029c
#define RK3399_LINE_FLAG 0x002a0
#define RK3399_VOP_STATUS 0x002a4
#define RK3399_BLANKING_VALUE 0x002a8
#define RK3399_MCU_BYPASS_PORT 0x002ac
#define RK3399_WIN0_DSP_BG 0x002b0
#define RK3399_WIN1_DSP_BG 0x002b4
#define RK3399_WIN2_DSP_BG 0x002b8
#define RK3399_WIN3_DSP_BG 0x002bc
#define RK3399_YUV2YUV_WIN 0x002c0
#define RK3399_YUV2YUV_POST 0x002c4
#define RK3399_AUTO_GATING_EN 0x002cc
#define RK3399_WIN0_CSC_COE 0x003a0
#define RK3399_WIN1_CSC_COE 0x003c0
#define RK3399_WIN2_CSC_COE 0x003e0
#define RK3399_WIN3_CSC_COE 0x00400
#define RK3399_HWC_CSC_COE 0x00420
#define RK3399_BCSH_R2Y_CSC_COE 0x00440
#define RK3399_BCSH_Y2R_CSC_COE 0x00460
#define RK3399_POST_YUV2YUV_Y2R_COE 0x00480
#define RK3399_POST_YUV2YUV_3X3_COE 0x004a0
#define RK3399_POST_YUV2YUV_R2Y_COE 0x004c0
#define RK3399_WIN0_YUV2YUV_Y2R 0x004e0
#define RK3399_WIN0_YUV2YUV_3X3 0x00500
#define RK3399_WIN0_YUV2YUV_R2Y 0x00520
#define RK3399_WIN1_YUV2YUV_Y2R 0x00540
#define RK3399_WIN1_YUV2YUV_3X3 0x00560
#define RK3399_WIN1_YUV2YUV_R2Y 0x00580
#define RK3399_WIN2_YUV2YUV_Y2R 0x005a0
#define RK3399_WIN2_YUV2YUV_3X3 0x005c0
#define RK3399_WIN2_YUV2YUV_R2Y 0x005e0
#define RK3399_WIN3_YUV2YUV_Y2R 0x00600
#define RK3399_WIN3_YUV2YUV_3X3 0x00620
#define RK3399_WIN3_YUV2YUV_R2Y 0x00640
#define RK3399_WIN2_LUT_ADDR 0x01000
#define RK3399_WIN3_LUT_ADDR 0x01400
#define RK3399_HWC_LUT_ADDR 0x01800
#define RK3399_CABC_GAMMA_LUT_ADDR 0x01c00
#define RK3399_GAMMA_LUT_ADDR 0x02000
#define RK3399_REG_CFG_DONE 0x0000
#define RK3399_VERSION_INFO 0x0004
#define RK3399_SYS_CTRL 0x0008
#define RK3399_SYS_CTRL1 0x000c
#define RK3399_DSP_CTRL0 0x0010
#define RK3399_DSP_CTRL1 0x0014
#define RK3399_DSP_BG 0x0018
#define RK3399_MCU_CTRL 0x001c
#define RK3399_WB_CTRL0 0x0020
#define RK3399_WB_CTRL1 0x0024
#define RK3399_WB_YRGB_MST 0x0028
#define RK3399_WB_CBR_MST 0x002c
#define RK3399_WIN0_CTRL0 0x0030
#define RK3399_WIN0_CTRL1 0x0034
#define RK3399_WIN0_COLOR_KEY 0x0038
#define RK3399_WIN0_VIR 0x003c
#define RK3399_WIN0_YRGB_MST 0x0040
#define RK3399_WIN0_CBR_MST 0x0044
#define RK3399_WIN0_ACT_INFO 0x0048
#define RK3399_WIN0_DSP_INFO 0x004c
#define RK3399_WIN0_DSP_ST 0x0050
#define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054
#define RK3399_WIN0_SCL_FACTOR_CBR 0x0058
#define RK3399_WIN0_SCL_OFFSET 0x005c
#define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060
#define RK3399_WIN0_DST_ALPHA_CTRL 0x0064
#define RK3399_WIN0_FADING_CTRL 0x0068
#define RK3399_WIN0_CTRL2 0x006c
#define RK3399_WIN1_CTRL0 0x0070
#define RK3399_WIN1_CTRL1 0x0074
#define RK3399_WIN1_COLOR_KEY 0x0078
#define RK3399_WIN1_VIR 0x007c
#define RK3399_WIN1_YRGB_MST 0x0080
#define RK3399_WIN1_CBR_MST 0x0084
#define RK3399_WIN1_ACT_INFO 0x0088
#define RK3399_WIN1_DSP_INFO 0x008c
#define RK3399_WIN1_DSP_ST 0x0090
#define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094
#define RK3399_WIN1_SCL_FACTOR_CBR 0x0098
#define RK3399_WIN1_SCL_OFFSET 0x009c
#define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0
#define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4
#define RK3399_WIN1_FADING_CTRL 0x00a8
#define RK3399_WIN1_CTRL2 0x00ac
#define RK3399_WIN2_CTRL0 0x00b0
#define RK3399_WIN2_CTRL1 0x00b4
#define RK3399_WIN2_VIR0_1 0x00b8
#define RK3399_WIN2_VIR2_3 0x00bc
#define RK3399_WIN2_MST0 0x00c0
#define RK3399_WIN2_DSP_INFO0 0x00c4
#define RK3399_WIN2_DSP_ST0 0x00c8
#define RK3399_WIN2_COLOR_KEY 0x00cc
#define RK3399_WIN2_MST1 0x00d0
#define RK3399_WIN2_DSP_INFO1 0x00d4
#define RK3399_WIN2_DSP_ST1 0x00d8
#define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc
#define RK3399_WIN2_MST2 0x00e0
#define RK3399_WIN2_DSP_INFO2 0x00e4
#define RK3399_WIN2_DSP_ST2 0x00e8
#define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec
#define RK3399_WIN2_MST3 0x00f0
#define RK3399_WIN2_DSP_INFO3 0x00f4
#define RK3399_WIN2_DSP_ST3 0x00f8
#define RK3399_WIN2_FADING_CTRL 0x00fc
#define RK3399_WIN3_CTRL0 0x0100
#define RK3399_WIN3_CTRL1 0x0104
#define RK3399_WIN3_VIR0_1 0x0108
#define RK3399_WIN3_VIR2_3 0x010c
#define RK3399_WIN3_MST0 0x0110
#define RK3399_WIN3_DSP_INFO0 0x0114
#define RK3399_WIN3_DSP_ST0 0x0118
#define RK3399_WIN3_COLOR_KEY 0x011c
#define RK3399_WIN3_MST1 0x0120
#define RK3399_WIN3_DSP_INFO1 0x0124
#define RK3399_WIN3_DSP_ST1 0x0128
#define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c
#define RK3399_WIN3_MST2 0x0130
#define RK3399_WIN3_DSP_INFO2 0x0134
#define RK3399_WIN3_DSP_ST2 0x0138
#define RK3399_WIN3_DST_ALPHA_CTRL 0x013c
#define RK3399_WIN3_MST3 0x0140
#define RK3399_WIN3_DSP_INFO3 0x0144
#define RK3399_WIN3_DSP_ST3 0x0148
#define RK3399_WIN3_FADING_CTRL 0x014c
#define RK3399_HWC_CTRL0 0x0150
#define RK3399_HWC_CTRL1 0x0154
#define RK3399_HWC_MST 0x0158
#define RK3399_HWC_DSP_ST 0x015c
#define RK3399_HWC_SRC_ALPHA_CTRL 0x0160
#define RK3399_HWC_DST_ALPHA_CTRL 0x0164
#define RK3399_HWC_FADING_CTRL 0x0168
#define RK3399_HWC_RESERVED1 0x016c
#define RK3399_POST_DSP_HACT_INFO 0x0170
#define RK3399_POST_DSP_VACT_INFO 0x0174
#define RK3399_POST_SCL_FACTOR_YRGB 0x0178
#define RK3399_POST_RESERVED 0x017c
#define RK3399_POST_SCL_CTRL 0x0180
#define RK3399_POST_DSP_VACT_INFO_F1 0x0184
#define RK3399_DSP_HTOTAL_HS_END 0x0188
#define RK3399_DSP_HACT_ST_END 0x018c
#define RK3399_DSP_VTOTAL_VS_END 0x0190
#define RK3399_DSP_VACT_ST_END 0x0194
#define RK3399_DSP_VS_ST_END_F1 0x0198
#define RK3399_DSP_VACT_ST_END_F1 0x019c
#define RK3399_PWM_CTRL 0x01a0
#define RK3399_PWM_PERIOD_HPR 0x01a4
#define RK3399_PWM_DUTY_LPR 0x01a8
#define RK3399_PWM_CNT 0x01ac
#define RK3399_BCSH_COLOR_BAR 0x01b0
#define RK3399_BCSH_BCS 0x01b4
#define RK3399_BCSH_H 0x01b8
#define RK3399_BCSH_CTRL 0x01bc
#define RK3399_CABC_CTRL0 0x01c0
#define RK3399_CABC_CTRL1 0x01c4
#define RK3399_CABC_CTRL2 0x01c8
#define RK3399_CABC_CTRL3 0x01cc
#define RK3399_CABC_GAUSS_LINE0_0 0x01d0
#define RK3399_CABC_GAUSS_LINE0_1 0x01d4
#define RK3399_CABC_GAUSS_LINE1_0 0x01d8
#define RK3399_CABC_GAUSS_LINE1_1 0x01dc
#define RK3399_CABC_GAUSS_LINE2_0 0x01e0
#define RK3399_CABC_GAUSS_LINE2_1 0x01e4
#define RK3399_FRC_LOWER01_0 0x01e8
#define RK3399_FRC_LOWER01_1 0x01ec
#define RK3399_FRC_LOWER10_0 0x01f0
#define RK3399_FRC_LOWER10_1 0x01f4
#define RK3399_FRC_LOWER11_0 0x01f8
#define RK3399_FRC_LOWER11_1 0x01fc
#define RK3399_AFBCD0_CTRL 0x0200
#define RK3399_AFBCD0_HDR_PTR 0x0204
#define RK3399_AFBCD0_PIC_SIZE 0x0208
#define RK3399_AFBCD0_STATUS 0x020c
#define RK3399_AFBCD1_CTRL 0x0220
#define RK3399_AFBCD1_HDR_PTR 0x0224
#define RK3399_AFBCD1_PIC_SIZE 0x0228
#define RK3399_AFBCD1_STATUS 0x022c
#define RK3399_AFBCD2_CTRL 0x0240
#define RK3399_AFBCD2_HDR_PTR 0x0244
#define RK3399_AFBCD2_PIC_SIZE 0x0248
#define RK3399_AFBCD2_STATUS 0x024c
#define RK3399_AFBCD3_CTRL 0x0260
#define RK3399_AFBCD3_HDR_PTR 0x0264
#define RK3399_AFBCD3_PIC_SIZE 0x0268
#define RK3399_AFBCD3_STATUS 0x026c
#define RK3399_INTR_EN0 0x0280
#define RK3399_INTR_CLEAR0 0x0284
#define RK3399_INTR_STATUS0 0x0288
#define RK3399_INTR_RAW_STATUS0 0x028c
#define RK3399_INTR_EN1 0x0290
#define RK3399_INTR_CLEAR1 0x0294
#define RK3399_INTR_STATUS1 0x0298
#define RK3399_INTR_RAW_STATUS1 0x029c
#define RK3399_LINE_FLAG 0x02a0
#define RK3399_VOP_STATUS 0x02a4
#define RK3399_BLANKING_VALUE 0x02a8
#define RK3399_MCU_BYPASS_PORT 0x02ac
#define RK3399_WIN0_DSP_BG 0x02b0
#define RK3399_WIN1_DSP_BG 0x02b4
#define RK3399_WIN2_DSP_BG 0x02b8
#define RK3399_WIN3_DSP_BG 0x02bc
#define RK3399_YUV2YUV_WIN 0x02c0
#define RK3399_YUV2YUV_POST 0x02c4
#define RK3399_AUTO_GATING_EN 0x02cc
#define RK3399_WIN0_CSC_COE 0x03a0
#define RK3399_WIN1_CSC_COE 0x03c0
#define RK3399_WIN2_CSC_COE 0x03e0
#define RK3399_WIN3_CSC_COE 0x0400
#define RK3399_HWC_CSC_COE 0x0420
#define RK3399_BCSH_R2Y_CSC_COE 0x0440
#define RK3399_BCSH_Y2R_CSC_COE 0x0460
#define RK3399_POST_YUV2YUV_Y2R_COE 0x0480
#define RK3399_POST_YUV2YUV_3X3_COE 0x04a0
#define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0
#define RK3399_WIN0_YUV2YUV_Y2R 0x04e0
#define RK3399_WIN0_YUV2YUV_3X3 0x0500
#define RK3399_WIN0_YUV2YUV_R2Y 0x0520
#define RK3399_WIN1_YUV2YUV_Y2R 0x0540
#define RK3399_WIN1_YUV2YUV_3X3 0x0560
#define RK3399_WIN1_YUV2YUV_R2Y 0x0580
#define RK3399_WIN2_YUV2YUV_Y2R 0x05a0
#define RK3399_WIN2_YUV2YUV_3X3 0x05c0
#define RK3399_WIN2_YUV2YUV_R2Y 0x05e0
#define RK3399_WIN3_YUV2YUV_Y2R 0x0600
#define RK3399_WIN3_YUV2YUV_3X3 0x0620
#define RK3399_WIN3_YUV2YUV_R2Y 0x0640
#define RK3399_WIN2_LUT_ADDR 0x1000
#define RK3399_WIN3_LUT_ADDR 0x1400
#define RK3399_HWC_LUT_ADDR 0x1800
#define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00
#define RK3399_GAMMA_LUT_ADDR 0x2000
/* rk3399 register definition end */
/* rk3036 register definition */