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hdmitx: Coverity defect cleanup: VOUT [1/1]

Browse Source 
PD#SWPL-13989

Problem:
Coverity defect cleanup: VOUT

Solution:
Modify code according to coverity

Verify:
verify on the board of U212

Change-Id: I787429350be37da84ccd85332e97d472f45d3826
Signed-off-by: Zhengrong Zhu <zhengrong.zhu@amlogic.com>
This commit is contained in:
Zhengrong.Zhu
2019-11-02 10:01:55 +08:00
committed by Luke Go
parent 945467e74b
commit 18100c2b93
1 changed files with 3 additions and 25 deletions
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28
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
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@@ -1381,13 +1381,11 @@ static void hdmi_tvenc_vesa_set(struct hdmitx_vidpara *param)
unsigned long hsync_pixels_venc = 0;
unsigned long de_h_begin = 0, de_h_end = 0;
unsigned long de_v_begin_even = 0, de_v_end_even = 0,
de_v_begin_odd = 0, de_v_end_odd = 0;
unsigned long de_v_begin_even = 0, de_v_end_even = 0;
unsigned long hs_begin = 0, hs_end = 0;
unsigned long vs_adjust = 0;
unsigned long vs_bline_evn = 0, vs_eline_evn = 0,
vs_bline_odd = 0, vs_eline_odd = 0;
unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
unsigned long vs_bline_evn = 0, vs_eline_evn = 0;
unsigned long vso_begin_evn = 0;
struct hdmi_format_para *vpara = NULL;
struct hdmi_cea_timing *vtiming = NULL;
@@ -1438,15 +1436,6 @@ static void hdmi_tvenc_vesa_set(struct hdmitx_vidpara *param)
de_v_end_even = de_v_begin_even + ACTIVE_LINES;
hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */
/* Program DE timing for odd field if needed */
if (INTERLACE_MODE) {
de_v_begin_odd = to_signed(
(hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST)
& 0xf0)>>4) + de_v_begin_even + (TOTAL_LINES-1)/2;
de_v_end_odd = de_v_begin_odd + ACTIVE_LINES;
hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);
hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd);
}
/* Program Hsync timing */
if (de_h_end + front_porch_venc >= total_pixels_venc) {
@@ -1472,17 +1461,6 @@ static void hdmi_tvenc_vesa_set(struct hdmitx_vidpara *param)
vso_begin_evn = hs_begin; /* 1692 */
hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */
hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */
/* Program Vsync timing for odd field if needed */
if (INTERLACE_MODE) {
vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1),
total_pixels_venc);
hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
}
switch (param->VIC) {
case HDMIV_640x480p60hz: