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drm/rockchip: vop2: reset transform offset when exit from afbc format

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If cluster transform offset isn't equeal to 0 at linear format mode, VOP will appear
iommu pagefault error.

errr log:

[ 8283.190920][    C0] rk_iommu fdd97e00.iommu: Page fault at 0x00000000f20b1000 of type read
[ 8283.191012][    C0] [drm:rockchip_drm_fault_handler] *ERROR* iommu fault handler flags: 0x18b
...
[ 8283.191131][    C0] Video Port0: DISABLED
[ 8283.191153][    C0] Video Port1: DISABLED
[ 8283.191198][    C0] SYS:
[ 8283.191252][    C0] 00000000: 00008008 40176786 7fffffff 00000000
[ 8283.191281][    C0] 00000010: 00000000 00000000 00000000 00000000
...
[ 8283.191715][    C0] OVL:
[ 8283.191765][    C0] 00000000: c0000000 75643120 e4e47531 00000000
[ 8283.191792][    C0] 00000010: 00000000 00000000 00000000 00000000
...
[ 8283.195257][    C0] Cluster3:
[ 8283.195306][    C0] 00000000: 00004001 00000000 000000e6 00000000
[ 8283.195333][    C0] 00000010: f2057000 00000000 00000030 00000000
[ 8283.195361][    C0] 00000020: 077f002f 077f002f 00000408 00000000
[ 8283.195389][    C0] 00000030: 00000000 00000000 00000000 00020009
[ 8283.195417][    C0] 00000040: 00000000 00000000 00000000 00000000
[ 8283.195445][    C0] 00000050: 00000010 00000000 f396a000 00290500
[ 8283.195473][    C0] 00000060: 048b028d 003a0139 00000000 00000094
...

[ 8283.199008][    C0] rockchip-vop2 fdd90000.vop: [drm:vop2_isr] *ERROR* POST_BUF_EMPTY irq err at vp3
[ 8283.199303][    C0] rockchip-vop2 fdd90000.vop: [drm:vop2_isr] *ERROR* POST_BUF_EMPTY irq err at vp3
[ 8283.199377][    C0] rockchip-vop2 fdd90000.vop: [drm:vop2_isr] *ERROR* POST_BUF_EMPTY irq err at vp3

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ib490796e1da568069f78ed35b2287a5fe32033d9
This commit is contained in:
Sandy Huang
2022-04-13 14:51:07 +08:00
committed by Tao Huang
parent a0dfa37898
commit 183bc1a692
1 changed files with 1 additions and 0 deletions
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1
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -4470,6 +4470,7 @@ static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, s
VOP_AFBC_SET(vop2, win, rotate_90, vpstate->rotate_90_en);
} else {
VOP_CLUSTER_SET(vop2, win, afbc_enable, 0);
VOP_AFBC_SET(vop2, win, transform_offset, 0);
VOP_WIN_SET(vop2, win, ymirror, vpstate->ymirror_en);
VOP_WIN_SET(vop2, win, xmirror, vpstate->xmirror_en);
}