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synced 2026-03-24 19:40:21 +09:00
ether: support eth1
test: ifconfig eth1 192.168.1.99; ping 192.168.1.10 by default pc ethernet is 100M, also can work Can be change via command: host: sudo ethtool eth0 sudo ethtool -s eth0 duplex full speed 1000 Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
This commit is contained in:
Zhangfei Gao
committed by
Andrey Konovalov
Andrey Konovalov
parent
83fb568563
commit
18adbd115f
@@ -14,6 +14,8 @@
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/dmapool.h>
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#include <linux/phy.h>
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#include <linux/of_mdio.h>
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#define PPE_CFG_RX_CFF_ADDR 0x100
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#define PPE_CFG_POOL_GRP 0x300
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@@ -36,6 +38,18 @@
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#define PPE_CFG_STS_MODE 0x700
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#define PPE_HIS_RX_PKT_CNT 0x804
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#define GE_MAX_FRM_SIZE_REG 0x3c
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#define GE_SHORT_RUNTS_THR_REG 0x50
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#define GE_TX_LOCAL_PAGE_REG 0x5c
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#define GE_TRANSMIT_CONTROL_REG 0x60
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#define GE_CF_CRC_STRIP_REG 0x1b0
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#define GE_RECV_CONTROL_REG 0x1e0
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#define PPE_CFG_MAX_FRAME_LEN_REG 0x408
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#define PPE_CFG_BUS_CTRL_REG 0x424
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#define PPE_CFG_RX_PKT_MODE_REG 0x438
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#define GMAC_PPE_RX_PKT_MAX_LEN (379)
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#define GMAC_MAX_PKT_LEN 1516
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/* REG_INTERRUPT_MASK */
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#define RCV_INT BIT(10)
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#define RCV_NOBUF BIT(8)
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@@ -71,6 +85,7 @@ struct hip04_priv {
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void __iomem *base;
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unsigned int port;
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unsigned int speed;
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unsigned int duplex;
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unsigned int id;
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unsigned int reg_inten;
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@@ -90,6 +105,9 @@ struct hip04_priv {
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unsigned char *rx_buf[RX_DESC_NUM];
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unsigned int rx_head;
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unsigned int rx_buf_size;
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struct device_node *phy_node;
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struct phy_device *phy;
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};
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static void __iomem *ppebase;
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@@ -98,106 +116,39 @@ static void hip04_config_port(struct hip04_priv *priv, u32 speed, u32 duplex)
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{
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u32 val, reg;
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priv->speed = speed;
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priv->duplex = duplex;
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switch (speed) {
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case SPEED_1000:
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reg = 8;
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break;
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case SPEED_100:
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reg = 1;
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if (!priv->id)
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reg = 1;
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else
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reg = 7;
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break;
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default:
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reg = 0;
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break;
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}
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val = readl_relaxed(priv->base + GE_PORT_MODE);
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val &= ~(0xf);
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val |= reg;
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writel_relaxed(val, priv->base + GE_PORT_MODE);
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reg = (duplex) ? BIT(1) : BIT(0);
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reg = (duplex) ? BIT(0) : 0;
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val = readl_relaxed(priv->base + GE_DUPLEX_TYPE);
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val &= ~(0x1);
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val |= reg;
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writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
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val = readl_relaxed(priv->base + GE_MODE_CHANGE_EN);
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val |= BIT(1);
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val |= BIT(0);
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writel_relaxed(val, priv->base + GE_MODE_CHANGE_EN);
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}
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#ifdef OBSOLETE_CONFIG
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#define GE_MAX_FRM_SIZE_REG 0x3c
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#define GE_SHORT_RUNTS_THR_REG 0x50
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#define GE_TX_LOCAL_PAGE_REG 0x5c
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#define GE_TRANSMIT_CONTROL_REG 0x60
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#define GE_CF_CRC_STRIP_REG 0x1b0
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#define GE_RECV_CONTROL_REG 0x1e0
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#define PPE_CFG_MAX_FRAME_LEN_REG 0x408
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#define PPE_CFG_BUS_CTRL_REG 0x424
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#define PPE_CFG_RX_PKT_MODE_REG 0x438
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#define GMAC_PPE_RX_PKT_MAX_LEN (379)
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#define GMAC_MAX_PKT_LEN 1516
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static void hip04_test_config(struct hip04_priv *priv)
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{
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u32 val;
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/* pkt mode */
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val = readl_relaxed(priv->base + PPE_CFG_RX_PKT_MODE_REG);
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val &= ~(0xc0000); /* [19:18] */
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val |= 1 << 18; /* align */
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writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
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/* set bus ctrl */
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val = 1 << 14; /* buffer locally release */
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val |= 1; /* big endian */
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/* fixme: fe only ?*/
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val &= ~BIT(7); /* disable poe */
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writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
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/* set max pkt len, curtail if exceed */
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val = readl_relaxed(priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
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val &= ~(0x3fff); /* [13:0]*/
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val |= GMAC_PPE_RX_PKT_MAX_LEN; /* max buffer len */
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writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
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/* set max len of each pkt */
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val = readl_relaxed(priv->base + GE_MAX_FRM_SIZE_REG);
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val &= ~(0xffff); /* [15:0]*/
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val |= GMAC_MAX_PKT_LEN; /* max buffer len */
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writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
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/* set min len of each pkt */
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val = readl_relaxed(priv->base + GE_SHORT_RUNTS_THR_REG);
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val |= 31; /* min buffer len */
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writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
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/* tx */
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val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
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val |= 1 << 5; /* tx auto neg */
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val |= 1 << 6; /* tx add crc */
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val |= 1 << 7; /* tx short pad through */
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writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
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/* rx crc */
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val = readl_relaxed(priv->base + GE_CF_CRC_STRIP_REG);
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val |= 1; /* rx strip crc */
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writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
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/* rx pad */
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val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
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val |= 1 << 3; /* rx strip pad */
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writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
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/* auto neg control */
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val = readl_relaxed(priv->base + GE_TX_LOCAL_PAGE_REG);
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val |= 1;
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val &= ~(0x1e0); /* [8:5] = 0*/
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val &= ~(0x3c0); /* [13:10] = 0*/
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val &= ~(0x8000); /* [15] = 0*/
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writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
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}
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#endif
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static void hip04_reset_ppe(struct hip04_priv *priv)
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{
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u32 val;
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@@ -244,6 +195,61 @@ static void hip04_config_fifo(struct hip04_priv *priv)
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val &= ~(0x1f80f); /* [16:11] [3:0]*/
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val |= 2 << 11; /* align */
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writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
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/* following cfg required for 1000M */
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/* pkt mode */
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val = readl_relaxed(priv->base + PPE_CFG_RX_PKT_MODE_REG);
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val &= ~(0xc0000); /* [19:18] */
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val |= 1 << 18; /* align */
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writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
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/* set bus ctrl */
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val = 1 << 14; /* buffer locally release */
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val |= 1; /* big endian */
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writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
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/* set max pkt len, curtail if exceed */
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val = readl_relaxed(priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
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val &= ~(0x3fff); /* [13:0]*/
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val |= GMAC_PPE_RX_PKT_MAX_LEN; /* max buffer len */
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writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
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/* set max len of each pkt */
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val = readl_relaxed(priv->base + GE_MAX_FRM_SIZE_REG);
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val &= ~(0xffff); /* [15:0]*/
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val |= GMAC_MAX_PKT_LEN; /* max buffer len */
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writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
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/* set min len of each pkt */
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val = readl_relaxed(priv->base + GE_SHORT_RUNTS_THR_REG);
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val |= 31; /* min buffer len */
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writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
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/* tx */
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val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
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val |= 1 << 5; /* tx auto neg */
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val |= 1 << 6; /* tx add crc */
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val |= 1 << 7; /* tx short pad through */
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writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
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/* rx crc */
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val = readl_relaxed(priv->base + GE_CF_CRC_STRIP_REG);
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val |= 1; /* rx strip crc */
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writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
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/* rx */
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val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
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val |= 1 << 3; /* rx strip pad */
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val |= 1 << 4; /* run pkt en */
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writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
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/* auto neg control */
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val = readl_relaxed(priv->base + GE_TX_LOCAL_PAGE_REG);
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val |= 1;
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val &= ~(0x1e0); /* [8:5] = 0*/
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val &= ~(0x3c0); /* [13:10] = 0*/
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val &= ~(0x8000); /* [15] = 0*/
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writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
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}
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static void hip04_mac_enable(struct net_device *ndev, bool enable)
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@@ -502,6 +508,15 @@ out_unlock:
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return ret;
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}
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static void hip04_adjust_link(struct net_device *ndev)
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{
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struct hip04_priv *priv = netdev_priv(ndev);
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struct phy_device *phy = priv->phy;
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if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex))
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hip04_config_port(priv, phy->speed, phy->duplex);
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}
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static int hip04_mac_open(struct net_device *ndev)
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{
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struct hip04_priv *priv = netdev_priv(ndev);
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@@ -520,6 +535,14 @@ static int hip04_mac_open(struct net_device *ndev)
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priv->tx_tail = 0;
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priv->tx_count = 0;
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if (priv->phy_node) {
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priv->phy = of_phy_connect(ndev, priv->phy_node,
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&hip04_adjust_link, 0, PHY_INTERFACE_MODE_GMII);
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if (!priv->phy)
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return -ENODEV;
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phy_start(priv->phy);
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}
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netif_start_queue(ndev);
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hip04_mac_enable(ndev, true);
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napi_enable(&priv->napi);
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@@ -663,7 +686,7 @@ static int hip04_mac_probe(struct platform_device *pdev)
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if (!ppebase) {
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struct device_node *n;
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n = of_find_compatible_node(NULL, NULL, "hisilicon,ppebase");
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n = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-ppebase");
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if (!n) {
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ret = -EINVAL;
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netdev_err(ndev, "not find hisilicon,ppebase\n");
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@@ -689,6 +712,7 @@ static int hip04_mac_probe(struct platform_device *pdev)
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priv->speed = SPEED_100;
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else
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priv->speed = SPEED_1000;
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priv->duplex = DUPLEX_FULL;
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/* fixme any id can be used directly? */
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ret = of_property_read_u32(node, "id", &priv->id);
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@@ -710,7 +734,7 @@ static int hip04_mac_probe(struct platform_device *pdev)
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SET_NETDEV_DEV(ndev, &pdev->dev);
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hip04_reset_ppe(priv);
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hip04_config_port(priv, priv->speed, DUPLEX_FULL);
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hip04_config_port(priv, priv->speed, priv->duplex);
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hip04_config_fifo(priv);
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random_ether_addr(ndev->dev_addr);
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hip04_update_mac_address(ndev);
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@@ -730,6 +754,8 @@ static int hip04_mac_probe(struct platform_device *pdev)
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goto init_fail;
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}
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priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
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ret = register_netdev(ndev);
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if (ret) {
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free_netdev(ndev);
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@@ -740,6 +766,7 @@ static int hip04_mac_probe(struct platform_device *pdev)
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alloc_fail:
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hip04_free_ring(ndev);
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init_fail:
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of_node_put(priv->phy_node);
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free_netdev(ndev);
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return ret;
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}
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@@ -747,11 +774,13 @@ init_fail:
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static int hip04_remove(struct platform_device *pdev)
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{
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struct net_device *ndev = platform_get_drvdata(pdev);
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struct hip04_priv *priv = netdev_priv(ndev);
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unregister_netdev(ndev);
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free_irq(ndev->irq, ndev);
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free_netdev(ndev);
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free_netdev(ndev);
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of_node_put(priv->phy_node);
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return 0;
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}
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