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[riscv64] Backport kernel image header support from kernel 5.3
This patch adds a header to the kernel image that allows bootloaders such as u-boot to properly load plain kernel images instead of requiring uImage-wrapped kernels. That also enables the use of syslinux-style boot menus in u-boot on riscv64.
This commit is contained in:
Karsten Merker
217
debian/patches/features/riscv64/RISC-V-Add-Image-header.patch
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217
debian/patches/features/riscv64/RISC-V-Add-Image-header.patch
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From 0f327f2aaad6a87356cbccfa390d4d3b64d0d3b6 Mon Sep 17 00:00:00 2001
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From: Atish Patra <atish.patra@wdc.com>
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Date: Thu, 6 Jun 2019 16:08:00 -0700
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Subject: RISC-V: Add an Image header that boot loader can parse.
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Origin: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/?id=0f327f2aaad6a87356cbccfa390d4d3b64d0d3b6
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Currently, the last stage boot loaders such as U-Boot can accept only
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uImage which is an unnecessary additional step in automating boot
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process.
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Add an image header that boot loader understands and boot Linux from
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flat Image directly.
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This header is based on ARM64 boot image header and provides an
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opportunity to combine both ARM64 & RISC-V image headers in future.
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Also make sure that PE/COFF header can co-exist in the same image so
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that EFI stub can be supported for RISC-V in future. EFI specification
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needs PE/COFF image header in the beginning of the kernel image in order
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to load it as an EFI application. In order to support EFI stub, code0
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should be replaced with "MZ" magic string and res4(at offset 0x3c)
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should point to the rest of the PE/COFF header (which will be added
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during EFI support).
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Tested on both QEMU and HiFive Unleashed using OpenSBI + U-Boot + Linux.
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Signed-off-by: Atish Patra <atish.patra@wdc.com>
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Reviewed-by: Karsten Merker <merker@debian.org>
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Tested-by: Karsten Merker <merker@debian.org> (QEMU+OpenSBI+U-Boot)
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Tested-by: Kevin Hilman <khilman@baylibre.com> (OpenSBI + U-Boot + Linux)
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[paul.walmsley@sifive.com: fixed whitespace in boot-image-header.txt;
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converted structure comment to kernel-doc format and added some detail]
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Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
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---
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Documentation/riscv/boot-image-header.txt | 50 ++++++++++++++++++++++++
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arch/riscv/include/asm/image.h | 65 +++++++++++++++++++++++++++++++
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arch/riscv/kernel/head.S | 32 +++++++++++++++
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3 files changed, 147 insertions(+)
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create mode 100644 Documentation/riscv/boot-image-header.txt
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create mode 100644 arch/riscv/include/asm/image.h
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diff --git a/Documentation/riscv/boot-image-header.txt b/Documentation/riscv/boot-image-header.txt
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new file mode 100644
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index 000000000000..1b73fea23b39
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--- /dev/null
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+++ b/Documentation/riscv/boot-image-header.txt
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@@ -0,0 +1,50 @@
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+ Boot image header in RISC-V Linux
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+ =============================================
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+
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+Author: Atish Patra <atish.patra@wdc.com>
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+Date : 20 May 2019
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+
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+This document only describes the boot image header details for RISC-V Linux.
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+The complete booting guide will be available at Documentation/riscv/booting.txt.
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+
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+The following 64-byte header is present in decompressed Linux kernel image.
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+
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+ u32 code0; /* Executable code */
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+ u32 code1; /* Executable code */
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+ u64 text_offset; /* Image load offset, little endian */
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+ u64 image_size; /* Effective Image size, little endian */
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+ u64 flags; /* kernel flags, little endian */
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+ u32 version; /* Version of this header */
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+ u32 res1 = 0; /* Reserved */
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+ u64 res2 = 0; /* Reserved */
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+ u64 magic = 0x5643534952; /* Magic number, little endian, "RISCV" */
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+ u32 res3; /* Reserved for additional RISC-V specific header */
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+ u32 res4; /* Reserved for PE COFF offset */
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+
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+This header format is compliant with PE/COFF header and largely inspired from
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+ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
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+header in future.
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+
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+Notes:
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+- This header can also be reused to support EFI stub for RISC-V in future. EFI
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+ specification needs PE/COFF image header in the beginning of the kernel image
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+ in order to load it as an EFI application. In order to support EFI stub,
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+ code0 should be replaced with "MZ" magic string and res5(at offset 0x3c) should
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+ point to the rest of the PE/COFF header.
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+
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+- version field indicate header version number.
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+ Bits 0:15 - Minor version
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+ Bits 16:31 - Major version
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+
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+ This preserves compatibility across newer and older version of the header.
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+ The current version is defined as 0.1.
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+
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+- res3 is reserved for offset to any other additional fields. This makes the
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+ header extendible in future. One example would be to accommodate ISA
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+ extension for RISC-V in future. For current version, it is set to be zero.
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+
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+- In current header, the flag field has only one field.
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+ Bit 0: Kernel endianness. 1 if BE, 0 if LE.
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+
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+- Image size is mandatory for boot loader to load kernel image. Booting will
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+ fail otherwise.
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diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h
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new file mode 100644
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index 000000000000..ef28e106f247
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--- /dev/null
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+++ b/arch/riscv/include/asm/image.h
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@@ -0,0 +1,65 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+
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+#ifndef __ASM_IMAGE_H
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+#define __ASM_IMAGE_H
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+
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+#define RISCV_IMAGE_MAGIC "RISCV"
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+
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+#define RISCV_IMAGE_FLAG_BE_SHIFT 0
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+#define RISCV_IMAGE_FLAG_BE_MASK 0x1
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+
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+#define RISCV_IMAGE_FLAG_LE 0
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+#define RISCV_IMAGE_FLAG_BE 1
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+
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+#ifdef CONFIG_CPU_BIG_ENDIAN
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+#error conversion of header fields to LE not yet implemented
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+#else
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+#define __HEAD_FLAG_BE RISCV_IMAGE_FLAG_LE
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+#endif
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+
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+#define __HEAD_FLAG(field) (__HEAD_FLAG_##field << \
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+ RISCV_IMAGE_FLAG_##field##_SHIFT)
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+
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+#define __HEAD_FLAGS (__HEAD_FLAG(BE))
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+
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+#define RISCV_HEADER_VERSION_MAJOR 0
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+#define RISCV_HEADER_VERSION_MINOR 1
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+
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+#define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 | \
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+ RISCV_HEADER_VERSION_MINOR)
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+
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+#ifndef __ASSEMBLY__
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+/**
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+ * struct riscv_image_header - riscv kernel image header
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+ * @code0: Executable code
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+ * @code1: Executable code
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+ * @text_offset: Image load offset (little endian)
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+ * @image_size: Effective Image size (little endian)
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+ * @flags: kernel flags (little endian)
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+ * @version: version
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+ * @res1: reserved
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+ * @res2: reserved
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+ * @magic: Magic number
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+ * @res3: reserved (will be used for additional RISC-V specific
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+ * header)
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+ * @res4: reserved (will be used for PE COFF offset)
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+ *
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+ * The intention is for this header format to be shared between multiple
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+ * architectures to avoid a proliferation of image header formats.
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+ */
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+
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+struct riscv_image_header {
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+ u32 code0;
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+ u32 code1;
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+ u64 text_offset;
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+ u64 image_size;
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+ u64 flags;
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+ u32 version;
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+ u32 res1;
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+ u64 res2;
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+ u64 magic;
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+ u32 res3;
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+ u32 res4;
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+};
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+#endif /* __ASSEMBLY__ */
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+#endif /* __ASM_IMAGE_H */
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diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
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index e368106f2228..0f1ba17e476f 100644
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--- a/arch/riscv/kernel/head.S
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+++ b/arch/riscv/kernel/head.S
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@@ -11,9 +11,41 @@
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#include <asm/thread_info.h>
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#include <asm/page.h>
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#include <asm/csr.h>
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+#include <asm/image.h>
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__INIT
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ENTRY(_start)
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+ /*
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+ * Image header expected by Linux boot-loaders. The image header data
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+ * structure is described in asm/image.h.
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+ * Do not modify it without modifying the structure and all bootloaders
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+ * that expects this header format!!
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+ */
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+ /* jump to start kernel */
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+ j _start_kernel
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+ /* reserved */
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+ .word 0
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+ .balign 8
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+#if __riscv_xlen == 64
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+ /* Image load offset(2MB) from start of RAM */
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+ .dword 0x200000
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+#else
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+ /* Image load offset(4MB) from start of RAM */
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+ .dword 0x400000
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+#endif
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+ /* Effective size of kernel image */
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+ .dword _end - _start
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+ .dword __HEAD_FLAGS
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+ .word RISCV_HEADER_VERSION
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+ .word 0
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+ .dword 0
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+ .asciz RISCV_IMAGE_MAGIC
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+ .word 0
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+ .balign 4
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+ .word 0
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+
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+.global _start_kernel
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+_start_kernel:
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/* Mask all interrupts */
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csrw CSR_SIE, zero
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csrw CSR_SIP, zero
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--
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cgit 1.2-0.3.lf.el7
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1
debian/patches/series
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1
debian/patches/series
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@@ -76,6 +76,7 @@ features/mips/MIPS-increase-MAX-PHYSMEM-BITS-on-Loongson-3-only.patch
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features/mips/MIPS-Loongson-3-Add-Loongson-LS3A-RS780E-1-way-machi.patch
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features/x86/x86-memtest-WARN-if-bad-RAM-found.patch
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features/x86/x86-make-x32-syscall-support-conditional.patch
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features/riscv64/RISC-V-Add-Image-header.patch
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# Miscellaneous bug fixes
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bugfix/all/disable-some-marvell-phys.patch
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