shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 03:15:31 +09:00
Code Issues Packages Projects Releases Wiki Activity

video: rockchip: rga3: move rga*_ops to rga*_reg_info.h

Browse Source 
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I8f81e5b11873af76e32dc112dd89a1bc0ef4bcf5
This commit is contained in:
Yu Qiaowei
2022-10-27 16:57:29 +08:00
committed by Tao Huang
parent 1514f2ab39
commit 19805cc2b8
8 changed files with 153 additions and 176 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/video/rockchip/rga3/include/rga2_reg_info.h
View File

@@ -440,14 +440,7 @@
#define s_RGA2_MMU_CTRL1_SW_ELS_MMU_EN(x) ((x & 0x1) << 12)
#define s_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH(x) ((x & 0x1) << 13)
int rga2_gen_reg_info(unsigned char *base, struct rga2_req *msg);
void rga2_soft_reset(struct rga_scheduler_t *scheduler);
int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler);
int rga2_init_reg(struct rga_job *job);
int rga2_get_version(struct rga_scheduler_t *scheduler);
void rga2_dump_read_back_reg(struct rga_scheduler_t *scheduler);
int rga2_read_back_reg(struct rga_job *job, struct rga_scheduler_t *scheduler);
extern const struct rga_backend_ops rga2_ops;
#endif

9
drivers/video/rockchip/rga3/include/rga3_reg_info.h
View File

@@ -499,14 +499,7 @@
#define RGA3_ROT_BIT_X_MIRROR BIT(1)
#define RGA3_ROT_BIT_Y_MIRROR BIT(2)
int rga3_gen_reg_info(unsigned char *base, struct rga3_req *msg);
void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req);
//void RGA_MSG_2_RGA3_MSG_32(struct rga_req_32 *req_rga, struct rga3_req *req);
void rga3_soft_reset(struct rga_scheduler_t *scheduler);
int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler);
int rga3_init_reg(struct rga_job *job);
int rga3_get_version(struct rga_scheduler_t *scheduler);
extern const struct rga_backend_ops rga3_ops;
#endif

4
drivers/video/rockchip/rga3/include/rga_drv.h
View File

@@ -295,6 +295,8 @@ struct rga_backend_ops {
int (*init_reg)(struct rga_job *job);
void (*soft_reset)(struct rga_scheduler_t *scheduler);
int (*read_back_reg)(struct rga_job *job, struct rga_scheduler_t *scheduler);
int (*irq)(struct rga_scheduler_t *scheduler);
int (*isr_thread)(struct rga_job *job, struct rga_scheduler_t *scheduler);
};
struct rga_timer {
@@ -424,8 +426,6 @@ struct rga_irqs_data_t {
struct rga_match_data_t {
const char * const *clks;
int num_clks;
const struct rga_irqs_data_t *irqs;
int num_irqs;
};
static inline int rga_read(int offset, struct rga_scheduler_t *scheduler)

3
drivers/video/rockchip/rga3/include/rga_job.h
View File

@@ -22,7 +22,8 @@ enum job_flags {
};
void rga_job_scheduler_dump_info(struct rga_scheduler_t *scheduler);
void rga_job_done(struct rga_scheduler_t *scheduler, int ret);
void rga_job_next(struct rga_scheduler_t *scheduler);
struct rga_job *rga_job_done(struct rga_scheduler_t *scheduler);
struct rga_job *rga_job_commit(struct rga_req *rga_command_base, struct rga_request *request);
int rga_job_mpi_commit(struct rga_req *rga_command_base, struct rga_request *request);

63
drivers/video/rockchip/rga3/rga2_reg_info.c
View File

@@ -7,7 +7,6 @@
#define pr_fmt(fmt) "rga2_reg: " fmt
#include "rga_job.h"
#include "rga2_reg_info.h"
#include "rga_dma_buf.h"
#include "rga_iommu.h"
@@ -1715,7 +1714,7 @@ static void RGA2_set_mmu_reg_info(u8 *base, struct rga2_req *msg)
*bRGA_MMU_ELS_BASE = (u32) (msg->mmu_info.els_base_addr) >> 4;
}
int rga2_gen_reg_info(u8 *base, struct rga2_req *msg)
static int rga2_gen_reg_info(u8 *base, struct rga2_req *msg)
{
u8 dst_nn_quantize_en = 0;
@@ -2060,7 +2059,7 @@ static void rga_cmd_to_rga2_cmd(struct rga_scheduler_t *scheduler,
}
}
void rga2_soft_reset(struct rga_scheduler_t *scheduler)
static void rga2_soft_reset(struct rga_scheduler_t *scheduler)
{
u32 i;
u32 reg;
@@ -2217,7 +2216,7 @@ static void print_debug_info(struct rga2_req *req)
pr_info("yuv2rgb mode is %x\n", req->yuv2rgb_mode);
}
int rga2_init_reg(struct rga_job *job)
static int rga2_init_reg(struct rga_job *job)
{
struct rga2_req req;
int ret = 0;
@@ -2340,7 +2339,7 @@ static void rga2_dump_read_back_cmd_reg(struct rga_scheduler_t *scheduler)
cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
}
void rga2_dump_read_back_reg(struct rga_scheduler_t *scheduler)
static void rga2_dump_read_back_reg(struct rga_scheduler_t *scheduler)
{
rga2_dump_read_back_sys_reg(scheduler);
rga2_dump_read_back_csc_reg(scheduler);
@@ -2409,7 +2408,7 @@ static void rga2_set_reg_full_csc(struct rga_job *job, struct rga_scheduler_t *s
rga_write(job->full_csc.coe_v.off, RGA2_DST_CSC_OFF2, scheduler);
}
int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
int i;
uint32_t sys_ctrl;
@@ -2485,7 +2484,7 @@ int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
return 0;
}
int rga2_get_version(struct rga_scheduler_t *scheduler)
static int rga2_get_version(struct rga_scheduler_t *scheduler)
{
u32 major_version, minor_version, svn_version;
u32 reg_version;
@@ -2517,7 +2516,7 @@ int rga2_get_version(struct rga_scheduler_t *scheduler)
return 0;
}
int rga2_read_back_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
static int rga2_read_back_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
if (job->rga_command_base.osd_info.enable) {
job->rga_command_base.osd_info.cur_flags0 = rga_read(RGA2_OSD_CUR_FLAGS0,
@@ -2528,3 +2527,51 @@ int rga2_read_back_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
return 0;
}
static int rga2_irq(struct rga_scheduler_t *scheduler)
{
if (DEBUGGER_EN(INT_FLAG))
pr_info("irq handler, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
rga_read(RGA2_INT, scheduler),
rga_read(RGA2_STATUS2, scheduler),
rga_read(RGA2_STATUS1, scheduler));
/*if error interrupt then soft reset hardware */
if (rga_read(RGA2_INT, scheduler) & m_RGA2_INT_ERROR_FLAG_MASK) {
pr_err("irq handler err! INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
rga_read(RGA2_INT, scheduler),
rga_read(RGA2_STATUS2, scheduler),
rga_read(RGA2_STATUS1, scheduler));
scheduler->ops->soft_reset(scheduler);
}
/*clear INTR */
rga_write(rga_read(RGA2_INT, scheduler) |
(m_RGA2_INT_ERROR_CLEAR_MASK |
m_RGA2_INT_ALL_CMD_DONE_INT_CLEAR | m_RGA2_INT_NOW_CMD_DONE_INT_CLEAR |
m_RGA2_INT_LINE_RD_CLEAR | m_RGA2_INT_LINE_WR_CLEAR),
RGA2_INT, scheduler);
return IRQ_WAKE_THREAD;
}
static int rga2_isr_thread(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
if (DEBUGGER_EN(INT_FLAG))
pr_info("isr thread, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
rga_read(RGA2_INT, scheduler),
rga_read(RGA2_STATUS2, scheduler),
rga_read(RGA2_STATUS1, scheduler));
return IRQ_HANDLED;
}
const struct rga_backend_ops rga2_ops = {
.get_version = rga2_get_version,
.set_reg = rga2_set_reg,
.init_reg = rga2_init_reg,
.soft_reset = rga2_soft_reset,
.read_back_reg = rga2_read_back_reg,
.irq = rga2_irq,
.isr_thread = rga2_isr_thread,
};

60
drivers/video/rockchip/rga3/rga3_reg_info.c
View File

@@ -1141,7 +1141,7 @@ static void RGA3_set_reg_overlap_info(u8 *base, struct rga3_req *msg)
*bRGA3_OVLP_OFF = msg->wr.x_offset | (msg->wr.y_offset << 16);
}
int rga3_gen_reg_info(u8 *base, struct rga3_req *msg)
static int rga3_gen_reg_info(u8 *base, struct rga3_req *msg)
{
switch (msg->render_mode) {
case BITBLT_MODE:
@@ -1225,7 +1225,7 @@ static void set_wr_info(struct rga_req *req_rga, struct rga3_req *req)
}
/* TODO: common part */
void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
{
u16 alpha_mode_0, alpha_mode_1;
struct rga_img_info_t tmp;
@@ -1589,7 +1589,7 @@ void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
}
}
void rga3_soft_reset(struct rga_scheduler_t *scheduler)
static void rga3_soft_reset(struct rga_scheduler_t *scheduler)
{
u32 i;
u32 reg;
@@ -1624,7 +1624,7 @@ void rga3_soft_reset(struct rga_scheduler_t *scheduler)
rga_write(0, RGA3_MMU_COMMAND, scheduler);
if (DEBUGGER_EN(INT_FLAG))
pr_info("soft reset, INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n",
pr_info("soft reset, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
rga_read(RGA3_INT_RAW, scheduler),
rga_read(RGA3_STATUS0, scheduler),
rga_read(RGA3_CMD_STATE, scheduler));
@@ -1839,7 +1839,7 @@ static int rga3_align_check(struct rga3_req *req)
return 0;
}
int rga3_init_reg(struct rga_job *job)
static int rga3_init_reg(struct rga_job *job)
{
struct rga3_req req;
int ret = 0;
@@ -1896,7 +1896,7 @@ static void rga3_dump_read_back_reg(struct rga_scheduler_t *scheduler)
cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
}
int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
static int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
int i;
uint32_t sys_ctrl;
@@ -1959,7 +1959,7 @@ int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
return 0;
}
int rga3_get_version(struct rga_scheduler_t *scheduler)
static int rga3_get_version(struct rga_scheduler_t *scheduler)
{
u32 major_version, minor_version, svn_version;
u32 reg_version;
@@ -1984,3 +1984,49 @@ int rga3_get_version(struct rga_scheduler_t *scheduler)
return 0;
}
static int rga3_irq(struct rga_scheduler_t *scheduler)
{
if (DEBUGGER_EN(INT_FLAG))
pr_info("irq handler, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
rga_read(RGA3_INT_RAW, scheduler),
rga_read(RGA3_STATUS0, scheduler),
rga_read(RGA3_CMD_STATE, scheduler));
if (rga_read(RGA3_INT_RAW, scheduler) & m_RGA3_INT_ERROR_MASK) {
pr_err("irq handler err! INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
rga_read(RGA3_INT_RAW, scheduler),
rga_read(RGA3_STATUS0, scheduler),
rga_read(RGA3_CMD_STATE, scheduler));
scheduler->ops->soft_reset(scheduler);
return IRQ_WAKE_THREAD;
}
/*clear INTR */
rga_write(m_RGA3_INT_FRM_DONE | m_RGA3_INT_CMD_LINE_FINISH | m_RGA3_INT_ERROR_MASK,
RGA3_INT_CLR, scheduler);
return IRQ_WAKE_THREAD;
}
static int rga3_isr_thread(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
if (DEBUGGER_EN(INT_FLAG))
pr_info("isr thread, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
rga_read(RGA3_INT_RAW, scheduler),
rga_read(RGA3_STATUS0, scheduler),
rga_read(RGA3_CMD_STATE, scheduler));
return IRQ_HANDLED;
}
const struct rga_backend_ops rga3_ops = {
.get_version = rga3_get_version,
.set_reg = rga3_set_reg,
.init_reg = rga3_init_reg,
.soft_reset = rga3_soft_reset,
.read_back_reg = NULL,
.irq = rga3_irq,
.isr_thread = rga3_isr_thread,
};

142
drivers/video/rockchip/rga3/rga_drv.c
View File

@@ -26,22 +26,6 @@ struct rga_drvdata_t *rga_drvdata;
static struct hrtimer timer;
static ktime_t kt;
static const struct rga_backend_ops rga3_ops = {
.get_version = rga3_get_version,
.set_reg = rga3_set_reg,
.init_reg = rga3_init_reg,
.soft_reset = rga3_soft_reset,
.read_back_reg = NULL,
};
static const struct rga_backend_ops rga2_ops = {
.get_version = rga2_get_version,
.set_reg = rga2_set_reg,
.init_reg = rga2_init_reg,
.soft_reset = rga2_soft_reset,
.read_back_reg = rga2_read_back_reg,
};
static struct rga_session *rga_session_init(void);
static int rga_session_deinit(struct rga_session *session);
@@ -1153,91 +1137,39 @@ static int rga_release(struct inode *inode, struct file *file)
return 0;
}
static irqreturn_t rga3_irq_handler(int irq, void *data)
static irqreturn_t rga_irq_handler(int irq, void *data)
{
irqreturn_t irq_ret = IRQ_NONE;
struct rga_scheduler_t *scheduler = data;
if (DEBUGGER_EN(INT_FLAG))
pr_info("irq handler, INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n",
rga_read(RGA3_INT_RAW, scheduler),
rga_read(RGA3_STATUS0, scheduler),
rga_read(RGA3_CMD_STATE, scheduler));
if (scheduler->ops->irq)
irq_ret = scheduler->ops->irq(scheduler);
if (rga_read(RGA3_INT_RAW, scheduler) & m_RGA3_INT_ERROR_MASK) {
pr_err("irq handler err! INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n",
rga_read(RGA3_INT_RAW, scheduler),
rga_read(RGA3_STATUS0, scheduler),
rga_read(RGA3_CMD_STATE, scheduler));
scheduler->ops->soft_reset(scheduler);
return irq_ret;
}
return IRQ_WAKE_THREAD;
static irqreturn_t rga_isr_thread(int irq, void *data)
{
irqreturn_t irq_ret = IRQ_NONE;
struct rga_scheduler_t *scheduler = data;
struct rga_job *job;
job = rga_job_done(scheduler);
if (job == NULL) {
pr_err("isr thread invalid job!\n");
return IRQ_HANDLED;
}
/*clear INT */
rga_write(m_RGA3_INT_FRM_DONE | m_RGA3_INT_CMD_LINE_FINISH | m_RGA3_INT_ERROR_MASK,
RGA3_INT_CLR, scheduler);
if (scheduler->ops->isr_thread)
irq_ret = scheduler->ops->isr_thread(job, scheduler);
return IRQ_WAKE_THREAD;
}
rga_request_release_signal(scheduler, job);
static irqreturn_t rga3_irq_thread(int irq, void *data)
{
struct rga_scheduler_t *scheduler = data;
rga_job_next(scheduler);
if (DEBUGGER_EN(INT_FLAG))
pr_info("irq thread, INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n",
rga_read(RGA3_INT_RAW, scheduler),
rga_read(RGA3_STATUS0, scheduler),
rga_read(RGA3_CMD_STATE, scheduler));
rga_power_disable(scheduler);
rga_job_done(scheduler, 0);
return IRQ_HANDLED;
}
static irqreturn_t rga2_irq_handler(int irq, void *data)
{
struct rga_scheduler_t *scheduler = data;
if (DEBUGGER_EN(INT_FLAG))
pr_info("irq handler, INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n",
rga_read(RGA2_INT, scheduler),
rga_read(RGA2_STATUS2, scheduler),
rga_read(RGA2_STATUS1, scheduler));
/*if error interrupt then soft reset hardware */
//warning
if (rga_read(RGA2_INT, scheduler) & m_RGA2_INT_ERROR_FLAG_MASK) {
pr_err("irq handler err! INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n",
rga_read(RGA2_INT, scheduler),
rga_read(RGA2_STATUS2, scheduler),
rga_read(RGA2_STATUS1, scheduler));
scheduler->ops->soft_reset(scheduler);
}
/*clear INT */
rga_write(rga_read(RGA2_INT, scheduler) |
(m_RGA2_INT_ERROR_CLEAR_MASK |
m_RGA2_INT_ALL_CMD_DONE_INT_CLEAR | m_RGA2_INT_NOW_CMD_DONE_INT_CLEAR |
m_RGA2_INT_LINE_RD_CLEAR | m_RGA2_INT_LINE_WR_CLEAR),
RGA2_INT, scheduler);
return IRQ_WAKE_THREAD;
}
static irqreturn_t rga2_irq_thread(int irq, void *data)
{
struct rga_scheduler_t *scheduler = data;
if (DEBUGGER_EN(INT_FLAG))
pr_info("irq thread, INT[0x%x], HW_STATS[0x%x], CMD_STATS[0x%x]\n",
rga_read(RGA2_INT, scheduler),
rga_read(RGA2_STATUS2, scheduler),
rga_read(RGA2_STATUS1, scheduler));
rga_job_done(scheduler, 0);
return IRQ_HANDLED;
return irq_ret;
}
const struct file_operations rga_fops = {
@@ -1280,44 +1212,24 @@ static const char *const rga3_core_1_clks[] = {
"clk_rga3_1",
};
static const struct rga_irqs_data_t single_rga2_irqs[] = {
{"rga2_irq", rga2_irq_handler, rga2_irq_thread}
};
static const struct rga_irqs_data_t rga3_core0_irqs[] = {
{"rga3_core0_irq", rga3_irq_handler, rga3_irq_thread}
};
static const struct rga_irqs_data_t rga3_core1_irqs[] = {
{"rga3_core1_irq", rga3_irq_handler, rga3_irq_thread}
};
static const struct rga_match_data_t old_rga2_match_data = {
.clks = old_rga2_clks,
.num_clks = ARRAY_SIZE(old_rga2_clks),
.irqs = single_rga2_irqs,
.num_irqs = ARRAY_SIZE(single_rga2_irqs)
};
static const struct rga_match_data_t rk3588_rga2_match_data = {
.clks = rk3588_rga2_clks,
.num_clks = ARRAY_SIZE(rk3588_rga2_clks),
.irqs = single_rga2_irqs,
.num_irqs = ARRAY_SIZE(single_rga2_irqs)
};
static const struct rga_match_data_t rga3_core0_match_data = {
.clks = rga3_core_0_clks,
.num_clks = ARRAY_SIZE(rga3_core_0_clks),
.irqs = rga3_core0_irqs,
.num_irqs = ARRAY_SIZE(rga3_core0_irqs)
};
static const struct rga_match_data_t rga3_core1_match_data = {
.clks = rga3_core_1_clks,
.num_clks = ARRAY_SIZE(rga3_core_1_clks),
.irqs = rga3_core1_irqs,
.num_irqs = ARRAY_SIZE(rga3_core1_irqs)
};
static const struct of_device_id rga3_core0_dt_ids[] = {
@@ -1429,21 +1341,21 @@ static int rga_drv_probe(struct platform_device *pdev)
/* there are irq names in dts */
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(dev, "no irq %s in dts\n", match_data->irqs[0].name);
dev_err(dev, "no irq %s in dts\n", dev_driver_string(dev));
return irq;
}
scheduler->irq = irq;
pr_info("%s, irq = %d, match scheduler\n", match_data->irqs[0].name, irq);
pr_info("%s, irq = %d, match scheduler\n", dev_driver_string(dev), irq);
ret = devm_request_threaded_irq(dev, irq,
match_data->irqs[0].irq_hdl,
match_data->irqs[0].irq_thread,
rga_irq_handler,
rga_isr_thread,
IRQF_SHARED,
dev_driver_string(dev), scheduler);
if (ret < 0) {
pr_err("request irq name: %s failed: %d\n", match_data->irqs[0].name, ret);
pr_err("request irq name: %s failed: %d\n", dev_driver_string(dev), ret);
return ret;
}

39
drivers/video/rockchip/rga3/rga_job.c
View File

@@ -195,7 +195,7 @@ static int rga_job_run(struct rga_job *job, struct rga_scheduler_t *scheduler)
}
static void rga_job_next(struct rga_scheduler_t *scheduler)
void rga_job_next(struct rga_scheduler_t *scheduler)
{
int ret;
struct rga_job *job = NULL;
@@ -242,30 +242,7 @@ next_job:
rga_job_put(job);
}
static void rga_job_finish_and_next(struct rga_scheduler_t *scheduler,
struct rga_job *job, int ret)
{
ktime_t now;
job->ret = ret;
if (DEBUGGER_EN(TIME)) {
now = ktime_get();
pr_info("hw use time = %lld\n", ktime_us_delta(now, job->hw_running_time));
pr_info("(pid:%d) job done use time = %lld\n", job->pid,
ktime_us_delta(now, job->timestamp));
}
rga_mm_unmap_job_info(job);
rga_request_release_signal(scheduler, job);
rga_job_next(scheduler);
rga_power_disable(scheduler);
}
void rga_job_done(struct rga_scheduler_t *scheduler, int ret)
struct rga_job *rga_job_done(struct rga_scheduler_t *scheduler)
{
struct rga_job *job;
unsigned long flags;
@@ -278,7 +255,7 @@ void rga_job_done(struct rga_scheduler_t *scheduler, int ret)
pr_err("core[0x%x] running job has been cleanup.\n", scheduler->core);
spin_unlock_irqrestore(&scheduler->irq_lock, flags);
return;
return NULL;
}
scheduler->running_job = NULL;
@@ -292,7 +269,15 @@ void rga_job_done(struct rga_scheduler_t *scheduler, int ret)
if (DEBUGGER_EN(DUMP_IMAGE))
rga_dump_job_image(job);
rga_job_finish_and_next(scheduler, job, ret);
if (DEBUGGER_EN(TIME)) {
pr_info("hw use time = %lld\n", ktime_us_delta(now, job->hw_running_time));
pr_info("(pid:%d) job done use time = %lld\n", job->pid,
ktime_us_delta(now, job->timestamp));
}
rga_mm_unmap_job_info(job);
return job;
}
static void rga_job_scheduler_timeout_clean(struct rga_scheduler_t *scheduler)