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hdmitx: fix the zigzag problem in color depth mode

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PD#160883: hdmitx: fix the zigzag problem in color depth mode

When reset HDMITX_DWC_MC_SWRSTZREQ directly, these pulses may not align.
Therefore, the following steps must be executed.

steps
1.disable video encoder output and controller clocks
2.reset HDMITX_DWC_MC_SWRSTZREQ
3.enable video encoder output and controller clocks

Change-Id: I6cebc299d0a61da878d7c87a131d06f2601b2989
Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>
This commit is contained in:
Yi Zhou
2018-03-21 21:13:55 +08:00
parent 2482566150
commit 199636b244
1 changed files with 6 additions and 5 deletions
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11
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
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@@ -4401,6 +4401,9 @@ static void config_hdmi20_tx(enum hdmi_vic vic,
/* Reset pulse */
hdmitx_rd_check_reg(HDMITX_DWC_MC_LOCKONCLOCK, 0xff, 0x9f);
hd_write_reg(P_ENCP_VIDEO_EN, 0);
hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0xdf);
hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, 0);
mdelay(10);
@@ -4415,11 +4418,9 @@ static void config_hdmi20_tx(enum hdmi_vic vic,
hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, data32);
hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH,
hdmitx_rd_reg(HDMITX_DWC_FC_VSYNCINWIDTH));
/*reset again*/
mdelay(1);
hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, 0);
hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH,
hdmitx_rd_reg(HDMITX_DWC_FC_VSYNCINWIDTH));
hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0);
hd_write_reg(P_ENCP_VIDEO_EN, 0xff);
hdmitx_set_reg_bits(HDMITX_DWC_FC_INVIDCONF, 0, 3, 1);
mdelay(1);