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clk: rockchip: px30: leave cpll for VOP only

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We will need a pll to support all kinds of clock rate requirement
for display. In order not to affect other clocks, remove the cpll
from the parent list of other clocks and only DCLK_VOP can select
cpll as parent.

Change-Id: I69e5e3ca1af66eba5b4cc92b792077ec64f67054
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-02-27 21:44:57 +08:00
committed by Tao Huang
parent e9c977b797
commit 1a36349dcc
1 changed files with 5 additions and 5 deletions
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10
drivers/clk/rockchip/clk-px30.c
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@@ -135,14 +135,14 @@ PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" };
PNAME(mux_4plls_p) = { "gpll", "cpll", "usb480m", "npll" };
PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" };
PNAME(mux_cpll_npll_p) = { "cpll", "npll" };
PNAME(mux_npll_cpll_p) = { "npll", "cpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
PNAME(mux_gpll_npll_p) = { "gpll", "npll" };
PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
PNAME(mux_gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "cpll", "npll", "xin24m" };
PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "npll" };
PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" };
PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"};
PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
PNAME(mux_i2s0_tx_p) = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"};
@@ -161,7 +161,7 @@ PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
PNAME(mux_uart5_p) = { "clk_uart5_src", "dummy", "clk_uart5_frac" };
PNAME(mux_cif_out_p) = { "xin24m", "cpll", "npll", "usb480m" };
PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" };
PNAME(mux_dclk_vopb_p) = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
PNAME(mux_dclk_vopl_p) = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
PNAME(mux_gmac_p) = { "clk_gmac_src", "gmac_clkin" };