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lcd: update lvds,vbyone,p2p config [1/1]

Browse Source 
PD#172587

Problem:
lcd not work on real chip

Solution:
update pll, phy and channel_swap config

Verify:
skt

Change-Id: I737f7c253697ed281050ad9606cbf7d86a4b2e39
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>

Conflicts:
	MAINTAINERS
	arch/arm/boot/dts/amlogic/mesontl1_skt-panel.dtsi
This commit is contained in:
Evoke Zhang
2018-11-23 21:15:01 +08:00
committed by Dongjin Kim
parent 62a7c96841
commit 1aac63619d
20 changed files with 25562 additions and 340 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
View File

@@ -14754,6 +14754,11 @@ F: drivers/amlogic/media/common/canvas/canvas_mgr.c
F: drivers/amlogic/media/common/vfm/vfm.c
F: include/linux/amlogic/media/camera/*
AMLOGIC MESON TL1 PANEL DTS
M: Evoke Zhang <evoke.zhang@amlogic.com>
F: arch/arm/boot/dts/amlogic/mesontl1_skt-panel.dtsi
F: arch/arm/boot/dts/amlogic/mesontl1_x301-panel.dtsi
AMLOGIC multimedia
M: Pengcheng Chen <pengcheng.chen@amlogic.com>
F: drivers/amlogic/media/common/ge2d/ge2d_dmabuf.c

35
arch/arm/boot/dts/amlogic/mesontl1.dtsi
View File

@@ -2089,4 +2089,39 @@
};
};
lcd_vbyone_pins: lcd_vbyone_pin {
mux {
groups = "vx1_lockn","vx1_htpdn";
function = "vx1";
};
};
lcd_vbyone_off_pins: lcd_vbyone_off_pin {
mux {
groups = "GPIOH_15","GPIOH_16";
function = "gpio_periphs";
input-enable;
};
};
lcd_tcon_pins: lcd_tcon_pin {
mux {
groups = "tcon_0","tcon_1","tcon_2","tcon_3",
"tcon_4","tcon_5","tcon_6","tcon_7",
"tcon_8","tcon_9","tcon_10","tcon_11",
"tcon_12","tcon_13","tcon_14","tcon_15",
"tcon_lock";
function = "tcon";
};
};
lcd_tcon_off_pins: lcd_tcon_off_pin {
mux {
groups = "GPIOH_0","GPIOH_1","GPIOH_2","GPIOH_3",
"GPIOH_4","GPIOH_5","GPIOH_6","GPIOH_7",
"GPIOH_8","GPIOH_9","GPIOH_10","GPIOH_11",
"GPIOH_12","GPIOH_13","GPIOH_14","GPIOH_15",
"GPIOH_16";
function = "gpio_periphs";
input-enable;
};
};
};

92
arch/arm/boot/dts/amlogic/mesontl1_pxp-panel.dtsi
View File

@@ -1,92 +0,0 @@
/*
* arch/arm64/boot/dts/amlogic/mesontl1_pxp-panel.dtsi
*
* Copyright (C) 2016 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
/ {
lcd {
compatible = "amlogic, lcd-tl1";
status = "okay";
mode = "tv";
fr_auto_policy = <0>; /* 0=disable, 1=60/50hz, 2=60/50/48hz */
key_valid = <0>;
clocks = <&clkc CLKID_VCLK2_ENCL
&clkc CLKID_VCLK2_VENCL
&clkc CLKID_TCON
&clkc CLKID_FCLK_DIV5
&clkc CLKID_TCON_PLL_COMP>;
clock-names = "encl_top_gate",
"encl_int_gate",
"tcon_gate",
"fclk_div5",
"clk_tcon";
reg = <0xff660000 0x8100
0xff634400 0x100>;
interrupts = <0 3 1
0 78 1
0 88 1>;
interrupt-names = "vsync","vbyone","tcon";
pinctrl_version = <2>; /* for uboot */
/* power type:(0=cpu_gpio, 2=signal, 3=extern, 0xff=ending) */
/* power index:(gpios_index, or extern_index, 0xff=invalid) */
/* power value:(0=output low, 1=output high, 2=input) */
/* power delay:(unit in ms) */
lvds_0{
model_name = "1080p-vfreq";
interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
1920 1080 /*h_active, v_active*/
2200 1125 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
2060 2650 /*h_period_min,max*/
1100 1480 /*v_period_min,max*/
120000000 160000000>; /*pclk_min,max*/
lcd_timing = <
44 148 0 /*hs_width, hs_bp, hs_pol*/
5 30 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
lvds_attr = <
1 /*lvds_repack*/
1 /*dual_port*/
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<
3 0 /*vswing_level, preem_level*/
0 0>; /*clk vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 0 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
}; /* end of lcd */
}; /* end of / */

669
arch/arm/boot/dts/amlogic/mesontl1_x301-panel.dtsi Normal file
View File

@@ -0,0 +1,669 @@
/*
* arch/arm64/boot/dts/amlogic/mesontl1_x301-panel.dtsi
*
* Copyright (C) 2016 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
/ {
lcd {
compatible = "amlogic, lcd-tl1";
status = "okay";
mode = "tv";
fr_auto_policy = <0>; /* 0=disable, 1=60/50hz, 2=60/50/48hz */
key_valid = <0>;
clocks = <&clkc CLKID_VCLK2_ENCL
&clkc CLKID_VCLK2_VENCL
&clkc CLKID_TCON
&clkc CLKID_FCLK_DIV5
&clkc CLKID_TCON_PLL_COMP>;
clock-names = "encl_top_gate",
"encl_int_gate",
"tcon_gate",
"fclk_div5",
"clk_tcon";
reg = <0xff660000 0x8100
0xff634400 0x300>;
interrupts = <0 3 1
0 78 1
0 88 1>;
interrupt-names = "vsync","vbyone","tcon";
pinctrl-names = "vbyone","vbyone_off","tcon","tcon_off";
pinctrl-0 = <&lcd_vbyone_pins>;
pinctrl-1 = <&lcd_vbyone_off_pins>;
pinctrl-2 = <&lcd_tcon_pins>;
pinctrl-3 = <&lcd_tcon_off_pins>;
pinctrl_version = <2>; /* for uboot */
/* power type:(0=cpu_gpio, 2=signal, 3=extern, 0xff=ending) */
/* power index:(gpios_index, or extern_index, 0xff=invalid) */
/* power value:(0=output low, 1=output high, 2=input) */
/* power delay:(unit in ms) */
lcd_cpu-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH
&gpio GPIOH_2 GPIO_ACTIVE_HIGH
&gpio GPIOH_3 GPIO_ACTIVE_HIGH
&gpio GPIOH_12 GPIO_ACTIVE_HIGH
&gpio GPIOH_8 GPIO_ACTIVE_HIGH
&gpio GPIOH_10 GPIO_ACTIVE_HIGH
&gpio GPIOH_11 GPIO_ACTIVE_HIGH
&gpio GPIOH_14 GPIO_ACTIVE_HIGH>;
lcd_cpu_gpio_names = "GPIOAO_4","GPIOH_2","GPIOH_3","GPIOH_12",
"GPIOH_8","GPIOH_10","GPIOH_11","GPIOH_14";
lvds_0{
model_name = "1080p-vfreq";
interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
1920 1080 /*h_active, v_active*/
2200 1125 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
2060 2650 /*h_period_min,max*/
1100 1480 /*v_period_min,max*/
120000000 160000000>; /*pclk_min,max*/
lcd_timing = <
44 148 0 /*hs_width, hs_bp, hs_pol*/
5 30 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
lvds_attr = <
1 /*lvds_repack*/
1 /*dual_port*/
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<
3 0 /*vswing_level, preem_level*/
0 0>; /*clk vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
0 0 1 20 /*panel power on*/
2 0 0 0 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0 0 0 100 /*panel power off*/
0xff 0 0 0>; /*ending*/
backlight_index = <0>;
};
lvds_1{
model_name = "1080p-hfreq_hdmi";
interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
1920 1080 /*h_active, v_active*/
2200 1125 /*h_period, v_period*/
8 /*lcd_bits*/
16 9>; /*screen_widht, screen_height*/
range_setting = <
2080 2720 /*h_period min, max*/
1100 1380 /*v_period min, max*/
133940000 156000000>; /*pclk_min, max*/
lcd_timing = <
44 148 0 /*hs_width, hs_bp, hs_pol*/
5 30 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
4 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level */
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
lvds_attr = <
1 /*lvds_repack*/
1 /*dual_port*/
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<
3 0 /*vswing_level, preem_level*/
0 0>; /*clk vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
0 0 1 20 /*panel power on*/
2 0 0 0 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0 0 0 100 /*panel power off*/
0xff 0 0 0>; /*ending*/
backlight_index = <0>;
};
lvds_2{
model_name = "768p-vfreq";
interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
1366 768 /*h_active, v_active*/
1560 806 /*h_period, v_period*/
8 /*lcd_bits*/
16 9>; /*screen_widht, screen_height*/
range_setting = <
1460 2000 /*h_period_min, max */
784 1015 /*v_period_min, max */
50000000 85000000>; /*pclk_min, max*/
lcd_timing = <
56 64 0 /*hs_width, hs_bp, hs_pol*/
3 28 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
lvds_attr = <
1 /*lvds_repack*/
0 /*dual_port*/
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<
3 0 /*vswing_level, preem_level*/
0 0>; /*clk vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
0 0 1 20 /*panel power on*/
2 0 0 0 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0 0 0 100 /*panel power off*/
0xff 0 0 0>; /*ending*/
backlight_index = <0>;
};
vbyone_0{
model_name = "public_2region";
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
10 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 4800 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
33 477 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
vbyone_attr = <
8 /*lane_count*/
2 /*region_num*/
4 /*byte_mode*/
4>; /*color_fmt*/
vbyone_intr_enable = <
1 /*vbyone_intr_enable */
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<3 0>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <0 0 1 50 /*panel power on*/
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <2 0 0 10 /*signal disable*/
0 0 0 200 /*panel power off*/
0xff 0 0 0>; /*ending*/
backlight_index = <2>;
};
vbyone_1{
model_name = "public_1region";
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
10 /*lcd_bits*/
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 4800 /*h_period_min, max*/
2200 2790 /*v_period_min, max*/
552000000 632000000>; /*pclk_min,max*/
lcd_timing = <
33 477 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
vbyone_attr = <
8 /*lane_count*/
1 /*region_num*/
4 /*byte_mode*/
4>; /*color_fmt*/
vbyone_intr_enable = <
1 /*vbyone_intr_enable*/
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<3 0>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
0 0 1 50 /*panel power on*/
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0 0 0 200 /*panel power off*/
0xff 0 0 0>; /*ending*/
backlight_index = <2>;
};
vbyone_2{
model_name = "public_2region_hdmi";
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
10 /*lcd_bits*/
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 4800 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*v_period_min, max*/
lcd_timing = <
33 477 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
4 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
vbyone_attr = <
8 /*lane_count*/
2 /*region_num*/
4 /*byte_mode*/
4>; /*color_fmt*/
vbyone_intr_enable = <
1 /*vbyone_intr_enable*/
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<3 0>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
0 0 1 50 /*panel power on*/
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0 0 0 200 /*panel power off*/
0xff 0 0 0>; /*ending*/
backlight_index = <2>;
};
vbyone_3{
model_name = "BOE_HV550QU2";
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
10 /*lcd_bits*/
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 4800 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
560000000 624000000>; /*pclk_min, max*/
lcd_timing = <
33 477 1 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
vbyone_attr = <
8 /*lane_count*/
2 /*region_num*/
4 /*byte_mode*/
4>; /*color_fmt*/
vbyone_intr_enable = <
1 /*vbyone_intr_enable*/
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<3 0>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
0 0 1 20 /*panel power on*/
0 3 0 10 /*3d_disable*/
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0 3 2 0 /*3d_disable*/
0 0 0 100 /*panel power off*/
0xff 0 0 0>; /*ending*/
backlight_index = <2>;
};
vbyone_4{
model_name = "BOE_HV550QU2_1region";
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
10 /*lcd_bits*/
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 4800 /*h_period_min,max*/
2200 2760 /*v_period_min,max*/
560000000 624000000>; /*pclk_min, max*/
lcd_timing = <
33 477 1 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
1 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
vbyone_attr = <
8 /*lane_count*/
1 /*region_num*/
4 /*byte_mode*/
4>; /*color_fmt*/
vbyone_intr_enable = <
1 /*vbyone_intr_enable*/
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<3 0>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
0 0 1 20 /*panel power on*/
0 3 0 10 /*3d_disable*/
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0 3 2 0 /*3d_disable*/
0 0 0 100 /*panel power off*/
0xff 0 0 0>; /*ending*/
backlight_index = <2>;
};
p2p{
model_name = "p2p_ceds";
interface = "p2p"; /*lcd_interface
*(lvds, vbyone, mlvds, p2p)
*/
basic_setting = <
3840 2160 /*h_active, v_active*/
5000 2250 /*h_period, v_period*/
10 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 5100 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
16 29 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
p2p_attr = <
1 /*lvds_repack*/
1 /*dual_port*/
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<
3 0 /*vswing_level, preem_level*/>;
/* power step: type, index, value, delay(ms) */
power_on_step = <
0 0 1 20 /*panel power on*/
3 2 0 200 /* extern init voltage */
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0 0 0 100 /*panel power off*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
};
lcd_extern{
compatible = "amlogic, lcd_extern";
status = "okay";
key_valid = <0>;
i2c_bus = "i2c_bus_1";
extern_0{
index = <0>;
extern_name = "ext_default";
status = "disabled";
type = <0>; /*0=i2c, 1=spi, 2=mipi*/
i2c_address = <0x1c>; /*7bit i2c_addr*/
i2c_address2 = <0xff>;
cmd_size = <0xff>; /*dynamic cmd_size*/
/* init on/off:
* fixed cmd_size: (type, value...);
* cmd_size include all data.
* dynamic cmd_size: (type, cmd_size, value...);
* cmd_size include value.
*/
/* type: 0x00=cmd with delay(bit[3:0]=1 for address2),
* 0xc0=cmd(bit[3:0]=1 for address2),
* 0xf0=gpio,
* 0xfd=delay,
* 0xff=ending
*/
/* value: i2c or spi cmd, or gpio index & level */
/* delay: unit ms */
init_on = <
0xc0 7 0x20 0x01 0x02 0x00 0x40 0xFF 0x00
0xc0 7 0x80 0x02 0x00 0x40 0x62 0x51 0x73
0xc0 7 0x61 0x06 0x00 0x00 0x00 0x00 0x00
0xc0 7 0xC1 0x05 0x0F 0x00 0x08 0x70 0x00
0xc0 7 0x13 0x01 0x00 0x00 0x00 0x00 0x00
0xc0 7 0x3D 0x02 0x01 0x00 0x00 0x00 0x00
0xc0 7 0xED 0x0D 0x01 0x00 0x00 0x00 0x00
0xc0 7 0x23 0x02 0x00 0x00 0x00 0x00 0x00
0xfd 1 10 /* delay 10ms */
0xff 0>; /*ending*/
init_off = <0xff 0>; /*ending*/
};
extern_1{
index = <1>;
extern_name = "i2c_T5800Q";
status = "disabled";
type = <0>; /* 0=i2c, 1=spi, 2=mipi */
i2c_address = <0x1c>; /* 7bit i2c address */
};
extern_2{
index = <2>;
extern_name = "i2c_ANX6862_7911";
status = "okay";
type = <0>; /* 0=i2c, 1=spi, 2=mipi */
i2c_address = <0x20>; /* 7bit i2c address */
i2c_address2 = <0x74>; /* 7bit i2c address */
cmd_size = <0xff>;
init_on = <
0xc0 2 0x01 0x2b
0xc0 2 0x02 0x05
0xc0 2 0x03 0x00
0xc0 2 0x04 0x00
0xc0 2 0x05 0x0c
0xc0 2 0x06 0x04
0xc0 2 0x07 0x21
0xc0 2 0x08 0x0f
0xc0 2 0x09 0x04
0xc0 2 0x0a 0x00
0xc0 2 0x0b 0x04
0xc0 2 0xff 0x00
0xfd 1 100 /* delay 100ms */
0xc1 2 0x01 0xca
0xc1 2 0x02 0x3b
0xc1 2 0x03 0x33
0xc1 2 0x04 0x05
0xc1 2 0x05 0x2c
0xc1 2 0x06 0xf2
0xc1 2 0x07 0x9c
0xc1 2 0x08 0x1b
0xc1 2 0x09 0x82
0xc1 2 0x0a 0x3d
0xc1 2 0x0b 0x20
0xc1 2 0x0c 0x11
0xc1 2 0x0d 0xc4
0xc1 2 0x0e 0x1a
0xc1 2 0x0f 0x31
0xc1 2 0x10 0x4c
0xc1 2 0x11 0x12
0xc1 2 0x12 0x90
0xc1 2 0x13 0xf7
0xc1 2 0x14 0x0c
0xc1 2 0x15 0x20
0xc1 2 0x16 0x13
0xff 0>; /*ending*/
init_off = <0xff 0>; /*ending*/
};
};
backlight{
compatible = "amlogic, backlight-tl1";
status = "okay";
key_valid = <0>;
pinctrl-names = "pwm_on","pwm_vs_on",
"pwm_combo_0_1_on",
"pwm_combo_0_vs_1_on",
"pwm_combo_0_1_vs_on",
"pwm_off",
"pwm_combo_off";
pinctrl-0 = <&pwm_c_pins3>;
pinctrl-1 = <&bl_pwm_vs_on_pins>;
pinctrl-2 = <&pwm_c_pins3 &pwm_d_pins2>;
pinctrl-3 = <&bl_pwm_combo_0_vs_on_pins &pwm_d_pins2>;
pinctrl-4 = <&pwm_c_pins3 &bl_pwm_combo_1_vs_on_pins>;
pinctrl-5 = <&bl_pwm_off_pins>;
pinctrl-6 = <&bl_pwm_combo_off_pins>;
pinctrl_version = <2>; /* for uboot */
interrupts = <0 3 1>;
interrupt-names = "ldim_vsync";
bl_pwm_config = <&bl_pwm_conf>;
/* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
/* power index:(point gpios_index, 0xff=invalid) */
/* power value:(0=output low, 1=output high, 2=input) */
/* power delay:(unit in ms) */
bl-gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH
&gpio GPIOZ_5 GPIO_ACTIVE_HIGH
&gpio GPIOZ_6 GPIO_ACTIVE_HIGH>;
bl_gpio_names = "GPIOAO_11","GPIOZ_5","GPIOZ_6";
backlight_0{
index = <0>;
bl_name = "backlight_pwm";
bl_level_default_uboot_kernel = <100 100>;
bl_level_attr = <255 10 /*max, min*/
128 128>; /*mid, mid_mapping*/
bl_ctrl_method = <1>; /*1=pwm,2=pwm_combo,3=ldim*/
bl_power_attr = <0 /*en_gpio_index*/
1 0 /*on_value, off_value*/
200 200>; /*on_delay(ms), off_delay(ms)*/
bl_pwm_port = "PWM_C";
bl_pwm_attr = <1 /*pwm_method(0=negative, 1=positvie)*/
180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
100 25>; /*duty_max(%), duty_min(%)*/
bl_pwm_power = <1 0 /*pwm_gpio_index, pwm_gpio_off*/
10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
};
backlight_1{
index = <1>;
bl_name = "backlight_pwm_vs";
bl_level_default_uboot_kernel = <100 100>;
bl_level_attr = <255 10 /*max, min*/
128 128>; /*mid, mid_mapping*/
bl_ctrl_method = <1>; /*1=pwm,2=pwm_combo,3=ldim*/
bl_power_attr = <0 /*en_gpio_index*/
1 0 /*on_value, off_value*/
200 200>; /* on_delay(ms), off_delay(ms)*/
bl_pwm_port = "PWM_VS";
bl_pwm_attr = <1 /*pwm_method(0=negative, 1=positvie)*/
2 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
100 25>; /*duty_max(%), duty_min(%)*/
bl_pwm_power = <1 0 /*pwm_gpio_index, pwm_gpio_off*/
10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
};
backlight_2{
index = <2>;
bl_name = "backlight_pwm_combo";
bl_level_default_uboot_kernel = <31 100>;
bl_level_attr = <255 10 /*max, min*/
128 128>; /*mid, mid_mapping*/
bl_ctrl_method = <2>; /*1=pwm,2=pwm_combo,3=ldim*/
bl_power_attr = <0 /*en_gpio_index*/
1 0 /*on_value, off_value*/
410 110>; /*on_delay(ms), off_delay(ms)*/
bl_pwm_combo_level_mapping = <255 10 /*pwm_0 range*/
0 0>; /*pwm_1 range*/
bl_pwm_combo_port = "PWM_B","PWM_C";
bl_pwm_combo_attr = <1 /*pwm0 method*/
180 /*pwm0 freq(pwm:Hz, pwm_vs:multiple of vs)*/
100 25 /*pwm0 duty_max(%), duty_min(%)*/
1 /*pwm1 method*/
18000 /*pwm1 freq(pwm:Hz, pwm_vs:multi of vs)*/
80 80>; /*pwm1 duty_max(%), duty_min(%)*/
bl_pwm_combo_power = <1 0 /*pwm0 gpio_index, gpio_off*/
2 0 /*pwm1 gpio_index, gpio_off*/
10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
};
};
bl_pwm_conf:bl_pwm_conf{
pwm_channel_0 {
pwm_port_index = <2>;
pwms = <&pwm_cd MESON_PWM_0 30040 0>;
};
pwm_channel_1 {
pwm_port_index = <3>;
pwms = <&pwm_cd MESON_PWM_1 30040 0>;
};
};
}; /* end of / */

36
arch/arm/boot/dts/amlogic/tl1_t962x2_skt.dts
View File

@@ -449,7 +449,7 @@
compatible = "amlogic, unifykey";
status = "okay";
unifykey-num = <19>;
unifykey-num = <20>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
@@ -469,6 +469,7 @@
unifykey-index-16 = <&keysn_16>;
unifykey-index-17 = <&keysn_17>;
unifykey-index-18 = <&keysn_18>;
unifykey-index-19 = <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
@@ -570,6 +571,11 @@
key-device = "normal";
key-permit = "read","write","del";
};
keysn_19:key_19{
key-name = "lcd_tcon";
key-device = "normal";
key-permit = "read","write","del";
};
}; /* End unifykey */
hdmirx {
@@ -1461,6 +1467,34 @@
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <300000>;
pinctrl-names="default";
pinctrl-0=<&i2c1_h_pins>;
lcd_extern_i2c0: lcd_extern_i2c@0 {
compatible = "lcd_ext, i2c";
dev_name = "i2c_T5800Q";
reg = <0x1c>;
status = "okay";
};
lcd_extern_i2c1: lcd_extern_i2c@1 {
compatible = "lcd_ext, i2c";
dev_name = "i2c_ANX6862";
reg = <0x20>;
status = "okay";
};
lcd_extern_i2c2: lcd_extern_i2c@2 {
compatible = "lcd_ext, i2c";
dev_name = "i2c_ANX7911";
reg = <0x74>;
status = "okay";
};
};
&pwm_ab {
status = "okay";
};

72
arch/arm/boot/dts/amlogic/tl1_t962x2_x301.dts
View File

@@ -19,7 +19,7 @@
#include "mesontl1.dtsi"
#include "partition_mbox_normal_P_32.dtsi"
#include "mesontl1_skt-panel.dtsi"
#include "mesontl1_x301-panel.dtsi"
/ {
model = "Amlogic TL1 T962X2 X301";
@@ -451,7 +451,7 @@
compatible = "amlogic, unifykey";
status = "okay";
unifykey-num = <19>;
unifykey-num = <20>;
unifykey-index-0 = <&keysn_0>;
unifykey-index-1 = <&keysn_1>;
unifykey-index-2 = <&keysn_2>;
@@ -471,6 +471,7 @@
unifykey-index-16 = <&keysn_16>;
unifykey-index-17 = <&keysn_17>;
unifykey-index-18 = <&keysn_18>;
unifykey-index-19 = <&keysn_19>;
keysn_0: key_0{
key-name = "usid";
@@ -572,6 +573,11 @@
key-device = "normal";
key-permit = "read","write","del";
};
keysn_19:key_19{
key-name = "lcd_tcon";
key-device = "normal";
key-permit = "read","write","del";
};
}; /* End unifykey */
hdmirx {
@@ -1252,6 +1258,40 @@
};
};
/*backlight*/
bl_pwm_vs_on_pins:bl_pwm_vs_on_pin {
mux {
groups = "pwm_vs_z5";
function = "pwm_vs";
};
};
bl_pwm_off_pins:bl_pwm_off_pin {
mux {
groups = "GPIOZ_5";
function = "gpio_periphs";
output-low;
};
};
bl_pwm_combo_0_vs_on_pins:bl_pwm_combo_0_vs_on_pin {
mux {
groups = "pwm_vs_z5";
function = "pwm_vs";
};
};
bl_pwm_combo_1_vs_on_pins:bl_pwm_combo_1_vs_on_pin {
mux {
groups = "pwm_vs_z6";
function = "pwm_vs";
};
};
bl_pwm_combo_off_pins:bl_pwm_combo_off_pin {
mux {
groups = "GPIOZ_5",
"GPIOZ_6";
function = "gpio_periphs";
output-low;
};
};
}; /* end of pinctrl_periphs */
@@ -1445,6 +1485,34 @@
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <300000>;
pinctrl-names="default";
pinctrl-0=<&i2c1_h_pins>;
lcd_extern_i2c0: lcd_extern_i2c@0 {
compatible = "lcd_ext, i2c";
dev_name = "i2c_T5800Q";
reg = <0x1c>;
status = "okay";
};
lcd_extern_i2c1: lcd_extern_i2c@1 {
compatible = "lcd_ext, i2c";
dev_name = "i2c_ANX6862";
reg = <0x20>;
status = "okay";
};
lcd_extern_i2c2: lcd_extern_i2c@2 {
compatible = "lcd_ext, i2c";
dev_name = "i2c_ANX7911";
reg = <0x74>;
status = "okay";
};
};
&pwm_ab {
status = "okay";
};

5
drivers/amlogic/media/vout/backlight/aml_bl.c
View File

@@ -3539,7 +3539,7 @@ static int aml_bl_probe(struct platform_device *pdev)
err:
kfree(bl_drv);
bl_drv = NULL;
return ret;
return 0;
}
static int __exit aml_bl_remove(struct platform_device *pdev)
@@ -3547,6 +3547,9 @@ static int __exit aml_bl_remove(struct platform_device *pdev)
int ret;
/*struct aml_bl *bl_drv = platform_get_drvdata(pdev);*/
if (bl_drv == NULL)
return 0;
aml_bl_remove_class();
ret = cancel_delayed_work_sync(&bl_drv->bl_delayed_work);

304
drivers/amlogic/media/vout/lcd/lcd_clk_config.c
View File

@@ -483,6 +483,7 @@ static void lcd_set_pll_ss_tl1(unsigned int ss_level)
static void lcd_set_pll_tl1(struct lcd_clk_config_s *cConf)
{
#if 0
unsigned int pll_ctrl, pll_ctrl1;
int ret;
@@ -509,7 +510,85 @@ static void lcd_set_pll_tl1(struct lcd_clk_config_s *cConf)
lcd_hiu_setb(HHI_TCON_PLL_CNTL0, 0, LCD_PLL_RST_TL1, 1);
lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00003008);
lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x0b8300c0);
#else
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
int ret;
switch (lcd_drv->lcd_config->lcd_basic.lcd_type) {
case LCD_LVDS:
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x200704ad);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x300704ad);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL1, 0x10508000);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00001108);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL3, 0x10058f30);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x010100c0);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x038300c0);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x340704ad);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x142e04ad);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00003008);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x0b8300c0);
mdelay(10);
break;
case LCD_VBYONE:
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x200f04f7);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x300f04f7);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL1, 0x10110000);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00001108);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL3, 0x10051400);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x010100c0);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x038300c0);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x340f04f7);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x140f04f7);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00003008);
mdelay(10);
break;
case LCD_P2P:
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x200604e1);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x300604e1);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL1, 0x10208000);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00001108);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL3, 0x10058f30);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x010100c0);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x038300c0);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x340604e1);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL0, 0x14af04e1);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00003008);
mdelay(10);
lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x0b8300c0);
mdelay(10);
break;
default:
break;
}
#endif
ret = lcd_pll_wait_lock(HHI_TCON_PLL_CNTL0, LCD_PLL_LOCK_TL1);
if (ret)
LCDERR("hpll lock failed\n");
@@ -554,7 +633,7 @@ static void lcd_set_vid_pll_div(struct lcd_clk_config_s *cConf)
lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 1, 15, 1);
lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, shift_val, 0, 15);
lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
/* Enable the final output clock */
@@ -604,34 +683,17 @@ static void lcd_set_dsi_phy_clk(int sel)
static void lcd_set_tcon_clk(struct lcd_config_s *pconf)
{
#if 0
unsigned int val;
if (lcd_debug_print_flag == 2)
LCDPR("%s\n", __func__);
switch (pconf->lcd_basic.lcd_type) {
case LCD_LVDS:
lcd_hiu_write(HHI_DIF_TCON_CNTL0, 0x0);
lcd_hiu_write(HHI_DIF_TCON_CNTL0, 0x80000000);
lcd_hiu_write(HHI_DIF_TCON_CNTL1, 0x0);
lcd_hiu_write(HHI_DIF_TCON_CNTL2, 0x0);
break;
case LCD_MLVDS:
val = pconf->lcd_control.mlvds_config->pi_clk_sel;
/*val = (~val) & 0x3ff;*/
lcd_hiu_write(HHI_DIF_TCON_CNTL0, (val << 12));
lcd_hiu_write(HHI_DIF_TCON_CNTL0, ((1 << 31) | (val << 12)));
val = pconf->lcd_control.mlvds_config->clk_phase & 0xfff;
lcd_hiu_write(HHI_DIF_TCON_CNTL1, val);
lcd_hiu_write(HHI_DIF_TCON_CNTL2, 0x0);
case LCD_P2P:
/* tcon_clk 50M */
/*lcd_hiu_write(HHI_TCON_CLK_CNTL,
* (1 << 7) | (1 << 6) | (7 << 0));
*/
if (!IS_ERR(lcd_clktree.tcon_clk)) {
if (!IS_ERR_OR_NULL(lcd_clktree.tcon_clk)) {
clk_set_rate(lcd_clktree.tcon_clk, 50000000);
clk_prepare_enable(lcd_clktree.tcon_clk);
}
@@ -639,7 +701,6 @@ static void lcd_set_tcon_clk(struct lcd_config_s *pconf)
default:
break;
}
#endif
}
/* ****************************************************
@@ -1088,6 +1149,32 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf)
}
}
break;
case LCD_P2P:
clk_div_sel = CLK_DIV_SEL_1;
xd = 1;
clk_div_out = cConf->fout * xd;
if (clk_div_out > cConf->data->div_out_fmax)
goto generate_clk_done_txl;
if (lcd_debug_print_flag == 2) {
LCDPR("fout=%d, xd=%d, clk_div_out=%d\n",
cConf->fout, xd, clk_div_out);
}
clk_div_in = clk_vid_pll_div_calc(clk_div_out,
clk_div_sel, CLK_DIV_O2I);
if (clk_div_in > cConf->data->div_in_fmax)
goto generate_clk_done_txl;
cConf->xd = xd;
cConf->div_sel = clk_div_sel;
pll_fout = clk_div_in;
if (lcd_debug_print_flag == 2) {
LCDPR("clk_div_sel=%s(index %d), pll_fout=%d\n",
lcd_clk_div_sel_table[clk_div_sel],
clk_div_sel, pll_fout);
}
done = check_pll_txl(cConf, pll_fout);
if (done)
goto generate_clk_done_txl;
break;
default:
break;
}
@@ -1525,20 +1612,20 @@ static void lcd_clk_set_tl1(struct lcd_config_s *pconf)
static void lcd_clk_gate_switch_dft(struct aml_lcd_drv_s *lcd_drv, int status)
{
if (status) {
if (IS_ERR(lcd_clktree.encl_top_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
LCDERR("%s: encl_top_gate\n", __func__);
else
clk_prepare_enable(lcd_clktree.encl_top_gate);
if (IS_ERR(lcd_clktree.encl_int_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
LCDERR("%s: encl_int_gata\n", __func__);
else
clk_prepare_enable(lcd_clktree.encl_int_gate);
} else {
if (IS_ERR(lcd_clktree.encl_int_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
LCDERR("%s: encl_int_gata\n", __func__);
else
clk_disable_unprepare(lcd_clktree.encl_int_gate);
if (IS_ERR(lcd_clktree.encl_top_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
LCDERR("%s: encl_top_gata\n", __func__);
else
clk_disable_unprepare(lcd_clktree.encl_top_gate);
@@ -1548,44 +1635,44 @@ static void lcd_clk_gate_switch_dft(struct aml_lcd_drv_s *lcd_drv, int status)
static void lcd_clk_gate_switch_axg(struct aml_lcd_drv_s *lcd_drv, int status)
{
if (status) {
if (IS_ERR(lcd_clktree.dsi_host_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_host_gate))
LCDERR("%s: dsi_host_gate\n", __func__);
else
clk_prepare_enable(lcd_clktree.dsi_host_gate);
if (IS_ERR(lcd_clktree.dsi_phy_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_phy_gate))
LCDERR("%s: dsi_phy_gate\n", __func__);
else
clk_prepare_enable(lcd_clktree.dsi_phy_gate);
if (IS_ERR(lcd_clktree.dsi_meas))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_meas))
LCDERR("%s: dsi_meas\n", __func__);
else
clk_prepare_enable(lcd_clktree.dsi_meas);
if (IS_ERR(lcd_clktree.mipi_enable_gate))
if (IS_ERR_OR_NULL(lcd_clktree.mipi_enable_gate))
LCDERR("%s: mipi_enable_gate\n", __func__);
else
clk_prepare_enable(lcd_clktree.mipi_enable_gate);
if (IS_ERR(lcd_clktree.mipi_bandgap_gate))
if (IS_ERR_OR_NULL(lcd_clktree.mipi_bandgap_gate))
LCDERR("%s: mipi_bandgap_gate\n", __func__);
else
clk_prepare_enable(lcd_clktree.mipi_bandgap_gate);
} else {
if (IS_ERR(lcd_clktree.dsi_host_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_host_gate))
LCDERR("%s: dsi_host_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.dsi_host_gate);
if (IS_ERR(lcd_clktree.dsi_phy_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_phy_gate))
LCDERR("%s: dsi_phy_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.dsi_phy_gate);
if (IS_ERR(lcd_clktree.dsi_meas))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_meas))
LCDERR("%s: dsi_meas\n", __func__);
else
clk_disable_unprepare(lcd_clktree.dsi_meas);
if (IS_ERR(lcd_clktree.mipi_enable_gate))
if (IS_ERR_OR_NULL(lcd_clktree.mipi_enable_gate))
LCDERR("%s: mipi_enable_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.mipi_enable_gate);
if (IS_ERR(lcd_clktree.mipi_bandgap_gate))
if (IS_ERR_OR_NULL(lcd_clktree.mipi_bandgap_gate))
LCDERR("%s: mipi_bandgap_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.mipi_bandgap_gate);
@@ -1596,56 +1683,56 @@ static void lcd_clk_gate_switch_g12a(struct aml_lcd_drv_s *lcd_drv, int status)
{
if (status) {
if (clk_conf.data->vclk_sel) {
if (IS_ERR(lcd_clktree.gp0_pll))
if (IS_ERR_OR_NULL(lcd_clktree.gp0_pll))
LCDERR("%s: gp0_pll\n", __func__);
else
clk_prepare_enable(lcd_clktree.gp0_pll);
}
if (IS_ERR(lcd_clktree.dsi_host_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_host_gate))
LCDERR("%s: dsi_host_gate\n", __func__);
else
clk_prepare_enable(lcd_clktree.dsi_host_gate);
if (IS_ERR(lcd_clktree.dsi_phy_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_phy_gate))
LCDERR("%s: dsi_phy_gate\n", __func__);
else
clk_prepare_enable(lcd_clktree.dsi_phy_gate);
if (IS_ERR(lcd_clktree.dsi_meas))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_meas))
LCDERR("%s: dsi_meas\n", __func__);
else
clk_prepare_enable(lcd_clktree.dsi_meas);
if (IS_ERR(lcd_clktree.encl_top_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
LCDERR("%s: encl_top_gate\n", __func__);
else
clk_prepare_enable(lcd_clktree.encl_top_gate);
if (IS_ERR(lcd_clktree.encl_int_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
LCDERR("%s: encl_int_gata\n", __func__);
else
clk_prepare_enable(lcd_clktree.encl_int_gate);
} else {
if (IS_ERR(lcd_clktree.dsi_host_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_host_gate))
LCDERR("%s: dsi_host_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.dsi_host_gate);
if (IS_ERR(lcd_clktree.dsi_phy_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_phy_gate))
LCDERR("%s: dsi_phy_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.dsi_phy_gate);
if (IS_ERR(lcd_clktree.dsi_meas))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_meas))
LCDERR("%s: dsi_meas\n", __func__);
else
clk_disable_unprepare(lcd_clktree.dsi_meas);
if (IS_ERR(lcd_clktree.encl_int_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
LCDERR("%s: encl_int_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.encl_int_gate);
if (IS_ERR(lcd_clktree.encl_top_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
LCDERR("%s: encl_top_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.encl_top_gate);
if (clk_conf.data->vclk_sel) {
if (IS_ERR(lcd_clktree.gp0_pll))
if (IS_ERR_OR_NULL(lcd_clktree.gp0_pll))
LCDERR("%s: gp0_pll\n", __func__);
else
clk_disable_unprepare(lcd_clktree.gp0_pll);
@@ -1656,22 +1743,22 @@ static void lcd_clk_gate_switch_g12a(struct aml_lcd_drv_s *lcd_drv, int status)
static void lcd_clk_gate_switch_tl1(struct aml_lcd_drv_s *lcd_drv, int status)
{
if (status) {
if (IS_ERR(lcd_clktree.encl_top_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
LCDERR("%s: encl_top_gate\n", __func__);
else
clk_prepare_enable(lcd_clktree.encl_top_gate);
if (IS_ERR(lcd_clktree.encl_int_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
LCDERR("%s: encl_int_gata\n", __func__);
else
clk_prepare_enable(lcd_clktree.encl_int_gate);
switch (lcd_drv->lcd_config->lcd_basic.lcd_type) {
case LCD_MLVDS:
case LCD_P2P:
if (IS_ERR(lcd_clktree.tcon_gate))
if (IS_ERR_OR_NULL(lcd_clktree.tcon_gate))
LCDERR("%s: tcon_gate\n", __func__);
else
clk_prepare_enable(lcd_clktree.tcon_gate);
if (IS_ERR(lcd_clktree.tcon_clk))
if (IS_ERR_OR_NULL(lcd_clktree.tcon_clk))
LCDERR("%s: tcon_clk\n", __func__);
else
clk_prepare_enable(lcd_clktree.tcon_clk);
@@ -1683,11 +1770,11 @@ static void lcd_clk_gate_switch_tl1(struct aml_lcd_drv_s *lcd_drv, int status)
switch (lcd_drv->lcd_config->lcd_basic.lcd_type) {
case LCD_MLVDS:
case LCD_P2P:
if (IS_ERR(lcd_clktree.tcon_clk))
if (IS_ERR_OR_NULL(lcd_clktree.tcon_clk))
LCDERR("%s: tcon_clk\n", __func__);
else
clk_disable_unprepare(lcd_clktree.tcon_clk);
if (IS_ERR(lcd_clktree.tcon_gate))
if (IS_ERR_OR_NULL(lcd_clktree.tcon_gate))
LCDERR("%s: tcon_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.tcon_gate);
@@ -1695,11 +1782,11 @@ static void lcd_clk_gate_switch_tl1(struct aml_lcd_drv_s *lcd_drv, int status)
default:
break;
}
if (IS_ERR(lcd_clktree.encl_int_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
LCDERR("%s: encl_int_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.encl_int_gate);
if (IS_ERR(lcd_clktree.encl_top_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
LCDERR("%s: encl_top_gate\n", __func__);
else
clk_disable_unprepare(lcd_clktree.encl_top_gate);
@@ -1713,11 +1800,11 @@ static void lcd_clktree_probe_dft(void)
lcd_clktree.clk_gate_state = 0;
lcd_clktree.encl_top_gate = devm_clk_get(lcd_drv->dev, "encl_top_gate");
if (IS_ERR(lcd_clktree.encl_top_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
LCDERR("%s: get encl_top_gate error\n", __func__);
lcd_clktree.encl_int_gate = devm_clk_get(lcd_drv->dev, "encl_int_gate");
if (IS_ERR(lcd_clktree.encl_int_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
LCDERR("%s: get encl_int_gate error\n", __func__);
LCDPR("lcd_clktree_probe\n");
@@ -1730,25 +1817,25 @@ static void lcd_clktree_probe_axg(void)
lcd_clktree.clk_gate_state = 0;
lcd_clktree.dsi_host_gate = devm_clk_get(lcd_drv->dev, "dsi_host_gate");
if (IS_ERR(lcd_clktree.dsi_host_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_host_gate))
LCDERR("%s: clk dsi_host_gate\n", __func__);
lcd_clktree.dsi_phy_gate = devm_clk_get(lcd_drv->dev, "dsi_phy_gate");
if (IS_ERR(lcd_clktree.dsi_phy_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_phy_gate))
LCDERR("%s: clk dsi_phy_gate\n", __func__);
lcd_clktree.dsi_meas = devm_clk_get(lcd_drv->dev, "dsi_meas");
if (IS_ERR(lcd_clktree.dsi_meas))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_meas))
LCDERR("%s: clk dsi_meas\n", __func__);
lcd_clktree.mipi_enable_gate = devm_clk_get(lcd_drv->dev,
"mipi_enable_gate");
if (IS_ERR(lcd_clktree.mipi_enable_gate))
if (IS_ERR_OR_NULL(lcd_clktree.mipi_enable_gate))
LCDERR("%s: clk mipi_enable_gate\n", __func__);
lcd_clktree.mipi_bandgap_gate = devm_clk_get(lcd_drv->dev,
"mipi_bandgap_gate");
if (IS_ERR(lcd_clktree.mipi_bandgap_gate))
if (IS_ERR_OR_NULL(lcd_clktree.mipi_bandgap_gate))
LCDERR("%s: clk mipi_bandgap_gate\n", __func__);
LCDPR("lcd_clktree_probe\n");
@@ -1761,27 +1848,27 @@ static void lcd_clktree_probe_g12a(void)
lcd_clktree.clk_gate_state = 0;
lcd_clktree.dsi_host_gate = devm_clk_get(lcd_drv->dev, "dsi_host_gate");
if (IS_ERR(lcd_clktree.dsi_host_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_host_gate))
LCDERR("%s: clk dsi_host_gate\n", __func__);
lcd_clktree.dsi_phy_gate = devm_clk_get(lcd_drv->dev, "dsi_phy_gate");
if (IS_ERR(lcd_clktree.dsi_phy_gate))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_phy_gate))
LCDERR("%s: clk dsi_phy_gate\n", __func__);
lcd_clktree.dsi_meas = devm_clk_get(lcd_drv->dev, "dsi_meas");
if (IS_ERR(lcd_clktree.dsi_meas))
if (IS_ERR_OR_NULL(lcd_clktree.dsi_meas))
LCDERR("%s: clk dsi_meas\n", __func__);
lcd_clktree.encl_top_gate = devm_clk_get(lcd_drv->dev, "encl_top_gate");
if (IS_ERR(lcd_clktree.encl_top_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
LCDERR("%s: clk encl_top_gate\n", __func__);
lcd_clktree.encl_int_gate = devm_clk_get(lcd_drv->dev, "encl_int_gate");
if (IS_ERR(lcd_clktree.encl_int_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
LCDERR("%s: clk encl_int_gate\n", __func__);
lcd_clktree.gp0_pll = devm_clk_get(lcd_drv->dev, "gp0_pll");
if (IS_ERR(lcd_clktree.gp0_pll))
if (IS_ERR_OR_NULL(lcd_clktree.gp0_pll))
LCDERR("%s: clk gp0_pll\n", __func__);
LCDPR("lcd_clktree_probe\n");
@@ -1795,34 +1882,27 @@ static void lcd_clktree_probe_tl1(void)
lcd_clktree.clk_gate_state = 0;
lcd_clktree.encl_top_gate = devm_clk_get(lcd_drv->dev, "encl_top_gate");
if (IS_ERR(lcd_clktree.encl_top_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
LCDERR("%s: get encl_top_gate error\n", __func__);
lcd_clktree.encl_int_gate = devm_clk_get(lcd_drv->dev, "encl_int_gate");
if (IS_ERR(lcd_clktree.encl_int_gate))
if (IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
LCDERR("%s: get encl_int_gate error\n", __func__);
switch (lcd_drv->lcd_config->lcd_basic.lcd_type) {
case LCD_MLVDS:
case LCD_P2P:
lcd_clktree.tcon_gate = devm_clk_get(lcd_drv->dev, "tcon_gate");
if (IS_ERR(lcd_clktree.tcon_gate))
LCDERR("%s: get tcon_gate error\n", __func__);
lcd_clktree.tcon_gate = devm_clk_get(lcd_drv->dev, "tcon_gate");
if (IS_ERR_OR_NULL(lcd_clktree.tcon_gate))
LCDERR("%s: get tcon_gate error\n", __func__);
temp_clk = devm_clk_get(lcd_drv->dev, "fclk_div5");
if (IS_ERR(temp_clk)) {
LCDERR("%s: clk fclk_div5\n", __func__);
return;
}
lcd_clktree.tcon_clk = devm_clk_get(lcd_drv->dev, "clk_tcon");
if (IS_ERR(lcd_clktree.tcon_clk))
LCDERR("%s: clk clk_tcon\n", __func__);
else
clk_set_parent(lcd_clktree.tcon_clk, temp_clk);
break;
default:
break;
temp_clk = devm_clk_get(lcd_drv->dev, "fclk_div5");
if (IS_ERR_OR_NULL(temp_clk)) {
LCDERR("%s: clk fclk_div5\n", __func__);
return;
}
lcd_clktree.tcon_clk = devm_clk_get(lcd_drv->dev, "clk_tcon");
if (IS_ERR_OR_NULL(lcd_clktree.tcon_clk))
LCDERR("%s: clk clk_tcon\n", __func__);
else
clk_set_parent(lcd_clktree.tcon_clk, temp_clk);
LCDPR("lcd_clktree_probe\n");
}
@@ -1834,9 +1914,9 @@ static void lcd_clktree_remove_dft(void)
if (lcd_debug_print_flag)
LCDPR("lcd_clktree_remove\n");
if (!IS_ERR(lcd_clktree.encl_top_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.encl_top_gate);
if (!IS_ERR(lcd_clktree.encl_int_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.encl_int_gate);
}
@@ -1847,17 +1927,17 @@ static void lcd_clktree_remove_axg(void)
if (lcd_debug_print_flag)
LCDPR("lcd_clktree_remove\n");
if (!IS_ERR(lcd_clktree.mipi_bandgap_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.mipi_bandgap_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.mipi_bandgap_gate);
if (!IS_ERR(lcd_clktree.mipi_enable_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.mipi_enable_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.mipi_enable_gate);
if (!IS_ERR(lcd_clktree.dsi_meas))
if (!IS_ERR_OR_NULL(lcd_clktree.dsi_meas))
devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_meas);
if (!IS_ERR(lcd_clktree.dsi_phy_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.dsi_phy_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_phy_gate);
if (!IS_ERR(lcd_clktree.dsi_host_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.dsi_host_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_host_gate);
if (!IS_ERR(lcd_clktree.gp0_pll))
if (!IS_ERR_OR_NULL(lcd_clktree.gp0_pll))
devm_clk_put(lcd_drv->dev, lcd_clktree.gp0_pll);
}
@@ -1868,15 +1948,15 @@ static void lcd_clktree_remove_g12a(void)
if (lcd_debug_print_flag)
LCDPR("lcd_clktree_remove\n");
if (!IS_ERR(lcd_clktree.dsi_host_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.dsi_host_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_host_gate);
if (!IS_ERR(lcd_clktree.dsi_phy_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.dsi_phy_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_phy_gate);
if (!IS_ERR(lcd_clktree.dsi_meas))
if (!IS_ERR_OR_NULL(lcd_clktree.dsi_meas))
devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_meas);
if (!IS_ERR(lcd_clktree.encl_top_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.encl_top_gate);
if (!IS_ERR(lcd_clktree.encl_int_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.encl_int_gate);
}
@@ -1887,22 +1967,14 @@ static void lcd_clktree_remove_tl1(void)
if (lcd_debug_print_flag)
LCDPR("lcd_clktree_remove\n");
if (!IS_ERR(lcd_clktree.encl_top_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.encl_top_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.encl_top_gate);
if (!IS_ERR(lcd_clktree.encl_int_gate))
if (!IS_ERR_OR_NULL(lcd_clktree.encl_int_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.encl_int_gate);
switch (lcd_drv->lcd_config->lcd_basic.lcd_type) {
case LCD_MLVDS:
case LCD_P2P:
if (!IS_ERR(lcd_clktree.tcon_clk))
devm_clk_put(lcd_drv->dev, lcd_clktree.tcon_clk);
if (IS_ERR(lcd_clktree.tcon_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.tcon_gate);
break;
default:
break;
}
if (!IS_ERR_OR_NULL(lcd_clktree.tcon_clk))
devm_clk_put(lcd_drv->dev, lcd_clktree.tcon_clk);
if (IS_ERR_OR_NULL(lcd_clktree.tcon_gate))
devm_clk_put(lcd_drv->dev, lcd_clktree.tcon_gate);
}
static void lcd_clk_config_init_print_dft(void)

2
drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h
View File

@@ -232,7 +232,7 @@
/* video */
#define CLK_DIV_IN_MAX_TL1 (3100 * 1000)
#define CRT_VID_CLK_IN_MAX_TL1 (3100 * 1000)
#define ENCL_CLK_IN_MAX_TL1 (400 * 1000)
#define ENCL_CLK_IN_MAX_TL1 (750 * 1000)
/* **********************************

41
drivers/amlogic/media/vout/lcd/lcd_common.c
View File

@@ -363,35 +363,42 @@ void lcd_vbyone_pinmux_set(int status)
pconf->pinmux_flag = index;
}
static char *lcd_tcon_pinmux_str[] = {
"tcon",
"tcon_off",
"none",
};
void lcd_tcon_pinmux_set(int status)
{
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
struct lcd_config_s *pconf;
unsigned int index;
if (lcd_debug_print_flag)
LCDPR("%s: %d\n", __func__, status);
pconf = lcd_drv->lcd_config;
if (status) {
if (pconf->pinmux_flag == 0) {
pconf->pinmux_flag = 1;
/* request pinmux */
pconf->pin = devm_pinctrl_get_select(lcd_drv->dev,
"tcon");
if (IS_ERR(pconf->pin))
LCDERR("set tcon pinmux error\n");
} else {
LCDPR("tcon pinmux is already selected\n");
}
index = (status) ? 0 : 1;
if (pconf->pinmux_flag == index) {
LCDPR("pinmux %s is already selected\n",
lcd_tcon_pinmux_str[index]);
return;
}
pconf->pin = devm_pinctrl_get_select(lcd_drv->dev,
lcd_tcon_pinmux_str[index]);
if (IS_ERR(pconf->pin)) {
LCDERR("set vbyone pinmux %s error\n",
lcd_tcon_pinmux_str[index]);
} else {
if (pconf->pinmux_flag) {
pconf->pinmux_flag = 0;
/* release pinmux */
devm_pinctrl_put(pconf->pin);
} else {
LCDPR("tcon pinmux is already released\n");
if (lcd_debug_print_flag) {
LCDPR("set vbyone pinmux %s: %p\n",
lcd_tcon_pinmux_str[index], pconf->pin);
}
}
pconf->pinmux_flag = index;
}
unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf)

2
drivers/amlogic/media/vout/lcd/lcd_common.h
View File

@@ -118,6 +118,8 @@ extern void lcd_venc_change(struct lcd_config_s *pconf);
extern void lcd_if_enable_retry(struct lcd_config_s *pconf);
/* lcd tcon */
extern unsigned int lcd_tcon_reg_read(unsigned int addr);
extern void lcd_tcon_reg_write(unsigned int addr, unsigned int val);
extern void lcd_tcon_reg_table_print(void);
extern void lcd_tcon_reg_readback_print(void);
extern int lcd_tcon_info_print(char *buf, int offset);

193
drivers/amlogic/media/vout/lcd/lcd_debug.c
View File

@@ -41,7 +41,7 @@
static struct lcd_debug_info_reg_s *lcd_debug_info_reg;
static struct lcd_debug_info_if_s *lcd_debug_info_if;
#define PR_BUF_MAX 2048
#define PR_BUF_MAX 4096
static void lcd_debug_parse_param(char *buf_orig, char **parm)
{
@@ -464,7 +464,7 @@ static int lcd_info_print_p2p(char *buf, int offset)
n = lcd_debug_info_len(len + offset);
len += snprintf((buf+len), n,
"channel_num %d\n"
"lane_num %d\n"
"channel_sel1 0x%08x\n"
"channel_sel1 0x%08x\n"
"clk_phase 0x%04x\n"
@@ -474,7 +474,7 @@ static int lcd_info_print_p2p(char *buf, int offset)
"phy_preem 0x%x\n"
"bit_rate %dHz\n"
"pi_clk_sel 0x%03x\n\n",
pconf->lcd_control.p2p_config->channel_num,
pconf->lcd_control.p2p_config->lane_num,
pconf->lcd_control.p2p_config->channel_sel0,
pconf->lcd_control.p2p_config->channel_sel1,
pconf->lcd_control.p2p_config->clk_phase,
@@ -962,28 +962,13 @@ static int lcd_reg_print_p2p(char *buf, int offset)
int n, len = 0;
n = lcd_debug_info_len(len + offset);
len += snprintf((buf+len), n, "\nmlvds regs:\n");
len += snprintf((buf+len), n, "\np2p regs:\n");
n = lcd_debug_info_len(len + offset);
reg = HHI_TCON_CLK_CNTL;
reg = HHI_TCON_CLK_CNTL_TL1;
len += snprintf((buf+len), n,
"HHI_TCON_CLK_CNTL [0x%04x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_TCON_CNTL0;
len += snprintf((buf+len), n,
"HHI_DIF_TCON_CNTL0 [0x%04x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_TCON_CNTL1;
len += snprintf((buf+len), n,
"HHI_DIF_TCON_CNTL1 [0x%04x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_TCON_CNTL2;
len += snprintf((buf+len), n,
"HHI_DIF_TCON_CNTL2 [0x%04x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = TCON_TOP_CTRL;
@@ -1077,17 +1062,103 @@ static int lcd_reg_print_phy_analog(char *buf, int offset)
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL1;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL1 [0x%04x] = 0x%08x\n",
"HHI_DIF_CSI_PHY_CNTL1 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL2;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL2 [0x%04x] = 0x%08x\n",
"HHI_DIF_CSI_PHY_CNTL2 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL3;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL3 [0x%04x] = 0x%08x\n",
"HHI_DIF_CSI_PHY_CNTL3 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
return len;
}
static int lcd_reg_print_phy_analog_tl1(char *buf, int offset)
{
unsigned int reg;
int n, len = 0;
n = lcd_debug_info_len(len + offset);
len += snprintf((buf+len), n, "\nphy analog regs:\n");
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL1;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL1 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL2;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL2 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL3;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL3 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL4;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL4 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL6;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL6 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL7;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL7 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL8;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL8 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL9;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL9 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL10;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL10 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL11;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL11 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL12;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL12 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL13;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL13 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL14;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL14 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL15;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL15 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_DIF_CSI_PHY_CNTL16;
len += snprintf((buf+len), n,
"HHI_DIF_CSI_PHY_CNTL16 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
return len;
@@ -1103,17 +1174,17 @@ static int lcd_reg_print_mipi_phy_analog(char *buf, int offset)
n = lcd_debug_info_len(len + offset);
reg = HHI_MIPI_CNTL0;
len += snprintf((buf+len), n,
"HHI_MIPI_CNTL0 [0x%04x] = 0x%08x\n",
"HHI_MIPI_CNTL0 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_MIPI_CNTL1;
len += snprintf((buf+len), n,
"HHI_MIPI_CNTL1 [0x%04x] = 0x%08x\n",
"HHI_MIPI_CNTL1 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
n = lcd_debug_info_len(len + offset);
reg = HHI_MIPI_CNTL2;
len += snprintf((buf+len), n,
"HHI_MIPI_CNTL2 [0x%04x] = 0x%08x\n",
"HHI_MIPI_CNTL2 [0x%02x] = 0x%08x\n",
reg, lcd_hiu_read(reg));
return len;
@@ -1139,7 +1210,7 @@ static int lcd_reg_print(char *buf, int offset)
break;
n = lcd_debug_info_len(len + offset);
len += snprintf((buf+len), n,
"hiu [0x%08x] = 0x%08x\n",
"hiu [0x%02x] = 0x%08x\n",
table[i], lcd_hiu_read(table[i]));
i++;
}
@@ -1174,7 +1245,7 @@ static int lcd_reg_print(char *buf, int offset)
if (table[i] == LCD_DEBUG_REG_END)
break;
len += snprintf((buf+len), n,
"PERIPHS_PIN_MUX [0x%08x] = 0x%08x\n",
"PERIPHS_PIN_MUX [0x%02x] = 0x%08x\n",
table[i], lcd_periphs_read(table[i]));
i++;
}
@@ -1967,18 +2038,18 @@ static ssize_t lcd_debug_change_store(struct class *class,
ret = sscanf(buf, "p2p %d %x %x %x %d %d",
&val[0], &val[1], &val[2], &val[3], &val[4], &val[5]);
if (ret == 6) {
p2p_conf->channel_num = val[0];
p2p_conf->lane_num = val[0];
p2p_conf->channel_sel0 = val[1];
p2p_conf->channel_sel1 = val[2];
p2p_conf->clk_phase = val[3];
p2p_conf->pn_swap = val[4];
p2p_conf->bit_swap = val[5];
pr_info("change mlvds config:\n"
"channel_num=%d,\n"
pr_info("change p2p config:\n"
"lane_num=%d,\n"
"channel_sel0=0x%08x, channel_sel1=0x%08x,\n"
"clk_phase=0x%04x,\n"
"pn_swap=%d, bit_swap=%d\n",
p2p_conf->channel_num,
p2p_conf->lane_num,
p2p_conf->channel_sel0,
p2p_conf->channel_sel1,
p2p_conf->clk_phase,
@@ -2433,6 +2504,16 @@ static void lcd_debug_reg_write(unsigned int reg, unsigned int data,
pr_info("write mipi_dsi_phy [0x%04x] = 0x%08x, readback 0x%08x\n",
reg, data, dsi_phy_read(reg));
break;
case 6: /* tcon */
lcd_tcon_reg_write(reg, data);
if (reg < TCON_TOP_BASE) {
pr_info("write tcon [0x%04x] = 0x%02x, readback 0x%02x\n",
reg, data, lcd_tcon_reg_read(reg));
} else {
pr_info("write tcon [0x%04x] = 0x%08x, readback 0x%08x\n",
reg, data, lcd_tcon_reg_read(reg));
}
break;
default:
break;
}
@@ -2465,6 +2546,15 @@ static void lcd_debug_reg_read(unsigned int reg, unsigned int bus)
pr_info("read mipi_dsi_phy [0x%04x] = 0x%08x\n",
reg, dsi_phy_read(reg));
break;
case 6:
if (reg < TCON_TOP_BASE) {
pr_info("read tcon [0x%04x] = 0x%02x\n",
reg, lcd_tcon_reg_read(reg));
} else {
pr_info("read tcon [0x%04x] = 0x%08x\n",
reg, lcd_tcon_reg_read(reg));
}
break;
default:
break;
}
@@ -2518,6 +2608,20 @@ static void lcd_debug_reg_dump(unsigned int reg, unsigned int num,
(reg + i), dsi_phy_read(reg + i));
}
break;
case 6:
pr_info("dump tcon regs:\n");
if (reg < TCON_TOP_BASE) {
for (i = 0; i < num; i++) {
pr_info("[0x%04x] = 0x%02x\n",
(reg + i), lcd_tcon_reg_read(reg + i));
}
} else {
for (i = 0; i < num; i++) {
pr_info("[0x%04x] = 0x%08x\n",
(reg + i), lcd_tcon_reg_read(reg + i));
}
}
break;
default:
break;
}
@@ -2552,6 +2656,9 @@ static ssize_t lcd_debug_reg_store(struct class *class,
ret = sscanf(buf, "wmp %x %x", &reg32, &data32);
bus = 5;
}
} else if (buf[1] == 't') {
ret = sscanf(buf, "wt %x %x", &reg32, &data32);
bus = 6;
}
if (ret == 2) {
lcd_debug_reg_write(reg32, data32, bus);
@@ -2581,6 +2688,9 @@ static ssize_t lcd_debug_reg_store(struct class *class,
ret = sscanf(buf, "rmp %x", &reg32);
bus = 5;
}
} else if (buf[1] == 't') {
ret = sscanf(buf, "rt %x", &reg32);
bus = 6;
}
if (ret == 1) {
lcd_debug_reg_read(reg32, bus);
@@ -2610,6 +2720,9 @@ static ssize_t lcd_debug_reg_store(struct class *class,
ret = sscanf(buf, "dmp %x %d", &reg32, &data32);
bus = 5;
}
} else if (buf[1] == 't') {
ret = sscanf(buf, "dt %x %d", &reg32, &data32);
bus = 6;
}
if (ret == 2) {
lcd_debug_reg_dump(reg32, data32, bus);
@@ -2978,7 +3091,7 @@ static const char *lcd_mlvds_debug_usage_str = {
static const char *lcd_p2p_debug_usage_str = {
"Usage:\n"
" echo <channel_num> <channel_sel0> <channel_sel1> <clk_phase> <pn_swap> <bit_swap> > minilvds ; set minilvds config\n"
" echo <lane_num> <channel_sel0> <channel_sel1> <clk_phase> <pn_swap> <bit_swap> > minilvds ; set minilvds config\n"
"data format:\n"
" <channel_sel> : minilvds 8 channels mapping in tx 10 channels\n"
" <clk_phase> : bit[13:12]=clk01_pi_sel, bit[11:8]=pi2, bit[7:4]=pi1, bit[3:0]=pi0\n"
@@ -3287,17 +3400,17 @@ static ssize_t lcd_p2p_debug_store(struct class *class,
p2p_conf = lcd_drv->lcd_config->lcd_control.p2p_config;
ret = sscanf(buf, "%d %x %x %x %d %d",
&p2p_conf->channel_num,
&p2p_conf->lane_num,
&p2p_conf->channel_sel0, &p2p_conf->channel_sel1,
&p2p_conf->clk_phase,
&p2p_conf->pn_swap, &p2p_conf->bit_swap);
if (ret == 6) {
pr_info("set minilvds config:\n"
"channel_num=%d,\n"
"lane_num=%d,\n"
"channel_sel0=0x%08x, channel_sel1=0x%08x,\n"
"clk_phase=0x%04x,\n"
"pn_swap=%d, bit_swap=%d\n",
p2p_conf->channel_num,
p2p_conf->lane_num,
p2p_conf->channel_sel0, p2p_conf->channel_sel1,
p2p_conf->clk_phase,
p2p_conf->pn_swap, p2p_conf->bit_swap);
@@ -4236,6 +4349,14 @@ int lcd_debug_probe(void)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
lcd_debug_info_reg = &lcd_debug_info_reg_tl1;
lcd_debug_info_if_lvds.reg_dump_phy =
lcd_reg_print_phy_analog_tl1;
lcd_debug_info_if_vbyone.reg_dump_phy =
lcd_reg_print_phy_analog_tl1;
lcd_debug_info_if_mlvds.reg_dump_phy =
lcd_reg_print_phy_analog_tl1;
lcd_debug_info_if_p2p.reg_dump_phy =
lcd_reg_print_phy_analog_tl1;
break;
case LCD_CHIP_G12A:
case LCD_CHIP_G12B:

6
drivers/amlogic/media/vout/lcd/lcd_debug.h
View File

@@ -178,9 +178,9 @@ static unsigned int lcd_reg_dump_pinmux_txlx[] = {
};
static unsigned int lcd_reg_dump_pinmux_tl1[] = {
PERIPHS_PIN_MUX_7,
PERIPHS_PIN_MUX_8,
PERIPHS_PIN_MUX_9,
PERIPHS_PIN_MUX_7_TL1,
PERIPHS_PIN_MUX_8_TL1,
PERIPHS_PIN_MUX_9_TL1,
LCD_DEBUG_REG_END,
};

51
drivers/amlogic/media/vout/lcd/lcd_reg.h
View File

@@ -58,6 +58,23 @@
#define PERIPHS_PIN_MUX_11 0x37
#define PERIPHS_PIN_MUX_12 0x38
#define PERIPHS_PIN_MUX_0_TL1 0x0b0
#define PERIPHS_PIN_MUX_1_TL1 0x0b1
#define PERIPHS_PIN_MUX_2_TL1 0x0b2
#define PERIPHS_PIN_MUX_3_TL1 0x0b3
#define PERIPHS_PIN_MUX_4_TL1 0x0b4
#define PERIPHS_PIN_MUX_5_TL1 0x0b5
#define PERIPHS_PIN_MUX_6_TL1 0x0b6
#define PERIPHS_PIN_MUX_7_TL1 0x0b7
#define PERIPHS_PIN_MUX_8_TL1 0x0b8
#define PERIPHS_PIN_MUX_9_TL1 0x0b9
#define PERIPHS_PIN_MUX_A_TL1 0x0ba
#define PERIPHS_PIN_MUX_B_TL1 0x0bb
#define PERIPHS_PIN_MUX_C_TL1 0x0bc
#define PERIPHS_PIN_MUX_D_TL1 0x0bd
#define PERIPHS_PIN_MUX_E_TL1 0x0be
#define PERIPHS_PIN_MUX_F_TL1 0x0bf
/* HIU: HHI_CBUS_BASE = 0x10 */
#define HHI_GCLK_MPEG0 0x50
@@ -139,14 +156,13 @@
#define HHI_DSI_LVDS_EDP_CNTL0 0xd1
#define HHI_DSI_LVDS_EDP_CNTL1 0xd2
#define HHI_DIF_CSI_PHY_CNTL0 0xd8
#define HHI_DIF_CSI_PHY_CNTL1 0xd9
#define HHI_DIF_CSI_PHY_CNTL2 0xda
#define HHI_DIF_CSI_PHY_CNTL3 0xdb
#define HHI_DIF_CSI_PHY_CNTL4 0xdc
#define HHI_DIF_CSI_PHY_CNTL5 0xdd
#define HHI_LVDS_TX_PHY_CNTL0 0xde
#define HHI_LVDS_TX_PHY_CNTL1 0xdf
#define HHI_LVDS_TX_PHY_CNTL0_TL1 0x9a
#define HHI_LVDS_TX_PHY_CNTL1_TL1 0x9b
#define HHI_VID2_PLL_CNTL 0xe0
#define HHI_VID2_PLL_CNTL2 0xe1
#define HHI_VID2_PLL_CNTL3 0xe2
@@ -155,6 +171,19 @@
#define HHI_VID2_PLL_CNTL6 0xe5
#define HHI_VID_LOCK_CLK_CNTL 0xf2
#define HHI_DIF_CSI_PHY_CNTL10 0x8e
#define HHI_DIF_CSI_PHY_CNTL11 0x8f
#define HHI_DIF_CSI_PHY_CNTL12 0x90
#define HHI_DIF_CSI_PHY_CNTL13 0x91
#define HHI_DIF_CSI_PHY_CNTL14 0x92
#define HHI_DIF_CSI_PHY_CNTL15 0x93
#define HHI_DIF_CSI_PHY_CNTL16 0xde
#define HHI_DIF_CSI_PHY_CNTL4 0xe9
#define HHI_DIF_CSI_PHY_CNTL6 0xea
#define HHI_DIF_CSI_PHY_CNTL7 0xeb
#define HHI_DIF_CSI_PHY_CNTL8 0xec
#define HHI_DIF_CSI_PHY_CNTL9 0xed
/* AXG use PLL 0xff63c000 */
#define HHI_GP0_PLL_CNTL_AXG 0x10
#define HHI_GP0_PLL_CNTL2_AXG 0x11
@@ -175,14 +204,15 @@
#define HHI_MIPIDSI_PHY_CLK_CNTL 0x95
#define HHI_MIPI_CNTL0 0x00
#define HHI_MIPI_CNTL1 0x01
#define HHI_MIPI_CNTL2 0x02
#define HHI_MIPI_CNTL0 0x00
#define HHI_MIPI_CNTL1 0x01
#define HHI_MIPI_CNTL2 0x02
#define HHI_DIF_TCON_CNTL0 0x3c
#define HHI_DIF_TCON_CNTL1 0x3d
#define HHI_DIF_TCON_CNTL2 0x3e
#define HHI_TCON_CLK_CNTL 0xf0
#define HHI_TCON_CLK_CNTL_TL1 0x9c
/* Global control: RESET_CBUS_BASE = 0x11 */
#define VERSION_CTRL 0x1100
@@ -711,6 +741,9 @@
* G5B10 Other
*/
#define LCD_MCU_DATA_1 0x14df
#define LVDS_CH_SWAP0 0x14e1
#define LVDS_CH_SWAP1 0x14e2
#define LVDS_CH_SWAP2 0x14e3
/* LVDS */
#define LVDS_GEN_CNTL 0x14e0
#define LVDS_PHY_CNTL0 0x14e1
@@ -909,8 +942,13 @@
#define ENCL_DACSEL_0 0x1cc9
#define ENCL_DACSEL_1 0x1cca
#define ENCL_VIDEO_H_PRE_DE_END 0x1ccf
#define ENCL_VIDEO_H_PRE_DE_BEGIN 0x1cd0
#define ENCL_VIDEO_V_PRE_DE_ELINE 0x1cd1
#define ENCL_VIDEO_V_PRE_DE_BLINE 0x1cd2
#define ENCL_INBUF_CNTL0 0x1cd3
#define ENCL_INBUF_CNTL1 0x1cd4
#define ENCL_INBUF_CNT 0x1cd5
/* ********************************
* TCON TOP: TCON_TOP_BASE = 0x2000
@@ -920,6 +958,7 @@
#define TCON_CTRL_TIMING_BASE 0x01b0
#define TCON_TOP_BASE 0x2000
#define TCON_TOP_CTRL 0x2000
#define TCON_RGB_IN_MUX 0x2001
#define TCON_OUT_CH_SEL0 0x2002

55
drivers/amlogic/media/vout/lcd/lcd_tcon.c
View File

@@ -33,6 +33,7 @@
#include "lcd_common.h"
#include "lcd_reg.h"
#include "lcd_tcon.h"
#include "tcon_ceds.h"
#define TCON_INTR_MASKN_VAL 0x0 /* default mask all */
@@ -54,6 +55,48 @@ static int lcd_tcon_valid_check(void)
return 0;
}
unsigned int lcd_tcon_reg_read(unsigned int addr)
{
unsigned int val;
int ret;
ret = lcd_tcon_valid_check();
if (ret)
return 0;
if (addr < TCON_TOP_BASE) {
if (lcd_tcon_data->core_reg_width == 8)
val = lcd_tcon_read_byte(addr);
else
val = lcd_tcon_read(addr);
} else {
val = lcd_tcon_read(addr);
}
return val;
}
void lcd_tcon_reg_write(unsigned int addr, unsigned int val)
{
unsigned char temp;
int ret;
ret = lcd_tcon_valid_check();
if (ret)
return;
if (addr < TCON_TOP_BASE) {
if (lcd_tcon_data->core_reg_width == 8) {
temp = (unsigned char)val;
lcd_tcon_write_byte(addr, temp);
} else {
lcd_tcon_write(addr, val);
}
} else {
lcd_tcon_write(addr, val);
}
}
static void lcd_tcon_od_check(unsigned char *table)
{
unsigned int reg, bit;
@@ -227,6 +270,7 @@ static int lcd_tcon_config(struct aml_lcd_drv_s *lcd_drv)
LCDPR("tcon axi_offset_addr = 0x%08x\n",
lcd_tcon_data->axi_offset_addr);
#if 0
/* get reg table from unifykey */
reg_len = lcd_tcon_data->reg_table_len;
if (lcd_tcon_data->reg_table == NULL) {
@@ -254,6 +298,17 @@ static int lcd_tcon_config(struct aml_lcd_drv_s *lcd_drv)
__func__);
return -1;
}
#else
reg_len = lcd_tcon_data->reg_table_len;
lcd_tcon_data->reg_table = uhd_tcon_setting_ceds_h10;
key_len = sizeof(uhd_tcon_setting_ceds_h10)/sizeof(unsigned char);
if (key_len != reg_len) {
lcd_tcon_data->reg_table = NULL;
LCDERR("%s: !!!!!!!!tcon unifykey load length error!!!!!!!!\n",
__func__);
return -1;
}
#endif
LCDPR("tcon: load key len: %d\n", key_len);
lcd_tcon_intr_init(lcd_drv);

269
drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
View File

@@ -75,6 +75,7 @@ static int lcd_type_supported(struct lcd_config_s *pconf)
static void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
{
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
unsigned int vswing, preem, ext_pullup;
unsigned int data32;
unsigned int rinner_table[] = {0xa, 0xa, 0x6, 0x4};
@@ -97,17 +98,41 @@ static void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
__func__, preem);
preem = VX1_PHY_PREEM_DFT;
}
if (ext_pullup)
data32 = VX1_PHY_CNTL1_G9TV_PULLUP | (vswing << 3);
else
data32 = VX1_PHY_CNTL1_G9TV | (vswing << 3);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
data32 = VX1_PHY_CNTL2_G9TV | (preem << 20) |
(rinner_table[ext_pullup] << 8);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
data32 = VX1_PHY_CNTL3_G9TV;
/*lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x00000a7c);*/
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0xf02027af);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x26022602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x26022602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x26022602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0x26022602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0x26022602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0x26022602);
break;
default:
if (ext_pullup) {
data32 = VX1_PHY_CNTL1_G9TV_PULLUP |
(vswing << 3);
} else {
data32 = VX1_PHY_CNTL1_G9TV | (vswing << 3);
}
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
data32 = VX1_PHY_CNTL2_G9TV | (preem << 20) |
(rinner_table[ext_pullup] << 8);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
data32 = VX1_PHY_CNTL3_G9TV;
/*lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x00000a7c);*/
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
break;
}
} else {
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
@@ -117,6 +142,7 @@ static void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
static void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
{
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
unsigned int vswing, preem, clk_vswing, clk_preem, channel_on;
unsigned int data32;
@@ -151,15 +177,36 @@ static void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
clk_preem = LVDS_PHY_CLK_PREEM_DFT;
}
data32 = LVDS_PHY_CNTL1_G9TV |
(vswing << 26) | (preem << 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
data32 = LVDS_PHY_CNTL2_G9TV;
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
data32 = LVDS_PHY_CNTL3_G9TV |
(channel_on << 16) |
(clk_vswing << 8) | (clk_preem << 5);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0xff2027ef);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x06020602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x06020602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x06020602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0x06020602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0x06020602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0x06020602);
break;
default:
data32 = LVDS_PHY_CNTL1_G9TV |
(vswing << 26) | (preem << 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
data32 = LVDS_PHY_CNTL2_G9TV;
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
data32 = LVDS_PHY_CNTL3_G9TV |
(channel_on << 16) |
(clk_vswing << 8) | (clk_preem << 5);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
break;
}
} else {
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
@@ -209,37 +256,25 @@ static void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status)
static void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status)
{
unsigned int vswing, preem;
unsigned int data32;
if (lcd_debug_print_flag)
LCDPR("%s: %d\n", __func__, status);
if (status) {
vswing = pconf->lcd_control.p2p_config->phy_vswing;
preem = pconf->lcd_control.p2p_config->phy_preem;
if (vswing > 7) {
LCDERR("%s: wrong vswing_level=%d, use default\n",
__func__, vswing);
vswing = LVDS_PHY_VSWING_DFT;
}
if (preem > 3) {
LCDERR("%s: wrong preemphasis_level=%d, use default\n",
__func__, preem);
preem = LVDS_PHY_PREEM_DFT;
}
data32 = MLVDS_PHY_CNTL1_TL1 |
(vswing << 3) | (vswing << 0) | (preem << 23);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
data32 = MLVDS_PHY_CNTL2_TL1 |
(preem << 14) | (preem << 12) |
(preem << 26) | (preem << 24);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
data32 = MLVDS_PHY_CNTL3_TL1 |
(preem << 6) | (preem << 4) |
(preem << 2) | (preem << 0) | (preem << 30);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0xff2027af);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x06020602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x06020602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x06020602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0x06020602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0x06020602);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0x06020602);
} else {
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
@@ -318,6 +353,20 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
lcd_vcbus_write(ENCL_VIDEO_HAVON_END, h_active - 1 + video_on_pixel);
lcd_vcbus_write(ENCL_VIDEO_VAVON_BLINE, video_on_line);
lcd_vcbus_write(ENCL_VIDEO_VAVON_ELINE, v_active - 1 + video_on_line);
switch (pconf->lcd_basic.lcd_type) {
case LCD_P2P:
lcd_vcbus_write(ENCL_VIDEO_V_PRE_DE_BLINE,
video_on_line - 1 - 4);
lcd_vcbus_write(ENCL_VIDEO_V_PRE_DE_ELINE,
video_on_line - 1);
lcd_vcbus_write(ENCL_VIDEO_H_PRE_DE_BEGIN,
video_on_pixel + PRE_DE_DELAY);
lcd_vcbus_write(ENCL_VIDEO_H_PRE_DE_END,
h_active - 1 + video_on_pixel + PRE_DE_DELAY);
break;
default:
break;
}
lcd_vcbus_write(ENCL_VIDEO_HSO_BEGIN, pconf->lcd_timing.hs_hs_addr);
lcd_vcbus_write(ENCL_VIDEO_HSO_END, pconf->lcd_timing.hs_he_addr);
@@ -352,7 +401,20 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
{
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
unsigned int phy_div;
unsigned int reg_cntl0, reg_cntl1;
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
break;
default:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1;
break;
}
if (pconf->lcd_control.lvds_config->dual_port)
phy_div = 2;
@@ -360,23 +422,32 @@ static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
phy_div = 1;
/* set fifo_clk_sel: div 7 */
lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (1 << 6));
lcd_hiu_write(reg_cntl0, (1 << 6));
/* set cntl_ser_en: 8-channel to 1 */
lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
switch (lcd_drv->data->chip_type) { /* pn swap */
case LCD_CHIP_TL1:
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
break;
default:
break;
}
/* decoupling fifo enable, gated clock enable */
lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
lcd_hiu_write(reg_cntl1,
(1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
/* decoupling fifo write enable after fifo enable */
lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
lcd_hiu_setb(reg_cntl1, 1, 31, 1);
}
static void lcd_lvds_control_set(struct lcd_config_s *pconf)
{
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
unsigned int bit_num = 1;
unsigned int pn_swap, port_swap, lane_reverse;
unsigned int dual_port, fifo_mode;
unsigned int lvds_repack = 1;
unsigned int ch_swap0, ch_swap1, ch_swap2;
if (lcd_debug_print_flag)
LCDPR("%s\n", __func__);
@@ -423,10 +494,21 @@ static void lcd_lvds_control_set(struct lcd_config_s *pconf)
(1 << 12) | /* g_select //0:R, 1:G, 2:B, 3:0 */
(2 << 14)); /* b_select //0:R, 1:G, 2:B, 3:0 */
lcd_vcbus_setb(LCD_PORT_SWAP, port_swap, 12, 1);
if (lane_reverse)
lcd_vcbus_setb(LVDS_GEN_CNTL, 0x03, 13, 2);
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
ch_swap0 = 0x3210;
ch_swap1 = 0x7654;
ch_swap2 = 0xba98;
lcd_vcbus_write(LVDS_CH_SWAP0, ch_swap0);
lcd_vcbus_write(LVDS_CH_SWAP1, ch_swap1);
lcd_vcbus_write(LVDS_CH_SWAP2, ch_swap2);
break;
default:
lcd_vcbus_setb(LCD_PORT_SWAP, port_swap, 12, 1);
if (lane_reverse)
lcd_vcbus_setb(LVDS_GEN_CNTL, 0x03, 13, 2);
break;
}
lcd_vcbus_write(LVDS_GEN_CNTL,
(lcd_vcbus_read(LVDS_GEN_CNTL) | (1 << 4) | (fifo_mode << 0)));
@@ -548,6 +630,19 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
{
unsigned int lcd_bits;
unsigned int div_sel, phy_div;
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
unsigned int reg_cntl0, reg_cntl1;
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
break;
default:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1;
break;
}
phy_div = pconf->lcd_control.vbyone_config->phy_div;
lcd_bits = pconf->lcd_basic.lcd_bits;
@@ -567,20 +662,28 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
break;
}
/* set fifo_clk_sel */
lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6));
lcd_hiu_write(reg_cntl0, (div_sel << 6));
/* set cntl_ser_en: 8-channel to 1 */
lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
switch (lcd_drv->data->chip_type) { /* pn swap */
case LCD_CHIP_TL1:
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
break;
default:
break;
}
/* decoupling fifo enable, gated clock enable */
lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
lcd_hiu_write(reg_cntl1,
(1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
/* decoupling fifo write enable after fifo enable */
lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
lcd_hiu_setb(reg_cntl1, 1, 31, 1);
}
static int lcd_vbyone_lanes_set(int lane_num, int byte_mode, int region_num,
int hsize, int vsize)
{
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
int sublane_num;
int region_size[4];
int tmp;
@@ -644,6 +747,16 @@ static int lcd_vbyone_lanes_set(int lane_num, int byte_mode, int region_num,
lcd_vcbus_setb(VBO_CTRL_H, 0x1, 9, 1);
/* lcd_vcbus_setb(VBO_CTRL_L,enable,0,1); */
switch (lcd_drv->data->chip_type) { /* pn swap */
case LCD_CHIP_TL1:
lcd_vcbus_write(LVDS_CH_SWAP0, 0x3210);
lcd_vcbus_write(LVDS_CH_SWAP1, 0x7654);
lcd_vcbus_write(LVDS_CH_SWAP2, 0xba98);
break;
default:
break;
}
return 0;
}
@@ -775,7 +888,8 @@ static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
/* lcd_vcbus_setb(LCD_PORT_SWAP, 1, 8, 1);//reverse lane output order */
/* Mux pads in combo-phy: 0 for dsi; 1 for lvds or vbyone; 2 for edp */
lcd_hiu_write(HHI_DSI_LVDS_EDP_CNTL0, 0x1);
/*lcd_hiu_write(HHI_DSI_LVDS_EDP_CNTL0, 0x1);*/
lcd_vcbus_write(VBO_INFILTER_CTRL, 0xff77);
lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 2);
lcd_vcbus_setb(VBO_CTRL_L, 1, 0, 1);
@@ -1295,10 +1409,39 @@ static irqreturn_t lcd_vbyone_interrupt_handler(int irq, void *dev_id)
static void lcd_p2p_control_set(struct lcd_config_s *pconf)
{
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
unsigned int reg_cntl0, reg_cntl1;
if (lcd_debug_print_flag)
LCDPR("%s\n", __func__);
lcd_vbyone_control_set(pconf);
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
break;
default:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1;
break;
}
/* fifo_clk_sel[7:6]: 0=div6, 1=div 7, 2=div8, 3=div10 */
lcd_hiu_write(reg_cntl0, (2 << 6));
/* serializer_en[27:16] */
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
/* pn swap[2] */
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
/* fifo enable[30], phy_clock gating[24] */
lcd_hiu_write(reg_cntl1, (1 << 30) | (1 << 24));
/* fifo write enable[31] */
lcd_hiu_setb(reg_cntl1, 1, 31, 1);
/* channel swap default no swap */
lcd_vcbus_write(LVDS_CH_SWAP0, 0x3210);
lcd_vcbus_write(LVDS_CH_SWAP1, 0x7654);
lcd_vcbus_write(LVDS_CH_SWAP2, 0xba98);
lcd_tcon_enable(pconf);
}
@@ -1306,8 +1449,6 @@ static void lcd_p2p_control_set(struct lcd_config_s *pconf)
static void lcd_p2p_disable(void)
{
lcd_tcon_disable();
lcd_vbyone_disable();
}
static unsigned int vbyone_lane_num[] = {
@@ -1583,8 +1724,8 @@ int lcd_tv_driver_init(void)
break;
case LCD_P2P:
lcd_p2p_control_set(pconf);
lcd_tcon_pinmux_set(1);
lcd_p2p_phy_set(pconf, 1);
lcd_tcon_pinmux_set(1);
break;
default:
break;

2
drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c
View File

@@ -1001,6 +1001,8 @@ static int lcd_config_load_from_dts(struct lcd_config_s *pconf,
}
}
break;
case LCD_P2P:
break;
default:
LCDERR("invalid lcd type\n");
break;

34
drivers/amlogic/media/vout/lcd/lcd_vout.c
View File

@@ -115,6 +115,36 @@ static struct vbyone_config_s lcd_vbyone_config = {
.cdr_training_hold = VX1_CDR_TRAINING_HOLD_DFT,
};
static struct mlvds_config_s lcd_mlvds_config = {
.channel_num = 12,
.channel_sel0 = 0x76543210,
.channel_sel1 = 0xba98,
.clk_phase = 0,
.pn_swap = 0,
.bit_swap = 0,
.phy_vswing = 0,
.phy_preem = 0,
.pi_clk_sel = 0,
.bit_rate = 0,
};
static struct p2p_config_s lcd_p2p_config = {
.p2p_type = P2P_MAX,
.port_num = 6,
.lane_num = 12,
.channel_sel0 = 0x76543210,
.channel_sel1 = 0xba98,
.clk_phase = 0,
.pn_swap = 0,
.bit_swap = 0,
.phy_vswing = 0,
.phy_preem = 0,
.pi_clk_sel = 0,
.bit_rate = 0,
};
static unsigned char dsi_init_on_table[DSI_INIT_ON_MAX] = {0xff, 0xff};
static unsigned char dsi_init_off_table[DSI_INIT_OFF_MAX] = {0xff, 0xff};
@@ -197,6 +227,8 @@ static struct lcd_config_s lcd_config_dft = {
.ttl_config = &lcd_ttl_config,
.lvds_config = &lcd_lvds_config,
.vbyone_config = &lcd_vbyone_config,
.mlvds_config = &lcd_mlvds_config,
.p2p_config = &lcd_p2p_config,
.mipi_config = &lcd_mipi_config,
.vlock_param = vlock_param,
},
@@ -965,6 +997,8 @@ static int lcd_mode_probe(struct device *dev)
LCDERR("invalid lcd mode: %d\n", lcd_driver->lcd_mode);
break;
}
if (lcd_driver->data->chip_type == LCD_CHIP_TL1)
lcd_tcon_probe(lcd_driver);
lcd_debug_probe();
lcd_fops_create();

24019
drivers/amlogic/media/vout/lcd/tcon_ceds.h Normal file
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File diff suppressed because it is too large Load Diff

10
include/linux/amlogic/media/vout/lcd/lcd_vout.h
View File

@@ -69,6 +69,7 @@ extern unsigned char lcd_debug_print_flag;
* **********************************
*/
#define TTL_DELAY 13
#define PRE_DE_DELAY 8
/* **********************************
@@ -338,8 +339,15 @@ struct mlvds_config_s {
unsigned int bit_rate; /* Hz */
};
enum p2p_type_e {
P2P_CEDS = 0,
P2P_MAX,
};
struct p2p_config_s {
unsigned int channel_num;
unsigned int p2p_type;
unsigned int port_num;
unsigned int lane_num;
unsigned int channel_sel0;
unsigned int channel_sel1;
unsigned int clk_phase; /* [13:12]=clk01_pi_sel,