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drm/rockchip: vop2: add support post scale

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Change-Id: I564235c41a59b767f433cfc2eb85cf8f71eea74c
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang
2020-12-09 11:05:57 +08:00
committed by Tao Huang
parent 2a4e295a77
commit 1b7d995fb2
3 changed files with 62 additions and 12 deletions
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1
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -519,6 +519,7 @@ struct vop2_video_port_regs {
struct vop_reg dsp_interlace;
struct vop_reg dsp_filed_pol;
struct vop_reg dsp_data_swap;
struct vop_reg post_dsp_out_r2y;
struct vop_reg pre_scan_htiming;
struct vop_reg htotal_pw;
struct vop_reg hact_st_end;

70
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -2789,6 +2789,55 @@ static void vop2_dither_setup(struct drm_crtc *crtc)
VOP_MODULE_SET(vop2, vp, dither_down_sel, DITHER_DOWN_ALLEGRO);
}
static void vop2_post_config(struct drm_crtc *crtc)
{
struct rockchip_crtc_state *vcstate =
to_rockchip_crtc_state(crtc->state);
struct vop2_video_port *vp = to_vop2_video_port(crtc);
struct vop2 *vop2 = vp->vop2;
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
u16 vtotal = mode->crtc_vtotal;
u16 hdisplay = mode->crtc_hdisplay;
u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
u16 vdisplay = mode->crtc_vdisplay;
u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
u16 hsize = hdisplay * (vcstate->left_margin + vcstate->right_margin) / 200;
u16 vsize = vdisplay * (vcstate->top_margin + vcstate->bottom_margin) / 200;
u16 hact_end, vact_end;
u32 val;
vsize = rounddown(vsize, 2);
hsize = rounddown(hsize, 2);
hact_st += hdisplay * (100 - vcstate->left_margin) / 200;
hact_end = hact_st + hsize;
val = hact_st << 16;
val |= hact_end;
VOP_MODULE_SET(vop2, vp, hpost_st_end, val);
vact_st += vdisplay * (100 - vcstate->top_margin) / 200;
vact_end = vact_st + vsize;
val = vact_st << 16;
val |= vact_end;
VOP_MODULE_SET(vop2, vp, vpost_st_end, val);
val = scl_cal_scale2(vdisplay, vsize) << 16;
val |= scl_cal_scale2(hdisplay, hsize);
VOP_MODULE_SET(vop2, vp, post_scl_factor, val);
#define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0)
#define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1)
VOP_MODULE_SET(vop2, vp, post_scl_ctrl,
POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) |
POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize));
if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
u16 vact_st_f1 = vtotal + vact_st + 1;
u16 vact_end_f1 = vact_st_f1 + vsize;
val = vact_st_f1 << 16 | vact_end_f1;
VOP_MODULE_SET(vop2, vp, vpost_st_end_f1, val);
}
VOP_MODULE_SET(vop2, vp, post_dsp_out_r2y,
is_yuv_output(vcstate->bus_format));
}
/*
* if adjusted mode update, return true, else return false
*/
@@ -3002,17 +3051,10 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
val = hact_st << 16;
val |= hact_end;
VOP_MODULE_SET(vop2, vp, hact_st_end, val);
VOP_MODULE_SET(vop2, vp, hpost_st_end, val);
val = vact_st << 16;
val |= vact_end;
VOP_MODULE_SET(vop2, vp, vact_st_end, val);
VOP_MODULE_SET(vop2, vp, vpost_st_end, val);
val = scl_cal_scale2(vdisplay, vdisplay) << 16;
val |= scl_cal_scale2(hdisplay, hdisplay);
VOP_MODULE_SET(vop2, vp, post_scl_factor, val);
VOP_MODULE_SET(vop2, vp, post_scl_ctrl, 0);
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
u16 vact_st_f1 = vtotal + vact_st + 1;
@@ -3020,7 +3062,6 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
val = vact_st_f1 << 16 | vact_end_f1;
VOP_MODULE_SET(vop2, vp, vact_st_end_f1, val);
VOP_MODULE_SET(vop2, vp, vpost_st_end_f1, val);
val = vtotal << 16 | (vtotal + vsync_len);
VOP_MODULE_SET(vop2, vp, vs_st_end_f1, val);
@@ -3051,6 +3092,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
else
val = 0;
VOP_MODULE_SET(vop2, vp, dsp_background, val);
vop2_post_config(crtc);
vop2_cfg_done(crtc);
@@ -3531,10 +3573,6 @@ static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state
kfree(vop2_zpos);
}
static void vop2_post_config(struct drm_crtc *crtc)
{
}
static void vop2_tv_config_update(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
@@ -4308,6 +4346,14 @@ static int vop2_create_crtc(struct vop2 *vop2)
rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
drm_object_attach_property(&crtc->base, vop2->soc_id_prop, vp_data->soc_id);
drm_object_attach_property(&crtc->base, vop2->vp_id_prop, vp->id);
drm_object_attach_property(&crtc->base,
drm_dev->mode_config.tv_left_margin_property, 100);
drm_object_attach_property(&crtc->base,
drm_dev->mode_config.tv_right_margin_property, 100);
drm_object_attach_property(&crtc->base,
drm_dev->mode_config.tv_top_margin_property, 100);
drm_object_attach_property(&crtc->base,
drm_dev->mode_config.tv_bottom_margin_property, 100);
}
/*

3
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -359,6 +359,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
.dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
.bg_dly = VOP_REG(RK3568_VP0_BG_MIX_CTRL, 0xff, 24),
.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
@@ -429,6 +430,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
.dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
.post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
.pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
.bg_dly = VOP_REG(RK3568_VP1_BG_MIX_CTRL, 0xff, 24),
.hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
@@ -474,6 +476,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
.dsp_filed_pol = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 6),
.dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7),
.dsp_data_swap = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1f, 8),
.post_dsp_out_r2y = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 15),
.pre_scan_htiming = VOP_REG(RK3568_VP2_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
.bg_dly = VOP_REG(RK3568_VP2_BG_MIX_CTRL, 0xff, 24),
.hpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_HACT_INFO, 0x1fff1fff, 0),