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lcd: add lcd_driver support for tm2 [2/2]
PD#SWPL-6398 Problem: add lcd_driver support Solution: add lcd_chip_tm2 and panel.dtsi Verify: ab301 Change-Id: I3cb5b67826ea2612e69b206168497771d5ced4b2 Signed-off-by: shaochan.liu <shaochan.liu@amlogic.com>
This commit is contained in:
shaochan.liu
committed by
Jianxiong Pan
Jianxiong Pan
parent
b0adddfa90
commit
1bf3efd544
@@ -14848,3 +14848,10 @@ F: include/dt-bindings/gpio/meson-tm2-gpio.h
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AMLOGIC MESON TM2 CLOCK DRIVER
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M: Jian Hu <jian.hu@amlogic.com>
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F: driver/amlogic/clk/tm2/*
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AMLOGIC MESON TM2 LCD DTS
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M: Shaochan Liu <shaochan.liu@amlogic.com>
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F: arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi
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F: arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
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F: arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi
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F: arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
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1066
arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi
Normal file
1066
arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
589
arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
Normal file
589
arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
Normal file
@@ -0,0 +1,589 @@
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/*
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* arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
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*
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* Copyright (C) 2016 Amlogic, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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/ {
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lcd {
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compatible = "amlogic, lcd-tm2";
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status = "okay";
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mode = "tv";
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fr_auto_policy = <0>; /* 0=disable, 1=60/50hz, 2=60/50/48hz */
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key_valid = <0>;
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clocks = <&clkc CLKID_VCLK2_ENCL
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&clkc CLKID_VCLK2_VENCL
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&clkc CLKID_TCON
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&clkc CLKID_FCLK_DIV5
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&clkc CLKID_TCON_PLL_COMP>;
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clock-names = "encl_top_gate",
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"encl_int_gate",
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"tcon_gate",
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"fclk_div5",
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"clk_tcon";
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reg = <0xff660000 0x8100
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0xff634400 0x300>;
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interrupts = <0 3 1
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0 78 1
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0 88 1>;
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interrupt-names = "vsync","vbyone","tcon";
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pinctrl-names = "vbyone","vbyone_off","tcon","tcon_off";
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pinctrl-0 = <&lcd_vbyone_pins>;
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pinctrl-1 = <&lcd_vbyone_off_pins>;
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pinctrl-2 = <&lcd_tcon_pins>;
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pinctrl-3 = <&lcd_tcon_off_pins>;
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pinctrl_version = <2>; /* for uboot */
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/* power type:(0=cpu_gpio, 2=signal, 3=extern, 0xff=ending) */
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/* power index:(gpios_index, or extern_index, 0xff=invalid) */
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/* power value:(0=output low, 1=output high, 2=input) */
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/* power delay:(unit in ms) */
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lvds_0{
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model_name = "1080p-vfreq";
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interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
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basic_setting = <
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1920 1080 /*h_active, v_active*/
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2200 1125 /*h_period, v_period*/
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8 /*lcd_bits */
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16 9>; /*screen_widht, screen_height*/
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range_setting = <
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2060 2650 /*h_period_min,max*/
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1100 1480 /*v_period_min,max*/
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120000000 160000000>; /*pclk_min,max*/
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lcd_timing = <
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44 148 0 /*hs_width, hs_bp, hs_pol*/
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5 30 0>; /*vs_width, vs_bp, vs_pol*/
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clk_attr = <
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2 /*fr_adj_type
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*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
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* 4=hdmi_mode)
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*/
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0 /*clk_ss_level*/
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1 /*clk_auto_generate*/
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0>; /*pixel_clk(unit in Hz)*/
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lvds_attr = <
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1 /*lvds_repack*/
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1 /*dual_port*/
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0 /*pn_swap*/
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0 /*port_swap*/
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0>; /*lane_reverse*/
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phy_attr=<0xf 0>; /*vswing_level, preem_level*/
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/* power step: type, index, value, delay(ms) */
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power_on_step = <
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2 0 0 0 /*signal enable*/
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0xff 0 0 0>; /*ending*/
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power_off_step = <
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2 0 0 10 /*signal disable*/
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0xff 0 0 0>; /*ending*/
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backlight_index = <0xff>;
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};
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lvds_1{
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model_name = "1080p-hfreq_hdmi";
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interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
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basic_setting = <
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1920 1080 /*h_active, v_active*/
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2200 1125 /*h_period, v_period*/
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8 /*lcd_bits*/
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16 9>; /*screen_widht, screen_height*/
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range_setting = <
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2080 2720 /*h_period min, max*/
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1100 1380 /*v_period min, max*/
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133940000 156000000>; /*pclk_min, max*/
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lcd_timing = <
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44 148 0 /*hs_width, hs_bp, hs_pol*/
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5 30 0>; /*vs_width, vs_bp, vs_pol*/
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clk_attr = <
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4 /*fr_adj_type
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*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
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* 4=hdmi_mode)
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*/
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0 /*clk_ss_level */
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1 /*clk_auto_generate*/
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0>; /*pixel_clk(unit in Hz)*/
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lvds_attr = <
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1 /*lvds_repack*/
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1 /*dual_port*/
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0 /*pn_swap*/
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0 /*port_swap*/
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0>; /*lane_reverse*/
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phy_attr=<0xf 0>; /*vswing_level, preem_level*/
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/* power step: type, index, value, delay(ms) */
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power_on_step = <
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2 0 0 0 /*signal enable*/
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0xff 0 0 0>; /*ending*/
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power_off_step = <
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2 0 0 10 /*signal disable*/
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0xff 0 0 0>; /*ending*/
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backlight_index = <0xff>;
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};
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vbyone_0{
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model_name = "public_2region";
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interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
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basic_setting = <
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3840 2160 /*h_active, v_active*/
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4400 2250 /*h_period, v_period*/
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10 /*lcd_bits */
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16 9>; /*screen_widht, screen_height*/
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range_setting = <
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4240 4800 /*h_period_min, max*/
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2200 2760 /*v_period_min, max*/
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480000000 624000000>; /*pclk_min, max*/
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lcd_timing = <
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33 477 0 /*hs_width, hs_bp, hs_pol*/
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6 65 0>; /*vs_width, vs_bp, vs_pol*/
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clk_attr = <
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2 /*fr_adj_type
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*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
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* 4=hdmi_mode)
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*/
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0 /*clk_ss_level*/
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1 /*clk_auto_generate*/
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0>; /*pixel_clk(unit in Hz)*/
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vbyone_attr = <
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8 /*lane_count*/
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2 /*region_num*/
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4 /*byte_mode*/
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4>; /*color_fmt*/
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vbyone_intr_enable = <
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1 /*vbyone_intr_enable */
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3>; /*vbyone_vsync_intr_enable*/
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phy_attr=<0xf 1>; /* vswing_level, preem_level */
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/* power step: type, index, value, delay(ms) */
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power_on_step = <
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2 0 0 10 /*signal enable*/
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0xff 0 0 0>; /*ending*/
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power_off_step = <
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2 0 0 10 /*signal disable*/
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0xff 0 0 0>; /*ending*/
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backlight_index = <0xff>;
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};
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vbyone_1{
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model_name = "public_1region";
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interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
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basic_setting = <
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3840 2160 /*h_active, v_active*/
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4400 2250 /*h_period, v_period*/
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10 /*lcd_bits*/
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16 9>; /*screen_widht, screen_height*/
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range_setting = <
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4240 4800 /*h_period_min, max*/
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2200 2790 /*v_period_min, max*/
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552000000 632000000>; /*pclk_min,max*/
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lcd_timing = <
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33 477 0 /*hs_width, hs_bp, hs_pol*/
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6 65 0>; /*vs_width, vs_bp, vs_pol*/
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clk_attr = <
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2 /*fr_adj_type
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*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
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* 4=hdmi_mode)
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*/
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0 /*clk_ss_level*/
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1 /*clk_auto_generate*/
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0>; /*pixel_clk(unit in Hz)*/
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vbyone_attr = <
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8 /*lane_count*/
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1 /*region_num*/
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4 /*byte_mode*/
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4>; /*color_fmt*/
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vbyone_intr_enable = <
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1 /*vbyone_intr_enable*/
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3>; /*vbyone_vsync_intr_enable*/
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phy_attr=<0xf 1>; /* vswing_level, preem_level */
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/* power step: type, index, value, delay(ms) */
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power_on_step = <
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2 0 0 10 /*signal enable*/
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0xff 0 0 0>; /*ending*/
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power_off_step = <
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2 0 0 10 /*signal disable*/
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0xff 0 0 0>; /*ending*/
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backlight_index = <0xff>;
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};
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p2p_0{
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model_name = "p2p_ceds";
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interface = "p2p"; /*lcd_interface
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*(lvds, vbyone, minilvds, p2p)
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*/
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basic_setting = <
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3840 2160 /*h_active, v_active*/
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5000 2250 /*h_period, v_period*/
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8 /*lcd_bits */
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16 9>; /*screen_widht, screen_height*/
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range_setting = <
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4240 5100 /*h_period_min, max*/
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2200 2760 /*v_period_min, max*/
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480000000 624000000>; /*pclk_min, max*/
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lcd_timing = <
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16 29 0 /*hs_width, hs_bp, hs_pol*/
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6 65 0>; /*vs_width, vs_bp, vs_pol*/
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clk_attr = <
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2 /*fr_adj_type
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*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
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* 4=hdmi_mode)
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*/
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0 /*clk_ss_level*/
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1 /*clk_auto_generate*/
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0>; /*pixel_clk(unit in Hz)*/
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p2p_attr = <
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0x0 /* p2p_teyp:
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* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
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* 0x10=chpi, 0x11=cspi, 0x12=usit
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*/
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12 /* channel_num */
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0x76543210 /* channel_sel0 */
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0xba98 /* channel_sel1 */
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0 /* pn_swap */
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0>; /* bit_swap */
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phy_attr=<0xf 1>; /* vswing_level, preem_level */
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/* power step: type, index, value, delay(ms) */
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power_on_step = <
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2 0 0 10 /*signal enable*/
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0xff 0 0 0>; /*ending*/
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power_off_step = <
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2 0 0 10 /*signal disable*/
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0xff 0 0 0>; /*ending*/
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backlight_index = <0xff>;
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};
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p2p_1{
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model_name = "p2p_ceds";
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interface = "p2p"; /*lcd_interface
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*(lvds, vbyone, minilvds, p2p)
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*/
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basic_setting = <
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3840 2160 /*h_active, v_active*/
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5000 2250 /*h_period, v_period*/
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8 /*lcd_bits */
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16 9>; /*screen_widht, screen_height*/
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range_setting = <
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4240 5100 /*h_period_min, max*/
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2200 2760 /*v_period_min, max*/
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480000000 624000000>; /*pclk_min, max*/
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lcd_timing = <
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16 29 0 /*hs_width, hs_bp, hs_pol*/
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6 65 0>; /*vs_width, vs_bp, vs_pol*/
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clk_attr = <
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2 /*fr_adj_type
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*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
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* 4=hdmi_mode)
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*/
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0 /*clk_ss_level*/
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1 /*clk_auto_generate*/
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0>; /*pixel_clk(unit in Hz)*/
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p2p_attr = <
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0x0 /* p2p_teyp:
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* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
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* 0x10=chpi, 0x11=cspi, 0x12=usit
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*/
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6 /* channel_num */
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0x76543210 /* channel_sel0 */
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0xba98 /* channel_sel1 */
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0 /* pn_swap */
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0>; /* bit_swap */
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phy_attr=<0xf 1>; /* vswing_level, preem_level */
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/* power step: type, index, value, delay(ms) */
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power_on_step = <
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2 0 0 10 /*signal enable*/
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0xff 0 0 0>; /*ending*/
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power_off_step = <
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2 0 0 10 /*signal disable*/
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0xff 0 0 0>; /*ending*/
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backlight_index = <0xff>;
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};
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p2p_2{
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model_name = "p2p_chpi";
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interface = "p2p"; /*lcd_interface
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*(lvds, vbyone, minilvds, p2p)
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*/
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basic_setting = <
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3840 2160 /*h_active, v_active*/
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4400 2250 /*h_period, v_period*/
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8 /*lcd_bits */
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16 9>; /*screen_widht, screen_height*/
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range_setting = <
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4240 5100 /*h_period_min, max*/
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2200 2760 /*v_period_min, max*/
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480000000 624000000>; /*pclk_min, max*/
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lcd_timing = <
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16 29 0 /*hs_width, hs_bp, hs_pol*/
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6 65 0>; /*vs_width, vs_bp, vs_pol*/
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clk_attr = <
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2 /*fr_adj_type
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*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
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* 4=hdmi_mode)
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*/
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0 /*clk_ss_level*/
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1 /*clk_auto_generate*/
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0>; /*pixel_clk(unit in Hz)*/
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p2p_attr = <
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0x10 /* p2p_teyp:
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* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
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* 0x10=chpi, 0x11=cspi, 0x12=usit
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*/
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6 /* channel_num */
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0x76543210 /* channel_sel0 */
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0xba98 /* channel_sel1 */
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0 /* pn_swap */
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0>; /* bit_swap */
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phy_attr=<0xf 1>; /* vswing_level, preem_level */
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/* power step: type, index, value, delay(ms) */
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power_on_step = <
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2 0 0 10 /*signal enable*/
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0xff 0 0 0>; /*ending*/
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power_off_step = <
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2 0 0 10 /*signal disable*/
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0xff 0 0 0>; /*ending*/
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backlight_index = <0xff>;
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};
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p2p_3{
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model_name = "p2p_chpi";
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interface = "p2p"; /*lcd_interface
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*(lvds, vbyone, minilvds, p2p)
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*/
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basic_setting = <
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3840 2160 /*h_active, v_active*/
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4400 2250 /*h_period, v_period*/
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8 /*lcd_bits */
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16 9>; /*screen_widht, screen_height*/
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range_setting = <
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4240 5100 /*h_period_min, max*/
|
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2200 2760 /*v_period_min, max*/
|
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480000000 624000000>; /*pclk_min, max*/
|
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lcd_timing = <
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16 29 0 /*hs_width, hs_bp, hs_pol*/
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6 65 0>; /*vs_width, vs_bp, vs_pol*/
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clk_attr = <
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2 /*fr_adj_type
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*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
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* 4=hdmi_mode)
|
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*/
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0 /*clk_ss_level*/
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1 /*clk_auto_generate*/
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0>; /*pixel_clk(unit in Hz)*/
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p2p_attr = <
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0x10 /* p2p_teyp:
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* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
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* 0x10=chpi, 0x11=cspi, 0x12=usit
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*/
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12 /* channel_num */
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0x76543210 /* channel_sel0 */
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0xba98 /* channel_sel1 */
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0 /* pn_swap */
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0>; /* bit_swap */
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phy_attr=<0xf 1>; /* vswing_level, preem_level */
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/* power step: type, index, value, delay(ms) */
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power_on_step = <
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2 0 0 10 /*signal enable*/
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0xff 0 0 0>; /*ending*/
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power_off_step = <
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2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
mlvds_0{
|
||||
model_name = "mlvds_1080p";
|
||||
interface = "minilvds"; /*lcd_interface
|
||||
*(lvds, vbyone, minilvds, p2p)
|
||||
*/
|
||||
basic_setting = <
|
||||
1920 1080 /*h_active, v_active*/
|
||||
2200 1125 /*h_period, v_period*/
|
||||
8 /*lcd_bits */
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
2080 2720 /*h_period_min, max*/
|
||||
2200 1125 /*v_period_min, max*/
|
||||
133940000 156000000>; /*pclk_min, max*/
|
||||
lcd_timing = <
|
||||
44 148 0 /*hs_width, hs_bp, hs_pol*/
|
||||
5 30 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
minilvds_attr = <
|
||||
6 /* channel_num */
|
||||
0x76543210 /* channel_sel0 */
|
||||
0xba98 /* channel_sel1 */
|
||||
0x660 /* clk_phase */
|
||||
0 /* pn_swap */
|
||||
0>; /* bit_swap */
|
||||
phy_attr=<0xf 0>; /* vswing_level, preem_level */
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 10 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
mlvds_1{
|
||||
model_name = "mlvds_768p";
|
||||
interface = "minilvds";/*lcd_interface
|
||||
*(lvds, vbyone, minilvds, p2p)
|
||||
*/
|
||||
basic_setting = <
|
||||
1366 768 /*h_active, v_active*/
|
||||
1560 806 /*h_period, v_period*/
|
||||
8 /*lcd_bits */
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
1460 2000 /*h_period_min, max*/
|
||||
784 1015 /*v_period_min, max*/
|
||||
50000000 85000000>; /*pclk_min, max*/
|
||||
lcd_timing = <
|
||||
56 64 0 /*hs_width, hs_bp, hs_pol*/
|
||||
3 28 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
minilvds_attr = <
|
||||
6 /* channel_num */
|
||||
0x76543210 /* channel_sel0 */
|
||||
0xba98 /* channel_sel1 */
|
||||
0x660 /* clk_phase */
|
||||
0 /* pn_swap */
|
||||
0>; /* bit_swap */
|
||||
phy_attr=<0xf 0>; /* vswing_level, preem_level */
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 10 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd_extern{
|
||||
compatible = "amlogic, lcd_extern";
|
||||
status = "okay";
|
||||
key_valid = <0>;
|
||||
i2c_bus = "i2c_bus_1";
|
||||
|
||||
extern_0{
|
||||
index = <0>;
|
||||
extern_name = "ext_default";
|
||||
status = "disabled";
|
||||
type = <0>; /*0=i2c, 1=spi, 2=mipi*/
|
||||
i2c_address = <0x1c>; /*7bit i2c_addr*/
|
||||
i2c_address2 = <0xff>;
|
||||
cmd_size = <0xff>; /*dynamic cmd_size*/
|
||||
|
||||
/* init on/off:
|
||||
* fixed cmd_size: (type, value...);
|
||||
* cmd_size include all data.
|
||||
* dynamic cmd_size: (type, cmd_size, value...);
|
||||
* cmd_size include value.
|
||||
*/
|
||||
/* type: 0x00=cmd with delay(bit[3:0]=1 for address2),
|
||||
* 0xc0=cmd(bit[3:0]=1 for address2),
|
||||
* 0xf0=gpio,
|
||||
* 0xfd=delay,
|
||||
* 0xff=ending
|
||||
*/
|
||||
/* value: i2c or spi cmd, or gpio index & level */
|
||||
/* delay: unit ms */
|
||||
init_on = <
|
||||
0xc0 7 0x20 0x01 0x02 0x00 0x40 0xFF 0x00
|
||||
0xc0 7 0x80 0x02 0x00 0x40 0x62 0x51 0x73
|
||||
0xc0 7 0x61 0x06 0x00 0x00 0x00 0x00 0x00
|
||||
0xc0 7 0xC1 0x05 0x0F 0x00 0x08 0x70 0x00
|
||||
0xc0 7 0x13 0x01 0x00 0x00 0x00 0x00 0x00
|
||||
0xc0 7 0x3D 0x02 0x01 0x00 0x00 0x00 0x00
|
||||
0xc0 7 0xED 0x0D 0x01 0x00 0x00 0x00 0x00
|
||||
0xc0 7 0x23 0x02 0x00 0x00 0x00 0x00 0x00
|
||||
0xfd 1 10 /* delay 10ms */
|
||||
0xff 0>; /*ending*/
|
||||
init_off = <0xff 0>; /*ending*/
|
||||
};
|
||||
extern_1{
|
||||
index = <1>;
|
||||
extern_name = "i2c_T5800Q";
|
||||
status = "disabled";
|
||||
type = <0>; /* 0=i2c, 1=spi, 2=mipi */
|
||||
i2c_address = <0x1c>; /* 7bit i2c address */
|
||||
};
|
||||
extern_2{
|
||||
index = <2>;
|
||||
extern_name = "i2c_ANX6862_7911";
|
||||
status = "okay";
|
||||
type = <0>; /* 0=i2c, 1=spi, 2=mipi */
|
||||
i2c_address = <0x20>; /* 7bit i2c address */
|
||||
i2c_address2 = <0x74>; /* 7bit i2c address */
|
||||
cmd_size = <0xff>;
|
||||
|
||||
init_on = <
|
||||
0xc0 2 0x01 0x2b
|
||||
0xc0 2 0x02 0x05
|
||||
0xc0 2 0x03 0x00
|
||||
0xc0 2 0x04 0x00
|
||||
0xc0 2 0x05 0x0c
|
||||
0xc0 2 0x06 0x04
|
||||
0xc0 2 0x07 0x21
|
||||
0xc0 2 0x08 0x0f
|
||||
0xc0 2 0x09 0x04
|
||||
0xc0 2 0x0a 0x00
|
||||
0xc0 2 0x0b 0x04
|
||||
0xc0 2 0xff 0x00
|
||||
0xfd 1 100 /* delay 100ms */
|
||||
|
||||
0xc1 2 0x01 0xca
|
||||
0xc1 2 0x02 0x3b
|
||||
0xc1 2 0x03 0x33
|
||||
0xc1 2 0x04 0x05
|
||||
0xc1 2 0x05 0x2c
|
||||
0xc1 2 0x06 0xf2
|
||||
0xc1 2 0x07 0x9c
|
||||
0xc1 2 0x08 0x1b
|
||||
0xc1 2 0x09 0x82
|
||||
0xc1 2 0x0a 0x3d
|
||||
0xc1 2 0x0b 0x20
|
||||
0xc1 2 0x0c 0x11
|
||||
0xc1 2 0x0d 0xc4
|
||||
0xc1 2 0x0e 0x1a
|
||||
0xc1 2 0x0f 0x31
|
||||
0xc1 2 0x10 0x4c
|
||||
0xc1 2 0x11 0x12
|
||||
0xc1 2 0x12 0x90
|
||||
0xc1 2 0x13 0xf7
|
||||
0xc1 2 0x14 0x0c
|
||||
0xc1 2 0x15 0x20
|
||||
0xc1 2 0x16 0x13
|
||||
0xff 0>; /*ending*/
|
||||
init_off = <0xff 0>; /*ending*/
|
||||
};
|
||||
};
|
||||
|
||||
}; /* end of / */
|
||||
@@ -19,6 +19,7 @@
|
||||
|
||||
#include "mesontm2.dtsi"
|
||||
#include "partition_mbox_normal.dtsi"
|
||||
#include "mesontm2_t962x3_ab301-panel.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Amlogic TM2 T962X3 AB301";
|
||||
@@ -1869,6 +1870,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm_cd {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
|
||||
#include "mesontm2.dtsi"
|
||||
#include "partition_mbox_normal.dtsi"
|
||||
#include "mesontm2_t962x3_ab309-panel.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Amlogic TM2 T962X3 AB309";
|
||||
|
||||
1066
arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi
Normal file
1066
arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
589
arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
Normal file
589
arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
Normal file
@@ -0,0 +1,589 @@
|
||||
/*
|
||||
* arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
|
||||
*
|
||||
* Copyright (C) 2018 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
lcd {
|
||||
compatible = "amlogic, lcd-tm2";
|
||||
status = "okay";
|
||||
mode = "tv";
|
||||
fr_auto_policy = <0>; /* 0=disable, 1=60/50hz, 2=60/50/48hz */
|
||||
key_valid = <0>;
|
||||
clocks = <&clkc CLKID_VCLK2_ENCL
|
||||
&clkc CLKID_VCLK2_VENCL
|
||||
&clkc CLKID_TCON
|
||||
&clkc CLKID_FCLK_DIV5
|
||||
&clkc CLKID_TCON_PLL_COMP>;
|
||||
clock-names = "encl_top_gate",
|
||||
"encl_int_gate",
|
||||
"tcon_gate",
|
||||
"fclk_div5",
|
||||
"clk_tcon";
|
||||
reg = <0x0 0xff660000 0x0 0x8100
|
||||
0x0 0xff634400 0x0 0x300>;
|
||||
interrupts = <0 3 1
|
||||
0 78 1
|
||||
0 88 1>;
|
||||
interrupt-names = "vsync","vbyone","tcon";
|
||||
pinctrl-names = "vbyone","vbyone_off","tcon","tcon_off";
|
||||
pinctrl-0 = <&lcd_vbyone_pins>;
|
||||
pinctrl-1 = <&lcd_vbyone_off_pins>;
|
||||
pinctrl-2 = <&lcd_tcon_pins>;
|
||||
pinctrl-3 = <&lcd_tcon_off_pins>;
|
||||
pinctrl_version = <2>; /* for uboot */
|
||||
|
||||
/* power type:(0=cpu_gpio, 2=signal, 3=extern, 0xff=ending) */
|
||||
/* power index:(gpios_index, or extern_index, 0xff=invalid) */
|
||||
/* power value:(0=output low, 1=output high, 2=input) */
|
||||
/* power delay:(unit in ms) */
|
||||
|
||||
lvds_0{
|
||||
model_name = "1080p-vfreq";
|
||||
interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
|
||||
basic_setting = <
|
||||
1920 1080 /*h_active, v_active*/
|
||||
2200 1125 /*h_period, v_period*/
|
||||
8 /*lcd_bits */
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
2060 2650 /*h_period_min,max*/
|
||||
1100 1480 /*v_period_min,max*/
|
||||
120000000 160000000>; /*pclk_min,max*/
|
||||
lcd_timing = <
|
||||
44 148 0 /*hs_width, hs_bp, hs_pol*/
|
||||
5 30 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
lvds_attr = <
|
||||
1 /*lvds_repack*/
|
||||
1 /*dual_port*/
|
||||
0 /*pn_swap*/
|
||||
0 /*port_swap*/
|
||||
0>; /*lane_reverse*/
|
||||
phy_attr=<0xf 0>; /*vswing_level, preem_level*/
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 0 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
lvds_1{
|
||||
model_name = "1080p-hfreq_hdmi";
|
||||
interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
|
||||
basic_setting = <
|
||||
1920 1080 /*h_active, v_active*/
|
||||
2200 1125 /*h_period, v_period*/
|
||||
8 /*lcd_bits*/
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
2080 2720 /*h_period min, max*/
|
||||
1100 1380 /*v_period min, max*/
|
||||
133940000 156000000>; /*pclk_min, max*/
|
||||
lcd_timing = <
|
||||
44 148 0 /*hs_width, hs_bp, hs_pol*/
|
||||
5 30 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
4 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level */
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
lvds_attr = <
|
||||
1 /*lvds_repack*/
|
||||
1 /*dual_port*/
|
||||
0 /*pn_swap*/
|
||||
0 /*port_swap*/
|
||||
0>; /*lane_reverse*/
|
||||
phy_attr=<0xf 0>; /*vswing_level, preem_level*/
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 0 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
vbyone_0{
|
||||
model_name = "public_2region";
|
||||
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
|
||||
basic_setting = <
|
||||
3840 2160 /*h_active, v_active*/
|
||||
4400 2250 /*h_period, v_period*/
|
||||
10 /*lcd_bits */
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
4240 4800 /*h_period_min, max*/
|
||||
2200 2760 /*v_period_min, max*/
|
||||
480000000 624000000>; /*pclk_min, max*/
|
||||
lcd_timing = <
|
||||
33 477 0 /*hs_width, hs_bp, hs_pol*/
|
||||
6 65 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
vbyone_attr = <
|
||||
8 /*lane_count*/
|
||||
2 /*region_num*/
|
||||
4 /*byte_mode*/
|
||||
4>; /*color_fmt*/
|
||||
vbyone_intr_enable = <
|
||||
1 /*vbyone_intr_enable */
|
||||
3>; /*vbyone_vsync_intr_enable*/
|
||||
phy_attr=<0xf 1>; /* vswing_level, preem_level */
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 10 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
vbyone_1{
|
||||
model_name = "public_1region";
|
||||
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
|
||||
basic_setting = <
|
||||
3840 2160 /*h_active, v_active*/
|
||||
4400 2250 /*h_period, v_period*/
|
||||
10 /*lcd_bits*/
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
4240 4800 /*h_period_min, max*/
|
||||
2200 2790 /*v_period_min, max*/
|
||||
552000000 632000000>; /*pclk_min,max*/
|
||||
lcd_timing = <
|
||||
33 477 0 /*hs_width, hs_bp, hs_pol*/
|
||||
6 65 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
vbyone_attr = <
|
||||
8 /*lane_count*/
|
||||
1 /*region_num*/
|
||||
4 /*byte_mode*/
|
||||
4>; /*color_fmt*/
|
||||
vbyone_intr_enable = <
|
||||
1 /*vbyone_intr_enable*/
|
||||
3>; /*vbyone_vsync_intr_enable*/
|
||||
phy_attr=<0xf 1>; /* vswing_level, preem_level */
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 10 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
p2p_0{
|
||||
model_name = "p2p_ceds";
|
||||
interface = "p2p"; /*lcd_interface
|
||||
*(lvds, vbyone, minilvds, p2p)
|
||||
*/
|
||||
basic_setting = <
|
||||
3840 2160 /*h_active, v_active*/
|
||||
5000 2250 /*h_period, v_period*/
|
||||
8 /*lcd_bits */
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
4240 5100 /*h_period_min, max*/
|
||||
2200 2760 /*v_period_min, max*/
|
||||
480000000 624000000>; /*pclk_min, max*/
|
||||
lcd_timing = <
|
||||
16 29 0 /*hs_width, hs_bp, hs_pol*/
|
||||
6 65 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
p2p_attr = <
|
||||
0x0 /* p2p_teyp:
|
||||
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
|
||||
* 0x10=chpi, 0x11=cspi, 0x12=usit
|
||||
*/
|
||||
12 /* channel_num */
|
||||
0x76543210 /* channel_sel0 */
|
||||
0xba98 /* channel_sel1 */
|
||||
0 /* pn_swap */
|
||||
0>; /* bit_swap */
|
||||
phy_attr=<0xf 1>; /* vswing_level, preem_level */
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 10 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
p2p_1{
|
||||
model_name = "p2p_ceds";
|
||||
interface = "p2p"; /*lcd_interface
|
||||
*(lvds, vbyone, minilvds, p2p)
|
||||
*/
|
||||
basic_setting = <
|
||||
3840 2160 /*h_active, v_active*/
|
||||
5000 2250 /*h_period, v_period*/
|
||||
8 /*lcd_bits */
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
4240 5100 /*h_period_min, max*/
|
||||
2200 2760 /*v_period_min, max*/
|
||||
480000000 624000000>; /*pclk_min, max*/
|
||||
lcd_timing = <
|
||||
16 29 0 /*hs_width, hs_bp, hs_pol*/
|
||||
6 65 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
p2p_attr = <
|
||||
0x0 /* p2p_teyp:
|
||||
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
|
||||
* 0x10=chpi, 0x11=cspi, 0x12=usit
|
||||
*/
|
||||
6 /* channel_num */
|
||||
0x76543210 /* channel_sel0 */
|
||||
0xba98 /* channel_sel1 */
|
||||
0 /* pn_swap */
|
||||
0>; /* bit_swap */
|
||||
phy_attr=<0xf 1>; /* vswing_level, preem_level */
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 10 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
p2p_2{
|
||||
model_name = "p2p_chpi";
|
||||
interface = "p2p"; /*lcd_interface
|
||||
*(lvds, vbyone, minilvds, p2p)
|
||||
*/
|
||||
basic_setting = <
|
||||
3840 2160 /*h_active, v_active*/
|
||||
4400 2250 /*h_period, v_period*/
|
||||
8 /*lcd_bits */
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
4240 5100 /*h_period_min, max*/
|
||||
2200 2760 /*v_period_min, max*/
|
||||
480000000 624000000>; /*pclk_min, max*/
|
||||
lcd_timing = <
|
||||
16 29 0 /*hs_width, hs_bp, hs_pol*/
|
||||
6 65 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
p2p_attr = <
|
||||
0x10 /* p2p_teyp:
|
||||
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
|
||||
* 0x10=chpi, 0x11=cspi, 0x12=usit
|
||||
*/
|
||||
6 /* channel_num */
|
||||
0x76543210 /* channel_sel0 */
|
||||
0xba98 /* channel_sel1 */
|
||||
0 /* pn_swap */
|
||||
0>; /* bit_swap */
|
||||
phy_attr=<0xf 1>; /* vswing_level, preem_level */
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 10 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
p2p_3{
|
||||
model_name = "p2p_chpi";
|
||||
interface = "p2p"; /*lcd_interface
|
||||
*(lvds, vbyone, minilvds, p2p)
|
||||
*/
|
||||
basic_setting = <
|
||||
3840 2160 /*h_active, v_active*/
|
||||
4400 2250 /*h_period, v_period*/
|
||||
8 /*lcd_bits */
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
4240 5100 /*h_period_min, max*/
|
||||
2200 2760 /*v_period_min, max*/
|
||||
480000000 624000000>; /*pclk_min, max*/
|
||||
lcd_timing = <
|
||||
16 29 0 /*hs_width, hs_bp, hs_pol*/
|
||||
6 65 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
p2p_attr = <
|
||||
0x10 /* p2p_teyp:
|
||||
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
|
||||
* 0x10=chpi, 0x11=cspi, 0x12=usit
|
||||
*/
|
||||
12 /* channel_num */
|
||||
0x76543210 /* channel_sel0 */
|
||||
0xba98 /* channel_sel1 */
|
||||
0 /* pn_swap */
|
||||
0>; /* bit_swap */
|
||||
phy_attr=<0xf 1>; /* vswing_level, preem_level */
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 10 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
mlvds_0{
|
||||
model_name = "mlvds_1080p";
|
||||
interface = "minilvds"; /*lcd_interface
|
||||
*(lvds, vbyone, minilvds, p2p)
|
||||
*/
|
||||
basic_setting = <
|
||||
1920 1080 /*h_active, v_active*/
|
||||
2200 1125 /*h_period, v_period*/
|
||||
8 /*lcd_bits */
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
2080 2720 /*h_period_min, max*/
|
||||
2200 1125 /*v_period_min, max*/
|
||||
133940000 156000000>; /*pclk_min, max*/
|
||||
lcd_timing = <
|
||||
44 148 0 /*hs_width, hs_bp, hs_pol*/
|
||||
5 30 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
minilvds_attr = <
|
||||
6 /* channel_num */
|
||||
0x76543210 /* channel_sel0 */
|
||||
0xba98 /* channel_sel1 */
|
||||
0x660 /* clk_phase */
|
||||
0 /* pn_swap */
|
||||
0>; /* bit_swap */
|
||||
phy_attr=<0xf 0>; /* vswing_level, preem_level */
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 10 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
mlvds_1{
|
||||
model_name = "mlvds_768p";
|
||||
interface = "minilvds"; /*lcd_interface
|
||||
*(lvds, vbyone, minilvds, p2p)
|
||||
*/
|
||||
basic_setting = <
|
||||
1366 768 /*h_active, v_active*/
|
||||
1560 806 /*h_period, v_period*/
|
||||
8 /*lcd_bits */
|
||||
16 9>; /*screen_widht, screen_height*/
|
||||
range_setting = <
|
||||
1460 2000 /*h_period_min, max*/
|
||||
784 1015 /*v_period_min, max*/
|
||||
50000000 85000000>; /*pclk_min, max*/
|
||||
lcd_timing = <
|
||||
56 64 0 /*hs_width, hs_bp, hs_pol*/
|
||||
3 28 0>; /*vs_width, vs_bp, vs_pol*/
|
||||
clk_attr = <
|
||||
2 /*fr_adj_type
|
||||
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
|
||||
* 4=hdmi_mode)
|
||||
*/
|
||||
0 /*clk_ss_level*/
|
||||
1 /*clk_auto_generate*/
|
||||
0>; /*pixel_clk(unit in Hz)*/
|
||||
minilvds_attr = <
|
||||
6 /* channel_num */
|
||||
0x76543210 /* channel_sel0 */
|
||||
0xba98 /* channel_sel1 */
|
||||
0x660 /* clk_phase */
|
||||
0 /* pn_swap */
|
||||
0>; /* bit_swap */
|
||||
phy_attr=<0xf 0>; /* vswing_level, preem_level */
|
||||
|
||||
/* power step: type, index, value, delay(ms) */
|
||||
power_on_step = <
|
||||
2 0 0 10 /*signal enable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
power_off_step = <
|
||||
2 0 0 10 /*signal disable*/
|
||||
0xff 0 0 0>; /*ending*/
|
||||
backlight_index = <0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
lcd_extern{
|
||||
compatible = "amlogic, lcd_extern";
|
||||
status = "okay";
|
||||
key_valid = <0>;
|
||||
i2c_bus = "i2c_bus_1";
|
||||
|
||||
extern_0{
|
||||
index = <0>;
|
||||
extern_name = "ext_default";
|
||||
status = "disabled";
|
||||
type = <0>; /*0=i2c, 1=spi, 2=mipi*/
|
||||
i2c_address = <0x1c>; /*7bit i2c_addr*/
|
||||
i2c_address2 = <0xff>;
|
||||
cmd_size = <0xff>; /*dynamic cmd_size*/
|
||||
|
||||
/* init on/off:
|
||||
* fixed cmd_size: (type, value...);
|
||||
* cmd_size include all data.
|
||||
* dynamic cmd_size: (type, cmd_size, value...);
|
||||
* cmd_size include value.
|
||||
*/
|
||||
/* type: 0x00=cmd with delay(bit[3:0]=1 for address2),
|
||||
* 0xc0=cmd(bit[3:0]=1 for address2),
|
||||
* 0xf0=gpio,
|
||||
* 0xfd=delay,
|
||||
* 0xff=ending
|
||||
*/
|
||||
/* value: i2c or spi cmd, or gpio index & level */
|
||||
/* delay: unit ms */
|
||||
init_on = <
|
||||
0xc0 7 0x20 0x01 0x02 0x00 0x40 0xFF 0x00
|
||||
0xc0 7 0x80 0x02 0x00 0x40 0x62 0x51 0x73
|
||||
0xc0 7 0x61 0x06 0x00 0x00 0x00 0x00 0x00
|
||||
0xc0 7 0xC1 0x05 0x0F 0x00 0x08 0x70 0x00
|
||||
0xc0 7 0x13 0x01 0x00 0x00 0x00 0x00 0x00
|
||||
0xc0 7 0x3D 0x02 0x01 0x00 0x00 0x00 0x00
|
||||
0xc0 7 0xED 0x0D 0x01 0x00 0x00 0x00 0x00
|
||||
0xc0 7 0x23 0x02 0x00 0x00 0x00 0x00 0x00
|
||||
0xfd 1 10 /* delay 10ms */
|
||||
0xff 0>; /*ending*/
|
||||
init_off = <0xff 0>; /*ending*/
|
||||
};
|
||||
extern_1{
|
||||
index = <1>;
|
||||
extern_name = "i2c_T5800Q";
|
||||
status = "disabled";
|
||||
type = <0>; /* 0=i2c, 1=spi, 2=mipi */
|
||||
i2c_address = <0x1c>; /* 7bit i2c address */
|
||||
};
|
||||
extern_2{
|
||||
index = <2>;
|
||||
extern_name = "i2c_ANX6862_7911";
|
||||
status = "okay";
|
||||
type = <0>; /* 0=i2c, 1=spi, 2=mipi */
|
||||
i2c_address = <0x20>; /* 7bit i2c address */
|
||||
i2c_address2 = <0x74>; /* 7bit i2c address */
|
||||
cmd_size = <0xff>;
|
||||
|
||||
init_on = <
|
||||
0xc0 2 0x01 0x2b
|
||||
0xc0 2 0x02 0x05
|
||||
0xc0 2 0x03 0x00
|
||||
0xc0 2 0x04 0x00
|
||||
0xc0 2 0x05 0x0c
|
||||
0xc0 2 0x06 0x04
|
||||
0xc0 2 0x07 0x21
|
||||
0xc0 2 0x08 0x0f
|
||||
0xc0 2 0x09 0x04
|
||||
0xc0 2 0x0a 0x00
|
||||
0xc0 2 0x0b 0x04
|
||||
0xc0 2 0xff 0x00
|
||||
0xfd 1 100 /* delay 100ms */
|
||||
|
||||
0xc1 2 0x01 0xca
|
||||
0xc1 2 0x02 0x3b
|
||||
0xc1 2 0x03 0x33
|
||||
0xc1 2 0x04 0x05
|
||||
0xc1 2 0x05 0x2c
|
||||
0xc1 2 0x06 0xf2
|
||||
0xc1 2 0x07 0x9c
|
||||
0xc1 2 0x08 0x1b
|
||||
0xc1 2 0x09 0x82
|
||||
0xc1 2 0x0a 0x3d
|
||||
0xc1 2 0x0b 0x20
|
||||
0xc1 2 0x0c 0x11
|
||||
0xc1 2 0x0d 0xc4
|
||||
0xc1 2 0x0e 0x1a
|
||||
0xc1 2 0x0f 0x31
|
||||
0xc1 2 0x10 0x4c
|
||||
0xc1 2 0x11 0x12
|
||||
0xc1 2 0x12 0x90
|
||||
0xc1 2 0x13 0xf7
|
||||
0xc1 2 0x14 0x0c
|
||||
0xc1 2 0x15 0x20
|
||||
0xc1 2 0x16 0x13
|
||||
0xff 0>; /*ending*/
|
||||
init_off = <0xff 0>; /*ending*/
|
||||
};
|
||||
};
|
||||
|
||||
}; /* end of / */
|
||||
@@ -19,6 +19,7 @@
|
||||
|
||||
#include "mesontm2.dtsi"
|
||||
#include "partition_mbox_normal.dtsi"
|
||||
#include "mesontm2_t962x3_ab301-panel.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Amlogic TM2 T962X3 AB301";
|
||||
@@ -78,6 +79,14 @@
|
||||
alloc-ranges = <0x0 0x30000000 0x0 0x50000000>;
|
||||
};
|
||||
|
||||
lcd_tcon_reserved:linux,lcd_tcon {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x0 0xc00000>;
|
||||
alignment = <0x0 0x400000>;
|
||||
alloc-ranges = <0x0 0x7ec00000 0x0 0xc00000>;
|
||||
};
|
||||
|
||||
/* codec shared reserved */
|
||||
codec_mm_reserved:linux,codec_mm_reserved {
|
||||
compatible = "amlogic, codec-mm-reserved";
|
||||
@@ -1567,7 +1576,40 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
/*backlight*/
|
||||
bl_pwm_vs_on_pins:bl_pwm_vs_on_pin {
|
||||
mux {
|
||||
groups = "pwm_vs_z5";
|
||||
function = "pwm_vs";
|
||||
};
|
||||
};
|
||||
bl_pwm_off_pins:bl_pwm_off_pin {
|
||||
mux {
|
||||
groups = "GPIOZ_5";
|
||||
function = "gpio_periphs";
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
bl_pwm_combo_0_vs_on_pins:bl_pwm_combo_0_vs_on_pin {
|
||||
mux {
|
||||
groups = "pwm_vs_z5";
|
||||
function = "pwm_vs";
|
||||
};
|
||||
};
|
||||
bl_pwm_combo_1_vs_on_pins:bl_pwm_combo_1_vs_on_pin {
|
||||
mux {
|
||||
groups = "pwm_vs_z6";
|
||||
function = "pwm_vs";
|
||||
};
|
||||
};
|
||||
bl_pwm_combo_off_pins:bl_pwm_combo_off_pin {
|
||||
mux {
|
||||
groups = "GPIOZ_5",
|
||||
"GPIOZ_6";
|
||||
function = "gpio_periphs";
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
}; /* end of pinctrl_periphs */
|
||||
|
||||
&pinctrl_aobus {
|
||||
@@ -1753,6 +1795,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm_cd {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -19,9 +19,10 @@
|
||||
|
||||
#include "mesontm2.dtsi"
|
||||
#include "partition_mbox_normal.dtsi"
|
||||
#include "mesontm2_t962x3_ab309-panel.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Amlogic TM2 T962E2 AB319";
|
||||
model = "Amlogic TM2 T962X3 AB309";
|
||||
amlogic-dt-id = "tm2_t962x3_ab309";
|
||||
compatible = "amlogic, tm2_t962x3_ab309";
|
||||
|
||||
|
||||
@@ -3376,6 +3376,12 @@ static struct bl_data_s bl_data_sm1 = {
|
||||
.pwm_reg = pwm_reg_txlx,
|
||||
};
|
||||
|
||||
static struct bl_data_s bl_data_tm2 = {
|
||||
.chip_type = BL_CHIP_TM2,
|
||||
.chip_name = "tm2",
|
||||
.pwm_reg = pwm_reg_txlx,
|
||||
};
|
||||
|
||||
static const struct of_device_id bl_dt_match_table[] = {
|
||||
{
|
||||
.compatible = "amlogic, backlight-gxl",
|
||||
@@ -3413,6 +3419,10 @@ static const struct of_device_id bl_dt_match_table[] = {
|
||||
.compatible = "amlogic, backlight-sm1",
|
||||
.data = &bl_data_sm1,
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic, backlight-tm2",
|
||||
.data = &bl_data_tm2,
|
||||
},
|
||||
{},
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -3013,6 +3013,7 @@ int aml_ldim_probe(struct platform_device *pdev)
|
||||
/* ldim_op_func */
|
||||
switch (bl_drv->data->chip_type) {
|
||||
case BL_CHIP_TL1:
|
||||
case BL_CHIP_TM2:
|
||||
devp->ldim_op_func = &ldim_op_func_tl1;
|
||||
break;
|
||||
case BL_CHIP_TXLX:
|
||||
|
||||
@@ -2996,6 +2996,7 @@ static void lcd_clk_config_chip_init(struct lcd_clk_config_s *cConf)
|
||||
cConf->data = &lcd_clk_data_g12b_path0;
|
||||
break;
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
cConf->data = &lcd_clk_data_tl1;
|
||||
break;
|
||||
default:
|
||||
|
||||
@@ -606,6 +606,7 @@ static void lcd_reg_print_serializer(char *buf, int offset)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
reg0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
|
||||
reg1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
|
||||
break;
|
||||
@@ -4496,6 +4497,7 @@ int lcd_debug_probe(void)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
lcd_debug_info_reg = &lcd_debug_info_reg_tl1;
|
||||
lcd_debug_info_if_lvds.reg_dump_phy =
|
||||
lcd_reg_print_phy_analog_tl1;
|
||||
|
||||
@@ -115,6 +115,7 @@ void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
|
||||
sizeof(unsigned int);
|
||||
if (preem >= size) {
|
||||
@@ -180,6 +181,7 @@ void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
|
||||
} else {
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
|
||||
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
|
||||
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
|
||||
@@ -228,6 +230,7 @@ void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
|
||||
sizeof(unsigned int);
|
||||
if (preem >= size) {
|
||||
@@ -286,6 +289,7 @@ void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
|
||||
} else {
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
|
||||
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
|
||||
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
|
||||
|
||||
@@ -196,6 +196,7 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
/*[15:14]: 2'b10 or 2'b01*/
|
||||
lcd_vcbus_write(ENCL_INBUF_CNTL1, (2 << 14) | (h_active - 1));
|
||||
lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200);
|
||||
@@ -238,6 +239,7 @@ static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
|
||||
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
|
||||
break;
|
||||
@@ -258,6 +260,7 @@ static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
|
||||
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
|
||||
switch (lcd_drv->data->chip_type) { /* pn swap */
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
|
||||
break;
|
||||
default:
|
||||
@@ -326,6 +329,7 @@ static void lcd_lvds_control_set(struct lcd_config_s *pconf)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
lcd_vcbus_write(P2P_CH_SWAP0, 0x76543210);
|
||||
lcd_vcbus_write(P2P_CH_SWAP1, 0xba98);
|
||||
break;
|
||||
@@ -366,6 +370,7 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
|
||||
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
|
||||
break;
|
||||
@@ -398,6 +403,7 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
|
||||
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
|
||||
switch (lcd_drv->data->chip_type) { /* pn swap */
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
|
||||
break;
|
||||
default:
|
||||
@@ -600,6 +606,7 @@ static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_L, 0xff);
|
||||
lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_H, 0x0);
|
||||
lcd_vcbus_setb(VBO_INSGN_CTRL, 0x7, 8, 4);
|
||||
|
||||
@@ -706,6 +706,7 @@ int lcd_tcon_probe(struct aml_lcd_drv_s *lcd_drv)
|
||||
lcd_tcon_data = NULL;
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
switch (lcd_drv->lcd_config->lcd_basic.lcd_type) {
|
||||
case LCD_MLVDS:
|
||||
case LCD_P2P:
|
||||
|
||||
@@ -181,6 +181,7 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
/*[15:14]: 2'b10 or 2'b01*/
|
||||
lcd_vcbus_write(ENCL_INBUF_CNTL1, (2 << 14) | (h_active - 1));
|
||||
lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200);
|
||||
@@ -210,6 +211,7 @@ static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
|
||||
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
|
||||
break;
|
||||
@@ -230,6 +232,7 @@ static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
|
||||
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
|
||||
switch (lcd_drv->data->chip_type) { /* pn swap */
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
|
||||
break;
|
||||
default:
|
||||
@@ -298,6 +301,7 @@ static void lcd_lvds_control_set(struct lcd_config_s *pconf)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
lcd_vcbus_write(P2P_CH_SWAP0, 0x76543210);
|
||||
lcd_vcbus_write(P2P_CH_SWAP1, 0xba98);
|
||||
break;
|
||||
@@ -396,6 +400,7 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
|
||||
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
|
||||
break;
|
||||
@@ -428,6 +433,7 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
|
||||
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
|
||||
switch (lcd_drv->data->chip_type) { /* pn swap */
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
|
||||
break;
|
||||
default:
|
||||
@@ -516,6 +522,7 @@ static void lcd_vbyone_hw_filter(int flag)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
if (flag) {
|
||||
lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_L, 0xffff);
|
||||
lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_H, 0xf);
|
||||
@@ -1212,6 +1219,7 @@ static void lcd_p2p_control_set(struct lcd_config_s *pconf)
|
||||
|
||||
switch (lcd_drv->data->chip_type) {
|
||||
case LCD_CHIP_TL1:
|
||||
case LCD_CHIP_TM2:
|
||||
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
|
||||
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
|
||||
break;
|
||||
|
||||
@@ -1371,6 +1371,12 @@ static struct lcd_data_s lcd_data_sm1 = {
|
||||
.reg_map_table = &lcd_reg_axg[0],
|
||||
};
|
||||
|
||||
static struct lcd_data_s lcd_data_tm2 = {
|
||||
.chip_type = LCD_CHIP_TM2,
|
||||
.chip_name = "tm2",
|
||||
.reg_map_table = &lcd_reg_tl1[0],
|
||||
};
|
||||
|
||||
static const struct of_device_id lcd_dt_match_table[] = {
|
||||
{
|
||||
.compatible = "amlogic, lcd-gxl",
|
||||
@@ -1408,6 +1414,10 @@ static const struct of_device_id lcd_dt_match_table[] = {
|
||||
.compatible = "amlogic, lcd-sm1",
|
||||
.data = &lcd_data_sm1,
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic, lcd-tm2",
|
||||
.data = &lcd_data_tm2,
|
||||
},
|
||||
{},
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -51,6 +51,7 @@ enum bl_chip_type_e {
|
||||
BL_CHIP_G12B,
|
||||
BL_CHIP_TL1,
|
||||
BL_CHIP_SM1,
|
||||
BL_CHIP_TM2,
|
||||
BL_CHIP_MAX,
|
||||
};
|
||||
|
||||
|
||||
@@ -93,6 +93,7 @@ enum lcd_chip_e {
|
||||
LCD_CHIP_G12B, /* 6 */
|
||||
LCD_CHIP_TL1, /* 7 */
|
||||
LCD_CHIP_SM1, /* 8 */
|
||||
LCD_CHIP_TM2, /* 9 */
|
||||
LCD_CHIP_MAX,
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user