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Merge commit 'ce5da098c4cd46deb075845111383d9fd34afa7a'

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* commit 'ce5da098c4cd46deb075845111383d9fd34afa7a': (27 commits)
  drm/rockchip: vop2: update rk3568 max height limit
  drm/rockchip: lvds: update MEDIA_BUS_FMT_RGB666_1X7X3_SPWG description
  mmc: sdhci-of-dwcmshc: support HS400ES for RK3568
  Revert "arm64: rockchip_defconfig: enable CONFIG_ROCKCHIP_DRM_CUBIC_LUT"
  Revert "FROMLIST: drm: Extend color correction to support 3D-CLU"
  drm/rockchip: vop2: move cubic lut to rockchip drm driver
  media: i2c: add ar0822 driver
  media: i2c: max96722: version 1.00.00
  video: rockchip: rga3: add mm_flag 'RGA_MEM_FORCE_FLUSH_CACHE'
  arm64: dts: rockchip: rk3528 boards: btsco enable 16k pcm support
  arm64: dts: rockchip: rk356x boards: btsco enable 16k pcm support
  arm64: dts: rockchip: rk3588 boards: btsco enable 16k pcm support
  arm64: dts: rockchip: rk3562-evb: enable logo display for rgb board
  nvme-pci: add NVME_QUIRK_LIMIT_IOQD32 to fix Phison E15 NVMe controller
  video: rockchip: mpp: fix crash issue when no iommu
  soc: rockchip: mtd_vendor_storage: force config spi nor erase size to 64KB
  PCI: rockchip: dw_ep: Delaying the link training after hot reset
  video: rockchip: rga3: adapt to kernel-6.1/5.10/4.19
  ARM: dts: rockchip: rmii_phy use increment 0 for rv1106-evb
  arm64: dts: rockchip: rk3588: Add opp-info support
  ...

Conflicts:
	drivers/gpu/drm/drm_atomic_helper.c
	drivers/media/i2c/Kconfig
	drivers/media/i2c/Makefile
	drivers/media/i2c/max96722.c
	drivers/nvme/host/pci.c
	drivers/pci/controller/dwc/pcie-dw-rockchip.c

Ignore:
	commit 49520417ba ("PCIe: dw: rockchip: Disabled BAR0 and BAR1").

Change-Id: I41d947eda90f8b547ef2af30c3b093f556521803
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang
2023-06-28 10:17:44 +08:00
parent 7abaac5a04 ce5da098c4
commit 1ce4377b68
43 changed files with 7069 additions and 549 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/rv1106-evb.dtsi
View File

@@ -72,6 +72,10 @@
status = "okay";
};
&rmii_phy {
bgs,increment = <0>;
};
&rng {
status = "okay";
};

2
arch/arm/boot/dts/rv1106.dtsi
View File

@@ -1014,6 +1014,8 @@
#size-cells = <0>;
clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk";
assigned-clocks = <&cru CLK_SPI1>;
assigned-clock-rates = <200000000>;
dmas = <&dmac 3>, <&dmac 2>;
dma-names = "tx", "rx";
pinctrl-names = "default";

4
arch/arm64/boot/dts/rockchip/rk3528-demo.dtsi
View File

@@ -43,7 +43,7 @@
bt_sco: bt-sco {
status = "disabled";
compatible = "delta,dfbmcs320";
#sound-dai-cells = <0>;
#sound-dai-cells = <1>;
};
bt_sound: bt-sound {
@@ -57,7 +57,7 @@
sound-dai = <&sai0>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco>;
sound-dai = <&bt_sco 1>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3528-evb.dtsi
View File

@@ -42,7 +42,7 @@
bt_sco: bt-sco {
status = "disabled";
compatible = "delta,dfbmcs320";
#sound-dai-cells = <0>;
#sound-dai-cells = <1>;
};
bt_sound: bt-sound {
@@ -56,7 +56,7 @@
sound-dai = <&sai0>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco>;
sound-dai = <&bt_sco 1>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts
View File

@@ -19,6 +19,7 @@
#size-cells = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_gpio_pins>;
spi-delay-us = <10>;
status = "okay";
sck-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
@@ -44,6 +45,7 @@
disable-delay-ms = <20>;
width-mm = <217>;
height-mm = <136>;
rockchip,cmd-type = "spi";
status = "okay";
// type:0 is cmd, 1 is data
@@ -235,7 +237,7 @@
};
&route_rgb {
status = "disabled";
status = "okay";
connect = <&vp0_out_rgb>;
};

4
arch/arm64/boot/dts/rockchip/rk3566-box.dtsi
View File

@@ -35,7 +35,7 @@
bt_sco: bt-sco {
status = "disabled";
compatible = "delta,dfbmcs320";
#sound-dai-cells = <0>;
#sound-dai-cells = <1>;
};
bt_sound: bt-sound {
@@ -49,7 +49,7 @@
sound-dai = <&i2s2_2ch>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco>;
sound-dai = <&bt_sco 1>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi
View File

@@ -144,7 +144,7 @@
bt_sco: bt-sco {
status = "disabled";
compatible = "delta,dfbmcs320";
#sound-dai-cells = <0>;
#sound-dai-cells = <1>;
};
bt_sound: bt-sound {
@@ -158,7 +158,7 @@
sound-dai = <&i2s3_2ch>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco>;
sound-dai = <&bt_sco 1>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
View File

@@ -87,7 +87,7 @@
bt_sco: bt-sco {
status = "disabled";
compatible = "delta,dfbmcs320";
#sound-dai-cells = <0>;
#sound-dai-cells = <1>;
};
bt_sound: bt-sound {
@@ -101,7 +101,7 @@
sound-dai = <&i2s2_2ch>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco>;
sound-dai = <&bt_sco 1>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi
View File

@@ -85,7 +85,7 @@
bt_sco: bt-sco {
status = "disabled";
compatible = "delta,dfbmcs320";
#sound-dai-cells = <0>;
#sound-dai-cells = <1>;
};
bt_sound: bt-sound {
@@ -99,7 +99,7 @@
sound-dai = <&i2s2_2ch>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco>;
sound-dai = <&bt_sco 1>;
};
};

52
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -642,8 +642,8 @@
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpul_leakage>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "specification_serial_number";
nvmem-cells = <&cpul_leakage>, <&cpul_opp_info>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
rockchip,supported-hw;
rockchip,opp-shared-dsu;
@@ -813,8 +813,8 @@
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpub0_leakage>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "specification_serial_number";
nvmem-cells = <&cpub0_leakage>, <&cpub01_opp_info>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
rockchip,supported-hw;
rockchip,pvtm-voltage-sel = <
@@ -1026,8 +1026,8 @@
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpub1_leakage>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "specification_serial_number";
nvmem-cells = <&cpub1_leakage>, <&cpub23_opp_info>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
rockchip,supported-hw;
rockchip,pvtm-voltage-sel = <
@@ -1379,8 +1379,8 @@
dmc_opp_table: dmc-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&log_leakage>;
nvmem-cell-names = "leakage";
nvmem-cells = <&log_leakage>, <&dmc_opp_info>;
nvmem-cell-names = "leakage", "opp-info";
rockchip,leakage-voltage-sel = <
1 31 0
32 44 1
@@ -1908,8 +1908,8 @@
gpu_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&gpu_leakage>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "specification_serial_number";
nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
rockchip,supported-hw;
rockchip,pvtm-voltage-sel = <
@@ -2897,8 +2897,8 @@
npu_opp_table: npu-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&npu_leakage>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "specification_serial_number";
nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
rockchip,supported-hw;
rockchip,pvtm-voltage-sel = <
@@ -3498,8 +3498,8 @@
venc_opp_table: venc-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&codec_leakage>;
nvmem-cell-names = "leakage";
nvmem-cells = <&codec_leakage>, <&venc_opp_info>;
nvmem-cell-names = "leakage", "opp-info";
rockchip,leakage-voltage-sel = <
1 8 0
9 20 1
@@ -5907,6 +5907,30 @@
codec_leakage: codec-leakage@29 {
reg = <0x29 0x1>;
};
cpul_opp_info: cpul-opp-info@3d {
reg = <0x3d 0x6>;
};
cpub01_opp_info: cpub01-opp-info@43 {
reg = <0x43 0x6>;
};
cpub23_opp_info: cpub23-opp-info@49 {
reg = <0x49 0x6>;
};
gpu_opp_info: gpu-opp-info@4f {
reg = <0x4f 0x6>;
};
npu_opp_info: npu-opp-info@55 {
reg = <0x55 0x6>;
};
dmc_opp_info: dmc-opp-info@5b {
reg = <0x5b 0x6>;
};
vop_opp_info: vop-opp-info@61 {
reg = <0x61 0x6>;
};
venc_opp_info: venc-opp-info@67 {
reg = <0x67 0x6>;
};
};
mailbox2: mailbox@fece0000 {

1
arch/arm64/configs/rockchip_defconfig
View File

@@ -619,7 +619,6 @@ CONFIG_DRM_IGNORE_IOTCL_PERMIT=y
CONFIG_DRM_DP_AUX_CHARDEV=y
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_ROCKCHIP_DRM_CUBIC_LUT=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DRM_TVE=y

4
drivers/clk/rockchip/clk-rk3399.c
View File

@@ -651,9 +651,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
RK3399_CLKGATE_CON(5), 6, GFLAGS),
GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
RK3399_CLKGATE_CON(5), 7, GFLAGS),
GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
RK3399_CLKGATE_CON(5), 6, GFLAGS),
GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
RK3399_CLKGATE_CON(5), 8, GFLAGS),
GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,

7
drivers/gpu/drm/drm_atomic_state_helper.c
View File

@@ -143,10 +143,6 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc,
drm_property_blob_get(state->ctm);
if (state->gamma_lut)
drm_property_blob_get(state->gamma_lut);
#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
if (state->cubic_lut)
drm_property_blob_get(state->cubic_lut);
#endif
state->mode_changed = false;
state->active_changed = false;
state->planes_changed = false;
@@ -219,9 +215,6 @@ void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state)
drm_property_blob_put(state->degamma_lut);
drm_property_blob_put(state->ctm);
drm_property_blob_put(state->gamma_lut);
#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
drm_property_blob_put(state->cubic_lut);
#endif
}
EXPORT_SYMBOL(__drm_atomic_helper_crtc_destroy_state);

14
drivers/gpu/drm/drm_atomic_uapi.c
View File

@@ -438,16 +438,6 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
} else if (property == config->cubic_lut_property) {
ret = drm_atomic_replace_property_blob_from_id(dev,
&state->cubic_lut,
val,
-1, sizeof(struct drm_color_lut),
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
#endif
} else if (property == config->prop_out_fence_ptr) {
s32 __user *fence_ptr = u64_to_user_ptr(val);
@@ -493,10 +483,6 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
*val = (state->ctm) ? state->ctm->base.id : 0;
else if (property == config->gamma_lut_property)
*val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
else if (property == config->cubic_lut_property)
*val = (state->cubic_lut) ? state->cubic_lut->base.id : 0;
#endif
else if (property == config->prop_out_fence_ptr)
*val = 0;
else if (property == crtc->scaling_filter_property)

44
drivers/gpu/drm/drm_color_mgmt.c
View File

@@ -34,7 +34,7 @@
/**
* DOC: overview
*
* Color management or color space adjustments is supported through a set of 7
* Color management or color space adjustments is supported through a set of 5
* properties on the &drm_crtc object. They are set up by calling
* drm_crtc_enable_color_mgmt().
*
@@ -61,7 +61,7 @@
* “CTM”:
* Blob property to set the current transformation matrix (CTM) apply to
* pixel data after the lookup through the degamma LUT and before the
* lookup through the cubic LUT. The data is interpreted as a struct
* lookup through the gamma LUT. The data is interpreted as a struct
* &drm_color_ctm.
*
* Setting this to NULL (blob property value set to 0) means a
@@ -69,40 +69,13 @@
* boot-up state too. Drivers can access the blob for the color conversion
* matrix through &drm_crtc_state.ctm.
*
* ”CUBIC_LUT”:
* Blob property to set the cubic (3D) lookup table performing color
* mapping after the transformation matrix and before the lookup through
* the gamma LUT. Unlike the degamma and gamma LUTs that map color
* components independently, the 3D LUT converts an input color to an
* output color by indexing into the 3D table using the color components
* as a 3D coordinate. The LUT is subsampled as 8-bit (or more) precision
* would require too much storage space in the hardware, so the precision
* of the color components is reduced before the look up, and the low
* order bits may be used to interpolate between the nearest points in 3D
* space.
*
* The data is interpreted as an array of &struct drm_color_lut elements.
* Hardware might choose not to use the full precision of the LUT
* elements.
*
* Setting this to NULL (blob property value set to 0) means the output
* color is identical to the input color. This is generally the driver
* boot-up state too. Drivers can access this blob through
* &drm_crtc_state.cubic_lut.
*
* ”CUBIC_LUT_SIZE”:
* Unsigned range property to give the size of the lookup table to be set
* on the CUBIC_LUT property (the size depends on the underlying hardware).
* If drivers support multiple LUT sizes then they should publish the
* largest size, and sub-sample smaller sized LUTs appropriately.
*
* “GAMMA_LUT”:
* Blob property to set the gamma lookup table (LUT) mapping pixel data
* after the cubic LUT to data sent to the connector. The data is
* interpreted as an array of &struct drm_color_lut elements. Hardware
* might choose not to use the full precision of the LUT elements nor use
* all the elements of the LUT (for example the hardware might choose to
* interpolate between LUT[0] and LUT[4]).
* after the transformation matrix to data sent to the connector. The
* data is interpreted as an array of &struct drm_color_lut elements.
* Hardware might choose not to use the full precision of the LUT elements
* nor use all the elements of the LUT (for example the hardware might
* choose to interpolate between LUT[0] and LUT[4]).
*
* Setting this to NULL (blob property value set to 0) means a
* linear/pass-thru gamma table should be used. This is generally the
@@ -359,9 +332,6 @@ static int drm_crtc_legacy_gamma_set(struct drm_crtc *crtc,
replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL);
replaced |= drm_property_replace_blob(&crtc_state->gamma_lut,
use_gamma_lut ? blob : NULL);
#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
replaced |= drm_property_replace_blob(&crtc_state->cubic_lut, NULL);
#endif
crtc_state->color_mgmt_changed |= replaced;
ret = drm_atomic_commit(state);

16
drivers/gpu/drm/drm_mode_config.c
View File

@@ -365,22 +365,6 @@ static int drm_mode_create_standard_properties(struct drm_device *dev)
return -ENOMEM;
dev->mode_config.gamma_lut_size_property = prop;
#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
prop = drm_property_create(dev,
DRM_MODE_PROP_BLOB,
"CUBIC_LUT", 0);
if (!prop)
return -ENOMEM;
dev->mode_config.cubic_lut_property = prop;
prop = drm_property_create_range(dev,
DRM_MODE_PROP_IMMUTABLE,
"CUBIC_LUT_SIZE", 0, UINT_MAX);
if (!prop)
return -ENOMEM;
dev->mode_config.cubic_lut_size_property = prop;
#endif
prop = drm_property_create(dev,
DRM_MODE_PROP_IMMUTABLE | DRM_MODE_PROP_BLOB,
"IN_FORMATS", 0);

7
drivers/gpu/drm/rockchip/Kconfig
View File

@@ -21,13 +21,6 @@ config DRM_ROCKCHIP
if DRM_ROCKCHIP
config ROCKCHIP_DRM_CUBIC_LUT
bool "Support 3D cubic LUT"
depends on NO_GKI
help
This add properties to support provision of a 3D cubic
look up table, allowing for color specific adjustments.
config ROCKCHIP_DRM_DEBUG
bool "Rockchip DRM debug"
depends on DEBUG_FS

3
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View File

@@ -1345,6 +1345,9 @@ static int rockchip_drm_create_properties(struct drm_device *dev)
private->aclk_prop = drm_property_create_range(dev, 0, "ACLK", 0, UINT_MAX);
private->bg_prop = drm_property_create_range(dev, 0, "BACKGROUND", 0, UINT_MAX);
private->line_flag_prop = drm_property_create_range(dev, 0, "LINE_FLAG1", 0, UINT_MAX);
private->cubic_lut_prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, "CUBIC_LUT", 0);
private->cubic_lut_size_prop = drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE,
"CUBIC_LUT_SIZE", 0, UINT_MAX);
return drm_mode_create_tv_properties(dev, 0, NULL);
}

3
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View File

@@ -257,6 +257,7 @@ struct rockchip_crtc_state {
struct drm_property_blob *hdr_ext_data;
struct drm_property_blob *acm_lut_data;
struct drm_property_blob *post_csc_data;
struct drm_property_blob *cubic_lut_data;
int request_refresh_rate;
int max_refresh_rate;
@@ -455,6 +456,8 @@ struct rockchip_drm_private {
struct drm_property *aclk_prop;
struct drm_property *bg_prop;
struct drm_property *line_flag_prop;
struct drm_property *cubic_lut_prop;
struct drm_property *cubic_lut_size_prop;
/* private plane prop */
struct drm_property *eotf_prop;

46
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -3522,7 +3522,6 @@ static int vop2_crtc_atomic_gamma_set(struct drm_crtc *crtc,
return 0;
}
#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc,
struct drm_crtc_state *old_state)
{
@@ -3595,18 +3594,12 @@ static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc,
return 0;
}
static void drm_crtc_enable_cubic_lut(struct drm_crtc *crtc, unsigned int cubic_lut_size)
static void vop2_attach_cubic_lut_prop(struct drm_crtc *crtc, unsigned int cubic_lut_size)
{
struct drm_device *dev = crtc->dev;
struct drm_mode_config *config = &dev->mode_config;
struct rockchip_drm_private *private = crtc->dev->dev_private;
if (cubic_lut_size) {
drm_object_attach_property(&crtc->base,
config->cubic_lut_property, 0);
drm_object_attach_property(&crtc->base,
config->cubic_lut_size_property,
cubic_lut_size);
}
drm_object_attach_property(&crtc->base, private->cubic_lut_prop, 0);
drm_object_attach_property(&crtc->base, private->cubic_lut_size_prop, cubic_lut_size);
}
static void vop2_cubic_lut_init(struct vop2 *vop2)
@@ -3626,12 +3619,9 @@ static void vop2_cubic_lut_init(struct vop2 *vop2)
vp->cubic_lut_len = vp_data->cubic_lut_len;
if (vp->cubic_lut_len)
drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len);
vop2_attach_cubic_lut_prop(crtc, vp->cubic_lut_len);
}
}
#else
static void vop2_cubic_lut_init(struct vop2 *vop2) { }
#endif
static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
{
@@ -9756,13 +9746,11 @@ static void vop2_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_stat
vp->gamma_lut = crtc->state->gamma_lut->data;
vop2_crtc_atomic_gamma_set(crtc, crtc->state);
}
#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
if (crtc->state->cubic_lut || vp->cubic_lut) {
if (crtc->state->cubic_lut)
vp->cubic_lut = crtc->state->cubic_lut->data;
if (vcstate->cubic_lut_data || vp->cubic_lut) {
if (vcstate->cubic_lut_data)
vp->cubic_lut = vcstate->cubic_lut_data->data;
vop2_crtc_atomic_cubic_lut_set(crtc, crtc->state);
}
#endif
} else {
VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 0);
}
@@ -9875,6 +9863,8 @@ static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc)
drm_property_blob_get(vcstate->acm_lut_data);
if (vcstate->post_csc_data)
drm_property_blob_get(vcstate->post_csc_data);
if (vcstate->cubic_lut_data)
drm_property_blob_get(vcstate->cubic_lut_data);
__drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
return &vcstate->base;
@@ -9889,6 +9879,7 @@ static void vop2_crtc_destroy_state(struct drm_crtc *crtc,
drm_property_blob_put(vcstate->hdr_ext_data);
drm_property_blob_put(vcstate->acm_lut_data);
drm_property_blob_put(vcstate->post_csc_data);
drm_property_blob_put(vcstate->cubic_lut_data);
kfree(vcstate);
}
@@ -10035,6 +10026,11 @@ static int vop2_crtc_atomic_get_property(struct drm_crtc *crtc,
return 0;
}
if (property == private->cubic_lut_prop) {
*val = (vcstate->cubic_lut_data) ? vcstate->cubic_lut_data->base.id : 0;
return 0;
}
DRM_ERROR("failed to get vop2 crtc property: %s\n", property->name);
return -EINVAL;
@@ -10160,6 +10156,16 @@ static int vop2_crtc_atomic_set_property(struct drm_crtc *crtc,
return ret;
}
if (property == private->cubic_lut_prop) {
ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
&vcstate->cubic_lut_data,
val,
-1, sizeof(struct drm_color_lut),
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
}
DRM_ERROR("failed to set vop2 crtc property %s\n", property->name);
return -EINVAL;

8
drivers/gpu/drm/rockchip/rockchip_lvds.c
View File

@@ -83,8 +83,8 @@
enum lvds_format {
LVDS_8BIT_MODE_FORMAT_1,
LVDS_8BIT_MODE_FORMAT_2,
LVDS_8BIT_MODE_FORMAT_3,
LVDS_6BIT_MODE,
LVDS_6BIT_MODE_FORMAT_1,
LVDS_6BIT_MODE_FORMAT_2,
LVDS_10BIT_MODE_FORMAT_1,
LVDS_10BIT_MODE_FORMAT_2,
};
@@ -190,8 +190,8 @@ rockchip_lvds_encoder_atomic_mode_set(struct drm_encoder *encoder,
case MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA: /* jeida-30 */
lvds->format = LVDS_10BIT_MODE_FORMAT_2;
break;
case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: /* vesa-18 */
lvds->format = LVDS_8BIT_MODE_FORMAT_3;
case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: /* jeida-18, compatible with the [JEIDA], [LDI] and [VESA] specifications */
lvds->format = LVDS_6BIT_MODE_FORMAT_1;
break;
case MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG: /* vesa-30 */
lvds->format = LVDS_10BIT_MODE_FORMAT_1;

6
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1256,7 +1256,7 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
VOP_FEATURE_HDR10 | VOP_FEATURE_OVERSCAN,
.gamma_lut_len = 1024,
.cubic_lut_len = 729, /* 9x9x9 */
.max_output = { 4096, 2304 },
.max_output = { 4096, 4096 },
.pre_scan_max_dly = { 69, 53, 53, 42 },
.intr = &rk3568_vp0_intr,
.hdr_table = &rk3568_vop_hdr_table,
@@ -1267,7 +1267,7 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
.soc_id = { 0x3568, 0x3566 },
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
.gamma_lut_len = 1024,
.max_output = { 2048, 1536 },
.max_output = { 2048, 2048 },
.pre_scan_max_dly = { 40, 40, 40, 40 },
.intr = &rk3568_vp1_intr,
.regs = &rk3568_vop_vp1_regs,
@@ -1277,7 +1277,7 @@ static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
.feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
.soc_id = { 0x3568, 0x3566 },
.gamma_lut_len = 1024,
.max_output = { 1920, 1080 },
.max_output = { 1920, 1920 },
.pre_scan_max_dly = { 40, 40, 40, 40 },
.intr = &rk3568_vp2_intr,
.regs = &rk3568_vop_vp2_regs,

14
drivers/media/i2c/Kconfig
View File

@@ -60,6 +60,20 @@ config VIDEO_AR0521
To compile this driver as a module, choose M here: the
module will be called ar0521.
config VIDEO_AR0822
tristate "Onsemi AR0822 sensor support"
depends on I2C && VIDEO_DEV
depends on MEDIA_CAMERA_SUPPORT
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
This is a Video4Linux2 sensor driver for the Onsemi
AR0822 camera.
To compile this driver as a module, choose M here: the
module will be called ar0822.
config VIDEO_BF3925
tristate "BYD BF3925 sensor support"
depends on I2C && VIDEO_DEV

1
drivers/media/i2c/Makefile
View File

@@ -21,6 +21,7 @@ obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
obj-$(CONFIG_VIDEO_APTINA_PLL) += aptina-pll.o
obj-$(CONFIG_VIDEO_AR0230) += ar0230.o
obj-$(CONFIG_VIDEO_AR0521) += ar0521.o
obj-$(CONFIG_VIDEO_AR0822) += ar0822.o
obj-$(CONFIG_VIDEO_AW36518) += aw36518.o
obj-$(CONFIG_VIDEO_AW8601) += aw8601.o
obj-$(CONFIG_VIDEO_BF3925) += bf3925.o

5484
drivers/media/i2c/ar0822.c Normal file
View File

File diff suppressed because it is too large Load Diff

1589
drivers/media/i2c/max96722.c
View File

File diff suppressed because it is too large Load Diff

21
drivers/media/platform/rockchip/hdmirx/rk_hdmirx.c
View File

@@ -269,6 +269,7 @@ static int hdmirx_set_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev);
static void hdmirx_cancel_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev);
static void hdmirx_plugout(struct rk_hdmirx_dev *hdmirx_dev);
static void process_signal_change(struct rk_hdmirx_dev *hdmirx_dev);
static void hdmirx_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en);
static u8 edid_init_data_340M[] = {
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
@@ -615,8 +616,10 @@ static void hdmirx_get_colordepth(struct rk_hdmirx_dev *hdmirx_dev)
static void hdmirx_get_pix_fmt(struct rk_hdmirx_dev *hdmirx_dev)
{
u32 val;
int timeout = 10;
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
try_loop:
val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
hdmirx_dev->pix_fmt = val & HDMIRX_FORMAT_MASK;
@@ -635,11 +638,16 @@ static void hdmirx_get_pix_fmt(struct rk_hdmirx_dev *hdmirx_dev)
break;
default:
if (timeout-- > 0) {
usleep_range(200 * 1000, 200 * 1010);
v4l2_err(v4l2_dev, "%s: get format failed, read again!\n", __func__);
goto try_loop;
}
hdmirx_dev->pix_fmt = HDMIRX_RGB888;
hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
v4l2_err(v4l2_dev,
"%s: err pix_fmt: %d, set RGB888 as default\n",
__func__, hdmirx_dev->pix_fmt);
hdmirx_dev->pix_fmt = HDMIRX_RGB888;
hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
break;
}
@@ -880,9 +888,12 @@ static int hdmirx_try_to_get_timings(struct rk_hdmirx_dev *hdmirx_dev,
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
u32 last_w, last_h;
struct v4l2_bt_timings *bt = &timings->bt;
enum hdmirx_pix_fmt last_fmt;
last_w = 0;
last_h = 0;
last_fmt = HDMIRX_RGB888;
for (i = 0; i < try_cnt; i++) {
ret = hdmirx_get_detected_timings(hdmirx_dev, timings, from_dma);
@@ -891,7 +902,8 @@ static int hdmirx_try_to_get_timings(struct rk_hdmirx_dev *hdmirx_dev,
last_h = bt->height;
}
if (ret || (last_w != bt->width) || (last_h != bt->height))
if (ret || (last_w != bt->width) || (last_h != bt->height)
|| (last_fmt != hdmirx_dev->pix_fmt))
cnt = 0;
else
cnt++;
@@ -901,6 +913,7 @@ static int hdmirx_try_to_get_timings(struct rk_hdmirx_dev *hdmirx_dev,
last_w = bt->width;
last_h = bt->height;
last_fmt = hdmirx_dev->pix_fmt;
usleep_range(10*1000, 10*1100);
}
@@ -2349,6 +2362,7 @@ static void process_signal_change(struct rk_hdmirx_dev *hdmirx_dev)
FIFO_UNDERFLOW_INT_EN |
HDMIRX_AXI_ERROR_INT_EN, 0);
hdmirx_reset_dma(hdmirx_dev);
hdmirx_interrupts_setup(hdmirx_dev, false);
v4l2_event_queue(&stream->vdev, &evt_signal_lost);
if (hdmirx_dev->hdcp && hdmirx_dev->hdcp->hdcp_stop)
hdmirx_dev->hdcp->hdcp_stop(hdmirx_dev->hdcp);
@@ -3243,7 +3257,6 @@ static void hdmirx_delayed_work_res_change(struct work_struct *work)
plugin = tx_5v_power_present(hdmirx_dev);
v4l2_dbg(1, debug, v4l2_dev, "%s: plugin:%d\n", __func__, plugin);
if (plugin) {
hdmirx_interrupts_setup(hdmirx_dev, false);
hdmirx_submodule_init(hdmirx_dev);
hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, POWERPROVIDED,
POWERPROVIDED);

22
drivers/mmc/host/sdhci-of-dwcmshc.c
View File

@@ -335,17 +335,19 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
txclk_tapnum = drv_data->hs200_tx_tap;
if ((drv_data->flags & RK_DLL_CMD_OUT) &&
host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
txclk_tapnum = drv_data->hs400_tx_tap;
extra = DLL_CMDOUT_SRC_CLK_NEG |
DLL_CMDOUT_BOTH_CLK_EDGE |
DWCMSHC_EMMC_DLL_DLYENA |
drv_data->hs400_cmd_tap |
DLL_CMDOUT_TAPNUM_FROM_SW;
if (drv_data->flags & RK_TAP_VALUE_SEL)
extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET;
sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
if (drv_data->flags & RK_DLL_CMD_OUT) {
extra = DLL_CMDOUT_SRC_CLK_NEG |
DLL_CMDOUT_BOTH_CLK_EDGE |
DWCMSHC_EMMC_DLL_DLYENA |
drv_data->hs400_cmd_tap |
DLL_CMDOUT_TAPNUM_FROM_SW;
if (drv_data->flags & RK_TAP_VALUE_SEL)
extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET;
sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
}
}
extra = DWCMSHC_EMMC_DLL_DLYENA |
DLL_TXCLK_TAPNUM_FROM_SW |

5
drivers/nvme/host/nvme.h
View File

@@ -149,6 +149,11 @@ enum nvme_quirks {
* Reports garbage in the namespace identifiers (eui64, nguid, uuid).
*/
NVME_QUIRK_BOGUS_NID = (1 << 18),
/*
* Limit io queue depth to 32
*/
NVME_QUIRK_LIMIT_IOQD32 = (1 << 31),
};
/*

5
drivers/nvme/host/pci.c
View File

@@ -2611,6 +2611,9 @@ static int nvme_pci_enable(struct nvme_dev *dev)
dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
if (dev->ctrl.quirks & NVME_QUIRK_LIMIT_IOQD32)
io_queue_depth = 32;
dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
io_queue_depth);
dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
@@ -3473,6 +3476,8 @@ static const struct pci_device_id nvme_id_table[] = {
NVME_QUIRK_IGNORE_DEV_SUBNQN, },
{ PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
.driver_data = NVME_QUIRK_BOGUS_NID, },
{ PCI_DEVICE(0x1987, 0x5013), /* Phison E13 */
.driver_data = NVME_QUIRK_LIMIT_IOQD32},
{ PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
NVME_QUIRK_BOGUS_NID, },

60
drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
View File

@@ -81,6 +81,10 @@
#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
#define PCIE_CLIENT_LTSSM_STATUS 0x300
#define PCIE_CLIENT_INTR_MASK 0x24
#define PCIE_LTSSM_APP_DLY1_EN BIT(0)
#define PCIE_LTSSM_APP_DLY2_EN BIT(1)
#define PCIE_LTSSM_APP_DLY1_DONE BIT(2)
#define PCIE_LTSSM_APP_DLY2_DONE BIT(3)
#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
#define PCIE_CLIENT_MSI_GEN_CON 0x38
@@ -106,6 +110,7 @@
#define PCIE_EP_OBJ_INFO_DRV_VERSION 0x00000001
#define PCIE_BAR_MAX_NUM 6
#define PCIE_HOTRESET_TMOUT_US 10000
struct rockchip_pcie {
struct dw_pcie pci;
@@ -130,6 +135,8 @@ struct rockchip_pcie {
phys_addr_t dbi_base_physical;
struct pcie_ep_obj_info *obj_info;
enum pcie_ep_mmap_resource cur_mmap_res;
struct workqueue_struct *hot_rst_wq;
struct work_struct hot_rst_work;
};
struct rockchip_pcie_misc_dev {
@@ -586,7 +593,8 @@ static void rockchip_pcie_fast_link_setup(struct rockchip_pcie *rockchip)
/* LTSSM EN ctrl mode */
val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_HOT_RESET_CTRL);
val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
val |= (PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN) |
((PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN) << 16);
rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
}
@@ -642,7 +650,7 @@ static irqreturn_t rockchip_pcie_sys_irq_handler(int irq, void *arg)
u32 chn;
union int_status wr_status, rd_status;
union int_clear clears;
u32 reg, val, mask;
u32 reg, mask;
bool sigio = false;
/* ELBI helper, only check the valid bits, and discard the rest interrupts */
@@ -713,14 +721,8 @@ out:
}
reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
if (reg & BIT(2)) {
/* Setup command register */
val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
val &= 0xffff0000;
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
}
if (reg & BIT(2))
queue_work(rockchip->hot_rst_wq, &rockchip->hot_rst_work);
rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
@@ -870,6 +872,23 @@ static void rockchip_pcie_config_dma_dwc(struct dma_table *table)
table->start.chnl = table->chn;
}
static void rockchip_pcie_hot_rst_work(struct work_struct *work)
{
struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie, hot_rst_work);
u32 status;
int ret;
if (rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_HOT_RESET_CTRL) & PCIE_LTSSM_APP_DLY2_EN) {
ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_LTSSM_STATUS,
status, ((status & 0x3F) == 0), 100, PCIE_HOTRESET_TMOUT_US);
if (ret)
dev_err(rockchip->pci.dev, "wait for detect quiet failed!\n");
rockchip_pcie_writel_apb(rockchip, (PCIE_LTSSM_APP_DLY2_DONE) | ((PCIE_LTSSM_APP_DLY2_DONE) << 16),
PCIE_CLIENT_HOT_RESET_CTRL);
}
}
static int rockchip_pcie_get_dma_status(struct dma_trx_obj *obj, u8 chn, enum dma_dir dir)
{
struct rockchip_pcie *rockchip = dev_get_drvdata(obj->dev);
@@ -1121,6 +1140,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
struct rockchip_pcie *rockchip;
int ret;
int retry, i;
u32 reg;
rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
if (!rockchip)
@@ -1182,6 +1202,26 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
rockchip_pcie_start_link(&rockchip->pci);
rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_LNKRDY);
rockchip->hot_rst_wq = create_singlethread_workqueue("rkep_hot_rst_wq");
if (rockchip->hot_rst_wq) {
dev_err(dev, "failed to create hot_rst workqueue\n");
ret = -ENOMEM;
goto deinit_phy;
}
INIT_WORK(&rockchip->hot_rst_work, rockchip_pcie_hot_rst_work);
reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
if ((reg & BIT(2)) &&
(rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_HOT_RESET_CTRL) & PCIE_LTSSM_APP_DLY2_EN)) {
rockchip_pcie_writel_apb(rockchip, PCIE_LTSSM_APP_DLY2_DONE | (PCIE_LTSSM_APP_DLY2_DONE << 16),
PCIE_CLIENT_HOT_RESET_CTRL);
dev_info(dev, "hot reset ever\n");
}
rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
/* Enable client reset or link down interrupt */
rockchip_pcie_writel_apb(rockchip, 0x40000, PCIE_CLIENT_INTR_MASK);
for (retry = 0; retry < 10000; retry++) {
if (dw_pcie_link_up(&rockchip->pci)) {
/*

8
drivers/soc/rockchip/fiq_debugger/rk_fiq_debugger.c
View File

@@ -334,7 +334,7 @@ static int console_thread(void *data)
unsigned int dropped;
set_current_state(TASK_INTERRUPTIBLE);
if (kfifo_is_empty(&fifo) && kfifo_is_empty(&tty_fifo)) {
if (console_thread_stop || (kfifo_is_empty(&fifo) && kfifo_is_empty(&tty_fifo))) {
smp_store_mb(console_thread_running, false);
schedule();
smp_store_mb(console_thread_running, true);
@@ -344,13 +344,13 @@ static int console_thread(void *data)
set_current_state(TASK_RUNNING);
while (!console_thread_stop && (!kfifo_is_empty(&fifo) || !kfifo_is_empty(&tty_fifo))) {
while (kfifo_get(&fifo, &c)) {
while (!console_thread_stop && kfifo_get(&fifo, &c)) {
console_put(pdev, &c, 1);
if (c == '\n')
break;
}
while (kfifo_get(&tty_fifo, &c)) {
while (!console_thread_stop && kfifo_get(&tty_fifo, &c)) {
console_putc(pdev, c);
len_tty++;
if (c == '\n')
@@ -418,6 +418,8 @@ static int tty_write(struct platform_device *pdev, const char *s, int count)
unsigned int ret = 0;
struct rk_fiq_debugger *t;
if (console_thread_stop)
return count;
t = container_of(dev_get_platdata(&pdev->dev), typeof(*t), pdata);
if (count > 0) {

31
drivers/soc/rockchip/mtd_vendor_storage.c
View File

@@ -20,6 +20,7 @@
#define MTD_VENDOR_PART_START 0
#define MTD_VENDOR_PART_SIZE FLASH_VENDOR_PART_SIZE
#define MTD_VENDOR_NOR_BLOCK_SIZE 128
#define MTD_VENDOR_PART_NUM 1
#define MTD_VENDOR_TAG VENDOR_HEAD_TAG
@@ -43,6 +44,7 @@ static u8 *g_idb_buffer;
static struct flash_vendor_info *g_vendor;
static DEFINE_MUTEX(vendor_ops_mutex);
static struct mtd_info *mtd;
static u32 mtd_erase_size;
static const char *vendor_mtd_name = "vnvm";
static struct mtd_nand_info nand_info;
static struct platform_device *g_pdev;
@@ -54,8 +56,8 @@ static int mtd_vendor_nand_write(void)
struct erase_info ei;
re_write:
if (nand_info.page_offset >= mtd->erasesize) {
nand_info.blk_offset += mtd->erasesize;
if (nand_info.page_offset >= mtd_erase_size) {
nand_info.blk_offset += mtd_erase_size;
if (nand_info.blk_offset >= mtd->size)
nand_info.blk_offset = 0;
if (mtd_block_isbad(mtd, nand_info.blk_offset))
@@ -63,7 +65,7 @@ re_write:
memset(&ei, 0, sizeof(struct erase_info));
ei.addr = nand_info.blk_offset;
ei.len = mtd->erasesize;
ei.len = mtd_erase_size;
if (mtd_erase(mtd, &ei))
goto re_write;
@@ -100,7 +102,15 @@ static int mtd_vendor_storage_init(void)
nand_info.ops_size = (sizeof(*g_vendor) + mtd->writesize - 1) / mtd->writesize;
nand_info.ops_size *= mtd->writesize;
for (offset = 0; offset < mtd->size; offset += mtd->erasesize) {
/*
* The NOR FLASH erase size maybe config as 4KB, need to re-define
* and maintain consistency with uboot.
*/
mtd_erase_size = mtd->erasesize;
if (mtd_erase_size <= MTD_VENDOR_NOR_BLOCK_SIZE * 512)
mtd_erase_size = MTD_VENDOR_NOR_BLOCK_SIZE * 512;
for (offset = 0; offset < mtd->size; offset += mtd_erase_size) {
if (!mtd_block_isbad(mtd, offset)) {
err = mtd_read(mtd, offset, sizeof(*g_vendor),
&bytes_read, (u8 *)g_vendor);
@@ -115,11 +125,11 @@ static int mtd_vendor_storage_init(void)
}
}
} else if (nand_info.blk_offset == offset)
nand_info.blk_offset += mtd->erasesize;
nand_info.blk_offset += mtd_erase_size;
}
if (nand_info.version) {
for (offset = mtd->erasesize - nand_info.ops_size;
for (offset = mtd_erase_size - nand_info.ops_size;
offset >= 0;
offset -= nand_info.ops_size) {
err = mtd_read(mtd, nand_info.blk_offset + offset,
@@ -145,7 +155,10 @@ static int mtd_vendor_storage_init(void)
if (bytes_read == sizeof(*g_vendor) &&
g_vendor->tag == MTD_VENDOR_TAG &&
g_vendor->version == g_vendor->version2) {
nand_info.version = g_vendor->version;
if (nand_info.version > g_vendor->version)
g_vendor->version = nand_info.version;
else
nand_info.version = g_vendor->version;
break;
}
}
@@ -155,11 +168,11 @@ static int mtd_vendor_storage_init(void)
g_vendor->tag = MTD_VENDOR_TAG;
g_vendor->free_size = sizeof(g_vendor->data);
g_vendor->version2 = g_vendor->version;
for (offset = 0; offset < mtd->size; offset += mtd->erasesize) {
for (offset = 0; offset < mtd->size; offset += mtd_erase_size) {
if (!mtd_block_isbad(mtd, offset)) {
memset(&ei, 0, sizeof(struct erase_info));
ei.addr = nand_info.blk_offset + offset;
ei.len = mtd->erasesize;
ei.len = mtd_erase_size;
mtd_erase(mtd, &ei);
}
}

11
drivers/soc/rockchip/rockchip_opp_select.c
View File

@@ -1634,9 +1634,14 @@ static void rockchip_adjust_opp_by_otp(struct device *dev,
if (opp->rates[0] > opp_info.max_freq * 1000000)
continue;
opp->supplies->u_volt += opp_info.volt * 1000;
if (opp->supplies->u_volt > opp->supplies->u_volt_max)
opp->supplies->u_volt = opp->supplies->u_volt_max;
opp->supplies[0].u_volt += opp_info.volt * 1000;
if (opp->supplies[0].u_volt > opp->supplies[0].u_volt_max)
opp->supplies[0].u_volt = opp->supplies[0].u_volt_max;
if (opp_table->regulator_count > 1) {
opp->supplies[1].u_volt += opp_info.volt * 1000;
if (opp->supplies[1].u_volt > opp->supplies[1].u_volt_max)
opp->supplies[1].u_volt = opp->supplies[1].u_volt_max;
}
}
mutex_unlock(&opp_table->lock);

2
drivers/video/rockchip/mpp/mpp_common.c
View File

@@ -2266,7 +2266,7 @@ irqreturn_t mpp_dev_irq(int irq, void *param)
irq_ret = mpp->dev_ops->irq(mpp);
if (task) {
if (irq_ret != IRQ_NONE) {
if (irq_ret == IRQ_WAKE_THREAD) {
/* if wait or delayed work timeout, abort request will turn on,
* isr should not to response, and handle it in delayed work
*/

3
drivers/video/rockchip/mpp/mpp_rkvdec2_link.c
View File

@@ -1356,7 +1356,8 @@ int rkvdec2_attach_ccu(struct device *dev, struct rkvdec2_dev *dec)
/* set the ccu-domain for current device */
ccu_info = queue->cores[0]->iommu_info;
cur_info = dec->mpp.iommu_info;
cur_info->domain = ccu_info->domain;
if (cur_info)
cur_info->domain = ccu_info->domain;
mpp_iommu_attach(cur_info);
}

66
drivers/video/rockchip/mpp/mpp_rkvenc2.c
View File

@@ -177,6 +177,12 @@ union rkvenc2_dual_core_handshake_id {
#define RKVENC2_REG_SLICE_NUM_BASE (0x4034)
#define RKVENC2_REG_SLICE_LEN_BASE (0x4038)
#define RKVENC2_REG_ST_BSB (0x402c)
#define RKVENC2_REG_ADR_BSBT (0x2b0)
#define RKVENC2_REG_ADR_BSBB (0x2b4)
#define RKVENC2_REG_ADR_BSBR (0x2b8)
#define RKVENC2_REG_ADR_BSBS (0x2bc)
union rkvenc2_slice_len_info {
u32 val;
@@ -282,6 +288,8 @@ struct rkvenc_dev {
u32 sram_enabled;
struct page *rcb_page;
u32 bs_overflow;
#ifdef CONFIG_PM_DEVFREQ
struct rockchip_opp_info opp_info;
struct monitor_dev_info *mdev_info;
@@ -1289,6 +1297,8 @@ static int rkvenc_irq(struct mpp_dev *mpp)
struct rkvenc_hw_info *hw = enc->hw_info;
struct mpp_task *mpp_task = NULL;
struct rkvenc_task *task = NULL;
u32 int_clear = 1;
u32 irq_mask = 0;
int ret = IRQ_NONE;
mpp_debug_enter();
@@ -1310,12 +1320,12 @@ static int rkvenc_irq(struct mpp_dev *mpp)
wake_up(&mpp_task->wait);
}
mpp_write(mpp, hw->int_mask_base, 0x100);
mpp_write(mpp, hw->int_clr_base, 0xffffffff);
udelay(5);
mpp_write(mpp, hw->int_sta_base, 0);
irq_mask = INT_STA_ENC_DONE_STA;
ret = IRQ_WAKE_THREAD;
if (enc->bs_overflow) {
mpp->irq_status |= INT_STA_BSF_OFLW_STA;
enc->bs_overflow = 0;
}
} else if (mpp->irq_status & INT_STA_SLC_DONE_STA) {
if (task && task->task_split) {
mpp_time_part_diff(mpp_task);
@@ -1324,7 +1334,42 @@ static int rkvenc_irq(struct mpp_dev *mpp)
wake_up(&mpp_task->wait);
}
mpp_write(mpp, hw->int_clr_base, INT_STA_SLC_DONE_STA);
irq_mask = INT_STA_ENC_DONE_STA;
int_clear = 0;
} else if (mpp->irq_status & INT_STA_BSF_OFLW_STA) {
u32 bs_rd = mpp_read(mpp, RKVENC2_REG_ADR_BSBR);
u32 bs_wr = mpp_read(mpp, RKVENC2_REG_ST_BSB);
u32 bs_top = mpp_read(mpp, RKVENC2_REG_ADR_BSBT);
u32 bs_bot = mpp_read(mpp, RKVENC2_REG_ADR_BSBB);
if (mpp_task)
dev_err(mpp->dev, "task %d found bitstream overflow [%#08x %#08x %#08x %#08x]\n",
mpp_task->task_index, bs_top, bs_bot, bs_wr, bs_rd);
bs_wr += 128;
if (bs_wr >= bs_top)
bs_wr = bs_bot;
/* clear int first */
mpp_write(mpp, hw->int_clr_base, mpp->irq_status);
/* update write addr for enc continue */
mpp_write(mpp, RKVENC2_REG_ADR_BSBS, bs_wr);
enc->bs_overflow = 1;
irq_mask = 0;
int_clear = 0;
ret = IRQ_HANDLED;
} else {
dev_err(mpp->dev, "found error status %08x\n", mpp->irq_status);
irq_mask = mpp->irq_status;
ret = IRQ_WAKE_THREAD;
}
if (irq_mask)
mpp_write(mpp, hw->int_mask_base, irq_mask);
if (int_clear) {
mpp_write(mpp, hw->int_clr_base, mpp->irq_status);
udelay(5);
mpp_write(mpp, hw->int_sta_base, 0);
}
mpp_debug_leave();
@@ -2225,8 +2270,10 @@ static int rkvenc_attach_ccu(struct device *dev, struct rkvenc_dev *enc)
ccu_info = ccu->main_core->iommu_info;
cur_info = enc->mpp.iommu_info;
cur_info->domain = ccu_info->domain;
cur_info->rw_sem = ccu_info->rw_sem;
if (cur_info) {
cur_info->domain = ccu_info->domain;
cur_info->rw_sem = ccu_info->rw_sem;
}
mpp_iommu_attach(cur_info);
/* increase main core message capacity */
@@ -2404,7 +2451,8 @@ static int rkvenc_core_probe(struct platform_device *pdev)
}
mpp->session_max_buffers = RKVENC_SESSION_MAX_BUFFERS;
enc->hw_info = to_rkvenc_info(mpp->var->hw_info);
mpp->iommu_info->hdl = rkvenc2_iommu_fault_handle;
if (mpp->iommu_info)
mpp->iommu_info->hdl = rkvenc2_iommu_fault_handle;
rkvenc_procfs_init(mpp);
rkvenc_procfs_ccu_init(mpp);

3
drivers/video/rockchip/mpp/mpp_vepu2.c
View File

@@ -1050,7 +1050,8 @@ static int vepu_attach_ccu(struct device *dev, struct vepu_dev *enc)
ccu_info = ccu->main_core->iommu_info;
cur_info = enc->mpp.iommu_info;
cur_info->domain = ccu_info->domain;
if (cur_info)
cur_info->domain = ccu_info->domain;
mpp_iommu_attach(cur_info);
}
enc->ccu = ccu;

2
drivers/video/rockchip/rga3/include/rga_drv.h
View File

@@ -87,7 +87,7 @@
#define DRIVER_MAJOR_VERISON 1
#define DRIVER_MINOR_VERSION 2
#define DRIVER_REVISION_VERSION 26
#define DRIVER_REVISION_VERSION 27
#define DRIVER_PATCH_VERSION
#define DRIVER_VERSION (STR(DRIVER_MAJOR_VERISON) "." STR(DRIVER_MINOR_VERSION) \

2
drivers/video/rockchip/rga3/include/rga_mm.h
View File

@@ -18,6 +18,8 @@ enum rga_mm_flag {
RGA_MEM_NEED_USE_IOMMU = 1 << 1,
/* Flag this is a physical contiguous memory. */
RGA_MEM_PHYSICAL_CONTIGUOUS = 1 << 2,
/* need force flush cache */
RGA_MEM_FORCE_FLUSH_CACHE = 1 << 3,
};
struct rga_mm {

20
drivers/video/rockchip/rga3/rga_mm.c
View File

@@ -577,6 +577,13 @@ static int rga_mm_map_virt_addr(struct rga_external_buffer *external_buffer,
mm_flag |= RGA_MEM_PHYSICAL_CONTIGUOUS;
}
/*
* Some userspace virtual addresses do not have an
* interface for flushing the cache, so it is mandatory
* to flush the cache when the virtual address is used.
*/
mm_flag |= RGA_MEM_FORCE_FLUSH_CACHE;
if (!rga_mm_check_memory_limit(scheduler, mm_flag)) {
pr_err("scheduler core[%d] unsupported mm_flag[0x%x]!\n",
scheduler->core, mm_flag);
@@ -1434,7 +1441,7 @@ static int rga_mm_get_buffer(struct rga_mm *mm,
goto put_internal_buffer;
}
if (internal_buffer->type == RGA_VIRTUAL_ADDRESS) {
if (internal_buffer->mm_flag & RGA_MEM_FORCE_FLUSH_CACHE) {
/*
* Some userspace virtual addresses do not have an
* interface for flushing the cache, so it is mandatory
@@ -1463,7 +1470,7 @@ static void rga_mm_put_buffer(struct rga_mm *mm,
struct rga_internal_buffer *internal_buffer,
enum dma_data_direction dir)
{
if (internal_buffer->type == RGA_VIRTUAL_ADDRESS && dir != DMA_NONE)
if (internal_buffer->mm_flag & RGA_MEM_FORCE_FLUSH_CACHE && dir != DMA_NONE)
if (rga_mm_sync_dma_sg_for_cpu(internal_buffer, job, dir))
pr_err("sync sgt for cpu error!\n");
@@ -1765,7 +1772,7 @@ static void rga_mm_unmap_channel_job_buffer(struct rga_job *job,
struct rga_job_buffer *job_buffer,
enum dma_data_direction dir)
{
if (job_buffer->addr->type == RGA_VIRTUAL_ADDRESS && dir != DMA_NONE)
if (job_buffer->addr->mm_flag & RGA_MEM_FORCE_FLUSH_CACHE && dir != DMA_NONE)
if (rga_mm_sync_dma_sg_for_cpu(job_buffer->addr, job, dir))
pr_err("sync sgt for cpu error!\n");
@@ -1802,12 +1809,7 @@ static int rga_mm_map_channel_job_buffer(struct rga_job *job,
goto error_unmap_buffer;
}
if (buffer->type == RGA_VIRTUAL_ADDRESS) {
/*
* Some userspace virtual addresses do not have an
* interface for flushing the cache, so it is mandatory
* to flush the cache when the virtual address is used.
*/
if (buffer->mm_flag & RGA_MEM_FORCE_FLUSH_CACHE) {
ret = rga_mm_sync_dma_sg_for_device(buffer, job, dir);
if (ret < 0) {
pr_err("sync sgt for device error!\n");

11
include/drm/drm_crtc.h
View File

@@ -278,16 +278,7 @@ struct drm_crtc_state {
* CLUT or color palette) for indexed formats like DRM_FORMAT_C8.
*/
struct drm_property_blob *gamma_lut;
#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
/**
* @cubic_lut:
*
* Cubic Lookup table for converting pixel data. See
* drm_crtc_enable_color_mgmt(). The blob (if not NULL) is a 3D array
* of &struct drm_color_lut.
*/
struct drm_property_blob *cubic_lut;
#endif
/**
* @target_vblank:
*

13
include/drm/drm_mode_config.h
View File

@@ -812,19 +812,6 @@ struct drm_mode_config {
*/
struct drm_property *gamma_lut_size_property;
#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
/**
* @cubic_lut_property: Optional CRTC property to set the 3D LUT used to
* convert color spaces.
*/
struct drm_property *cubic_lut_property;
/**
* @cubic_lut_size_property: Optional CRTC property for the size of the
* 3D LUT as supported by the driver (read-only).
*/
struct drm_property *cubic_lut_size_property;
#endif
/**
* @suggested_x_property: Optional connector property with a hint for
* the position of the output on the host's screen.