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USB: Fix USB bypass UART function.

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This commit is contained in:
wlf
2014-03-27 16:16:25 +08:00
parent 57c92b59db
commit 1dbffa5af9
2 changed files with 12 additions and 8 deletions
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19
arch/arm/common/fiq_debugger.c Normal file → Executable file
View File

@@ -40,6 +40,9 @@
#include <asm/stacktrace.h>
#include <linux/uaccess.h>
#include <linux/rockchip/grf.h>
#include <linux/rockchip/iomap.h>
#include <linux/rockchip/cpu.h>
#include "fiq_debugger_ringbuf.h"
@@ -1166,15 +1169,15 @@ static void debug_fiq(struct fiq_glue_handler *h, void *regs, void *svc_sp)
* and make uart controller enter infinite fiq loop
*/
#ifdef CONFIG_RK_USB_UART
#ifdef CONFIG_ARCH_RK2928
if(!(readl_relaxed(RK2928_GRF_BASE + 0x014c) & (1<<10))){//id low
writel_relaxed(0x34000000, RK2928_GRF_BASE + 0x190); //enter usb phy
if(cpu_is_rk3188()){
if(!(readl_relaxed(RK_GRF_VIRT + RK3188_GRF_SOC_STATUS0) & (1 << 13))){//id low
writel_relaxed((0x0300 << 16), RK_GRF_VIRT + RK3188_GRF_UOC0_CON0); //enter usb phy
}
}else if(cpu_is_rk3288()){
if(!(readl_relaxed(RK_GRF_VIRT + RK3288_GRF_SOC_STATUS2) & (1 << 17))){//id low
writel_relaxed((0x00c0 << 16), RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);//enter usb phy
}
}
#elif defined(CONFIG_ARCH_RK3188)
if(!(readl_relaxed(RK30_GRF_BASE + 0x00ac) & (1 << 13))){//id low
writel_relaxed((0x0300 << 16), RK30_GRF_BASE + 0x010c); //enter usb phy
}
#endif
#endif
need_irq = debug_handle_uart_interrupt(state, this_cpu, regs, svc_sp);
if (need_irq)

1
arch/arm/mach-rockchip/rk3288.c Normal file → Executable file
View File

@@ -118,6 +118,7 @@ static void __init rk3288_dt_map_io(void)
{
iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc));
debug_ll_io_init();
usb_uart_init();
rockchip_soc_id = ROCKCHIP_SOC_RK3288;