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ARM: dts: rockchip: rk3288: Fix edp node

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Change-Id: I01855dd3ef2ea3be1db063e35f9aebd815fd66ba
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2020-12-11 00:59:00 +00:00
committed by Tao Huang
parent 36f27e6905
commit 1e6ad41b1d
1 changed files with 25 additions and 4 deletions
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29
arch/arm/boot/dts/rk3288.dtsi
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@@ -922,6 +922,13 @@
status = "disabled";
};
mipi_phy_rx0: mipi-phy-rx0 {
compatible = "rockchip,rk3288-mipi-dphy";
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
clock-names = "dphy-ref", "pclk";
status = "disabled";
};
usbphy: usbphy {
compatible = "rockchip,rk3288-usb-phy";
#address-cells = <1>;
@@ -1206,14 +1213,28 @@
};
};
video_phy: video-phy@ff96c000 {
compatible = "rockchip,rk3288-video-phy";
reg = <0x0 0xff96c000 0x0 0x4000>;
clocks = <&cru PCLK_LVDS_PHY>;
clock-names = "pclk";
resets = <&cru SRST_LVDS_PHY>;
reset-names = "rst";
power-domains = <&power RK3288_PD_VIO>;
#phy-cells = <0>;
status = "disabled";
};
edp: dp@ff970000 {
compatible = "rockchip,rk3288-dp";
reg = <0x0 0xff970000 0x0 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
phys = <&edp_phy>;
phy-names = "dp";
clocks = <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>,
<&cru SCLK_EDP>;
clock-names = "dp", "pclk", "spdif";
assigned-clocks = <&cru SCLK_EDP_24M>;
assigned-clock-parents = <&xin24m>;
power-domains = <&power RK3288_PD_VIO>;
resets = <&cru SRST_EDP>;
reset-names = "dp";
rockchip,grf = <&grf>;