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clk: rockchip: rk3399: make the cpll as parent just for vop

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others clk change it's parent from cpll to dummy_cpll.
the vop's parent just vpll and cpll,
make sure each vop have it's own pll as parent.

Change-Id: Ia61e10918e14a69c053455018ddf0183ff15ea19
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2016-09-12 09:57:04 +08:00
parent fda5ee0f9a
commit 1f7732bedf
2 changed files with 124 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

151
drivers/clk/rockchip/clk-rk3399.c
View File

@@ -145,10 +145,69 @@ PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
"clk_ddrc_bpll_src",
"clk_ddrc_dpll_src",
"clk_ddrc_gpll_src" };
PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
PNAME(mux_pll_src_dmyvpll_cpll_gpll_p) = { "dummy_vpll", "cpll", "gpll" };
#ifdef RK3399_TWO_PLL_FOR_VOP
PNAME(mux_aclk_cci_p) = { "dummy_cpll",
"gpll_aclk_cci_src",
"npll_aclk_cci_src",
"dummy_vpll" };
PNAME(mux_cci_trace_p) = { "dummy_cpll",
"gpll_cci_trace" };
PNAME(mux_cs_p) = { "dummy_cpll", "gpll_cs",
"npll_cs"};
PNAME(mux_aclk_perihp_p) = { "dummy_cpll",
"gpll_aclk_perihp_src" };
PNAME(mux_pll_src_cpll_gpll_p) = { "dummy_cpll", "gpll" };
PNAME(mux_pll_src_cpll_gpll_npll_p) = { "dummy_cpll", "gpll", "npll" };
PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "dummy_cpll", "gpll", "ppll" };
PNAME(mux_pll_src_cpll_gpll_upll_p) = { "dummy_cpll", "gpll", "upll" };
PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "dummy_cpll", "gpll" };
PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "dummy_cpll", "gpll", "npll",
"ppll" };
PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "dummy_cpll", "gpll", "npll",
"xin24m" };
PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "dummy_cpll", "gpll", "npll",
"clk_usbphy_480m" };
PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "dummy_cpll", "gpll",
"npll", "upll" };
PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "dummy_cpll", "gpll", "npll",
"upll", "xin24m" };
PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "dummy_cpll", "gpll", "npll",
"ppll", "upll", "xin24m" };
/*
* We hope to be able to HDMI/DP can obtain better signal quality,
* therefore, we move VOP pwm and aclk clocks to other PLLs, let
* HDMI/DP phyclock can monopolize VPLL.
*/
PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "dummy_cpll", "gpll",
"npll" };
PNAME(mux_pll_src_dmyvpll_cpll_gpll_gpll_p) = { "dummy_vpll", "dummy_cpll", "gpll",
"gpll" };
PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
"dummy_cpll", "gpll" };
PNAME(mux_aclk_emmc_p) = { "dummy_cpll",
"gpll_aclk_emmc_src" };
PNAME(mux_aclk_perilp0_p) = { "dummy_cpll",
"gpll_aclk_perilp0_src" };
PNAME(mux_fclk_cm0s_p) = { "dummy_cpll",
"gpll_fclk_cm0s_src" };
PNAME(mux_hclk_perilp1_p) = { "dummy_cpll",
"gpll_hclk_perilp1_src" };
PNAME(mux_aclk_gmac_p) = { "dummy_cpll",
"gpll_aclk_gmac_src" };
#else
PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
"gpll_aclk_cci_src",
"npll_aclk_cci_src",
"vpll_aclk_cci_src" };
"dummy_vpll" };
PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
"gpll_cci_trace" };
PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
@@ -173,26 +232,17 @@ PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
"upll", "xin24m" };
PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
"ppll", "upll", "xin24m" };
PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
/*
* We hope to be able to HDMI/DP can obtain better signal quality,
* therefore, we move VOP pwm and aclk clocks to other PLLs, let
* HDMI/DP phyclock can monopolize VPLL.
*/
PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "cpll", "gpll",
"npll" };
PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
"xin24m" };
PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
"dclk_vop0_frac" };
PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
"dclk_vop1_frac" };
PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
PNAME(mux_pll_src_dmyvpll_cpll_gpll_gpll_p) = { "dummy_vpll", "cpll", "gpll",
"gpll" };
PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
"cpll", "gpll" };
PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
"clk_pcie_core_phy" };
PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
"gpll_aclk_emmc_src" };
@@ -205,14 +255,26 @@ PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
"gpll_hclk_perilp1_src" };
PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
"gpll_aclk_gmac_src" };
#endif
PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
"dummy_dclk_vop0_frac" };
PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
"dummy_dclk_vop1_frac" };
PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
"clk_pcie_core_phy" };
PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
"clk_usbphy1_480m_src" };
PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
"gpll_aclk_gmac_src" };
PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
"clkin_i2s", "xin12m" };
@@ -247,8 +309,13 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
[dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
RK3399_PLL_CON(19), 8, 31, 0, NULL),
#ifdef RK3399_TWO_PLL_FOR_VOP
[cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
RK3399_PLL_CON(27), 8, 31, 0, rk3399_pll_rates),
#else
[cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
#endif
[gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
@@ -605,7 +672,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(5), 9, GFLAGS),
/* spdif */
COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE(SCLK_SPDIF_DIV, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0,
@@ -619,7 +686,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 6, GFLAGS),
/* i2s */
COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE(SCLK_I2S0_DIV, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 3, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
@@ -629,7 +696,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 5, GFLAGS),
COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE(SCLK_I2S1_DIV, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
@@ -639,7 +706,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
RK3399_CLKGATE_CON(8), 8, GFLAGS),
COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
COMPOSITE(SCLK_I2S2_DIV, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3399_CLKGATE_CON(8), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
@@ -656,7 +723,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(8), 12, GFLAGS),
/* uart */
MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
MUX(SCLK_UART0_SRC, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
@@ -666,7 +733,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(9), 1, GFLAGS,
&rk3399_uart0_fracmux, RK3399_UART_FRAC_MAX_PRATE),
MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
MUX(SCLK_UART_SRC, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
@@ -753,7 +820,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(2), 9, GFLAGS),
GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
COMPOSITE_NOGATE(SCLK_CS, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(15), 5, GFLAGS),
@@ -840,7 +907,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(16), 9, GFLAGS),
/* center */
COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
COMPOSITE(ACLK_CENTER, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3399_CLKGATE_CON(3), 7, GFLAGS),
GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
@@ -1170,7 +1237,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKGATE_CON(11), 7, GFLAGS),
/* vop0 */
COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 8, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
@@ -1187,20 +1254,27 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(28), 0, GFLAGS),
COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
#ifdef RK3399_TWO_PLL_FOR_VOP
COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3399_CLKGATE_CON(10), 12, GFLAGS),
#else
COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3399_CLKGATE_CON(10), 12, GFLAGS),
#endif
COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
/* The VOP0 is main screen, it is able to re-set parent rate. */
COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(106), 0,
&rk3399_dclk_vop0_fracmux, RK3399_VOP_FRAC_MAX_PRATE),
COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,
COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 14, GFLAGS),
/* vop1 */
COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 10, GFLAGS),
COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
@@ -1217,15 +1291,22 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(28), 4, GFLAGS),
COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
/* The VOP1 is sub screen, it is note able to re-set parent rate. */
#ifdef RK3399_TWO_PLL_FOR_VOP
COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3399_CLKGATE_CON(10), 13, GFLAGS),
#else
COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_dmyvpll_cpll_gpll_p, 0,
RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3399_CLKGATE_CON(10), 13, GFLAGS),
#endif
COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
RK3399_CLKSEL_CON(107), 0,
&rk3399_dclk_vop1_fracmux, RK3399_VOP_FRAC_MAX_PRATE),
COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(10), 15, GFLAGS),

8
include/dt-bindings/clock/rk3399-cru.h
View File

@@ -7,6 +7,8 @@
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
/* #define RK3399_TWO_PLL_FOR_VOP */
/* core clocks */
#define PLL_APLLL 1
#define PLL_APLLB 2
@@ -126,6 +128,12 @@
#define SCLK_USBPHY1_480M_SRC 169
#define SCLK_DDRC 170
#define SCLK_TESTCLKOUT2 171
#define SCLK_UART0_SRC 172
#define SCLK_UART_SRC 173
#define SCLK_I2S0_DIV 174
#define SCLK_I2S1_DIV 175
#define SCLK_I2S2_DIV 176
#define SCLK_SPDIF_DIV 177
#define SCLK_TESTCLKOUT1 179
#define DCLK_VOP0 180