hdmirx: add phy eq debug function [1/1]

PD#SWPL-12881

Problem:
Need to add eq debug function

Solution:
Add phy eq debug function,use auto-eq as default.

Verify:
TL1

Change-Id: I723d74d1bad226267b60ffb66d3670d01e6a4e1b
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
This commit is contained in:
yicheng shen
2019-10-10 20:06:09 +08:00
committed by Luke Go
parent 3850cdc48d
commit 1fb1400913
4 changed files with 69 additions and 9 deletions

View File

@@ -41,7 +41,7 @@
*
*
*/
#define RX_VER1 "ver.2019/09/05"
#define RX_VER1 "ver.2019/10/21"
/*
*
*

View File

@@ -105,6 +105,7 @@ int clock_lock_th = 2;
int scdc_force_en = 1;
/* for hdcp_hpd debug, disable by default */
bool hdcp_hpd_ctrl_en;
int eq_dbg_lvl;
/*------------------------variable define end------------------------------*/
@@ -3543,6 +3544,43 @@ static const uint32_t phy_dchd_2[][3] = {
},
};
static const u32 eq_debug[] = {
/* value eq gain */
0xffffffff,
0xffff1030,/* min */
0x7fff1030,
0x7f7f1030,
0x3f7f1030,
0x3f3f1030,
0x1f3f1030,
0x1f1f1030,
0x0f0f1030,/* half of all range max */
0x0f071030,
0x07071030,
0x07031030,
0x03031030,
0x03011030,
0x01011030,
0x01001030,
0x00001030,/* max */
0xffff0000,/* min */
0x7fff0000,
0x7f7f0000,
0x3f7f0000,
0x3f3f0000,
0x1f3f0000,
0x1f1f0000,
0x0f0f0000,/* half of all range max */
0x0f070000,
0x07070000,
0x07030000,
0x03030000,
0x03010000,
0x01010000,
0x01000000,
0x00000000,/* max */
};
void aml_phy_switch_port(void)
{
uint32_t data32;
@@ -3634,10 +3672,14 @@ void aml_phy_init_1(void)
void aml_phy_init(void)
{
uint32_t idx = rx.phy.phy_bw;
uint32_t data32;
u32 data32, c1, c2, r1, r2;
uint32_t term_value =
hdmirx_rd_top(TOP_HPD_PWR5V) & 0x7;
c1 = eq_debug[eq_dbg_lvl] & 0xff;
c2 = (eq_debug[eq_dbg_lvl] >> 8) & 0xff;
r1 = (eq_debug[eq_dbg_lvl] >> 16) & 0xff;
r2 = (eq_debug[eq_dbg_lvl] >> 24) & 0xff;
data32 = phy_misci[idx][0];
data32 = (data32 & (~0x7));
data32 |= term_value;
@@ -3679,14 +3721,27 @@ void aml_phy_init(void)
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
phy_dcha_reva[idx][2]);
} else {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0,
phy_dcha[idx][0]);
if (eq_dbg_lvl == 0) {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0,
phy_dcha[idx][0]);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1,
phy_dcha[idx][1]);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1,
phy_dcha[idx][1]);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
phy_dcha[idx][2]);
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
phy_dcha[idx][2]);
} else {
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0,
(phy_dcha[idx][0] | (c1 << 10)
| (c2 << 18) | (r1 << 26)));
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1,
(phy_dcha[idx][1] | (r1 >> 6))
| (r2 << 2));
wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
(phy_dcha[idx][2] & (~(1 << 24))));
}
}
if (cdr_lock_level == 0)

View File

@@ -1119,6 +1119,8 @@ extern int hbr_force_8ch;
extern int clock_lock_th;
extern int scdc_force_en;
extern bool hdcp_hpd_ctrl_en;
extern int eq_dbg_lvl;
extern void rx_get_best_eq_setting(void);
extern void wr_reg_hhi(unsigned int offset, unsigned int val);
extern void wr_reg_hhi_bits(unsigned int offset, unsigned int mask,
@@ -1223,10 +1225,10 @@ extern void rx_force_rxsense_cfg(uint8_t level);
extern void rx_force_hpd_rxsense_cfg(uint8_t level);
void rx_audio_bandgap_rst(void);
void rx_audio_bandgap_en(void);
void rx_aml_eq_debug(int eq_lvl);
extern void rx_phy_rxsense_pulse(unsigned int t1, unsigned int t2, bool en);
extern void rx_phy_power_on(unsigned int onoff);
enum measure_clk_top_e {
TOP_HDMI_TMDSCLK = 0,
TOP_HDMI_CABLECLK,

View File

@@ -1736,6 +1736,8 @@ int rx_set_global_variable(const char *buf, int size)
return pr_var(scdc_force_en, index);
if (set_pr_var(tmpbuf, hdcp_hpd_ctrl_en, value, &index, ret))
return pr_var(hdcp_hpd_ctrl_en, index);
if (set_pr_var(tmpbuf, eq_dbg_lvl, value, &index, ret))
return pr_var(eq_dbg_lvl, index);
return 0;
}
@@ -1850,6 +1852,7 @@ void rx_get_global_variable(const char *buf)
pr_var(earc_cap_ds_update_hpd_en, i++);
pr_var(scdc_force_en, i++);
pr_var(hdcp_hpd_ctrl_en, i++);
pr_var(eq_dbg_lvl, i++);
}
void skip_frame(unsigned int cnt)