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hdmirx: add phy eq debug function [1/1]
PD#SWPL-12881 Problem: Need to add eq debug function Solution: Add phy eq debug function,use auto-eq as default. Verify: TL1 Change-Id: I723d74d1bad226267b60ffb66d3670d01e6a4e1b Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
This commit is contained in:
@@ -41,7 +41,7 @@
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*
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*
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*/
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#define RX_VER1 "ver.2019/09/05"
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#define RX_VER1 "ver.2019/10/21"
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/*
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*
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*
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@@ -105,6 +105,7 @@ int clock_lock_th = 2;
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int scdc_force_en = 1;
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/* for hdcp_hpd debug, disable by default */
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bool hdcp_hpd_ctrl_en;
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int eq_dbg_lvl;
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/*------------------------variable define end------------------------------*/
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@@ -3543,6 +3544,43 @@ static const uint32_t phy_dchd_2[][3] = {
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},
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};
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static const u32 eq_debug[] = {
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/* value eq gain */
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0xffffffff,
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0xffff1030,/* min */
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0x7fff1030,
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0x7f7f1030,
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0x3f7f1030,
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0x3f3f1030,
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0x1f3f1030,
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0x1f1f1030,
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0x0f0f1030,/* half of all range max */
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0x0f071030,
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0x07071030,
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0x07031030,
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0x03031030,
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0x03011030,
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0x01011030,
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0x01001030,
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0x00001030,/* max */
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0xffff0000,/* min */
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0x7fff0000,
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0x7f7f0000,
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0x3f7f0000,
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0x3f3f0000,
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0x1f3f0000,
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0x1f1f0000,
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0x0f0f0000,/* half of all range max */
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0x0f070000,
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0x07070000,
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0x07030000,
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0x03030000,
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0x03010000,
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0x01010000,
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0x01000000,
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0x00000000,/* max */
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};
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void aml_phy_switch_port(void)
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{
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uint32_t data32;
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@@ -3634,10 +3672,14 @@ void aml_phy_init_1(void)
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void aml_phy_init(void)
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{
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uint32_t idx = rx.phy.phy_bw;
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uint32_t data32;
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u32 data32, c1, c2, r1, r2;
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uint32_t term_value =
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hdmirx_rd_top(TOP_HPD_PWR5V) & 0x7;
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c1 = eq_debug[eq_dbg_lvl] & 0xff;
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c2 = (eq_debug[eq_dbg_lvl] >> 8) & 0xff;
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r1 = (eq_debug[eq_dbg_lvl] >> 16) & 0xff;
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r2 = (eq_debug[eq_dbg_lvl] >> 24) & 0xff;
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data32 = phy_misci[idx][0];
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data32 = (data32 & (~0x7));
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data32 |= term_value;
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@@ -3679,14 +3721,27 @@ void aml_phy_init(void)
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wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
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phy_dcha_reva[idx][2]);
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} else {
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wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0,
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phy_dcha[idx][0]);
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if (eq_dbg_lvl == 0) {
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wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0,
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phy_dcha[idx][0]);
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wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1,
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phy_dcha[idx][1]);
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wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1,
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phy_dcha[idx][1]);
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wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
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phy_dcha[idx][2]);
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wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
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phy_dcha[idx][2]);
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} else {
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wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0,
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(phy_dcha[idx][0] | (c1 << 10)
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| (c2 << 18) | (r1 << 26)));
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wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1,
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(phy_dcha[idx][1] | (r1 >> 6))
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| (r2 << 2));
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wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2,
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(phy_dcha[idx][2] & (~(1 << 24))));
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}
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}
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if (cdr_lock_level == 0)
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@@ -1119,6 +1119,8 @@ extern int hbr_force_8ch;
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extern int clock_lock_th;
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extern int scdc_force_en;
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extern bool hdcp_hpd_ctrl_en;
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extern int eq_dbg_lvl;
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extern void rx_get_best_eq_setting(void);
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extern void wr_reg_hhi(unsigned int offset, unsigned int val);
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extern void wr_reg_hhi_bits(unsigned int offset, unsigned int mask,
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@@ -1223,10 +1225,10 @@ extern void rx_force_rxsense_cfg(uint8_t level);
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extern void rx_force_hpd_rxsense_cfg(uint8_t level);
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void rx_audio_bandgap_rst(void);
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void rx_audio_bandgap_en(void);
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void rx_aml_eq_debug(int eq_lvl);
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extern void rx_phy_rxsense_pulse(unsigned int t1, unsigned int t2, bool en);
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extern void rx_phy_power_on(unsigned int onoff);
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enum measure_clk_top_e {
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TOP_HDMI_TMDSCLK = 0,
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TOP_HDMI_CABLECLK,
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@@ -1736,6 +1736,8 @@ int rx_set_global_variable(const char *buf, int size)
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return pr_var(scdc_force_en, index);
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if (set_pr_var(tmpbuf, hdcp_hpd_ctrl_en, value, &index, ret))
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return pr_var(hdcp_hpd_ctrl_en, index);
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if (set_pr_var(tmpbuf, eq_dbg_lvl, value, &index, ret))
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return pr_var(eq_dbg_lvl, index);
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return 0;
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}
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@@ -1850,6 +1852,7 @@ void rx_get_global_variable(const char *buf)
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pr_var(earc_cap_ds_update_hpd_en, i++);
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pr_var(scdc_force_en, i++);
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pr_var(hdcp_hpd_ctrl_en, i++);
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pr_var(eq_dbg_lvl, i++);
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}
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void skip_frame(unsigned int cnt)
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