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Merge commit '0e6f34b90b7dee1271c4264b32668dbf7c198624'

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* commit '0e6f34b90b7dee1271c4264b32668dbf7c198624':
  video: rockchip: mpp_osal: add api mpp_device_add_driver() for rockit
  ASoC: rockchip: multicodecs: remove unused cables
  ASoC: rockchip: multicodecs: checking hp status when resume from sleep
  dt-bindings: suspend: rk3576: add RKPM_SLP_ARCH_TIMER_RESET macro
  dt-bindings: suspend: rk3588: add RKPM_SLP_ARCH_TIMER_RESET macro
  dt-bindings: suspend: rk3588: add sleep-pin related macros
  mmc: cqhci: add emmc hardware reset after cqe recovery
  arm64: dts: rockchip: rk3576: remove freq table for ufs
  scsi: ufs: rockchip: disabled devfreq for rk3576
  scsi: ufs: rockchip: fix dme-reset failed issue
  video: rockchip: rga3: fix bi-linear scaled down causing timeout
  video: rockchip: rga3: fix intr exception that causes driver timeout
  iio: imu: inv_icm42670: add core of new inv_icm42670 driver
  drm/rockchip: vop2: fix XRGB format alpha overlay error
  nvmem: rockchip-otp: reduce otp size to remove non-ecc area for rk3506

Change-Id: I806dbac1edb0c70840748e53fc1adf99ccc6e82e
This commit is contained in:
Tao Huang
2024-12-13 19:50:26 +08:00
parent d5a67c0586 0e6f34b90b
commit 1ffa5bc702
24 changed files with 2448 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm64/boot/dts/rockchip/rk3576.dtsi
View File

@@ -4785,7 +4785,6 @@
<&cru CLK_REF_UFS_CLKOUT>;
clock-names = "core", "pclk", "pclk_mphy",
"ref_out";
freq-table-hz = <50000000 250000000>, <0 0>, <0 0>, <0 0>;
assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;

14
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -10362,10 +10362,12 @@ static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config,
alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE;
alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en)
if (alpha_config->dst_pixel_alpha_en && dst_glb_alpha_en)
alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
else if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en)
alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX;
else
alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_GLOBAL;
alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION;
alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
}
@@ -10405,7 +10407,7 @@ static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_cluster *clu
struct vop2_plane_state *sub_vpstate;
struct vop2_plane_state *top_win_vpstate;
struct vop2_plane_state *bottom_win_vpstate;
bool src_pixel_alpha_en = false;
bool src_pixel_alpha_en = false, dst_pixel_alpha_en = false;
u16 src_glb_alpha_val = 0xff, dst_glb_alpha_val = 0xff;
bool premulti_en = false;
bool swap = false;
@@ -10456,10 +10458,11 @@ static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_cluster *clu
fb = bottom_win_vpstate->base.fb;
if (!fb)
return;
dst_pixel_alpha_en = is_alpha_support(fb->format->format);
alpha_config.src_premulti_en = premulti_en;
alpha_config.dst_premulti_en = false;
alpha_config.src_pixel_alpha_en = src_pixel_alpha_en;
alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
alpha_config.dst_pixel_alpha_en = dst_pixel_alpha_en; /* alpha value need transfer to next mix */
alpha_config.src_glb_alpha_value = src_glb_alpha_val;
alpha_config.dst_glb_alpha_value = dst_glb_alpha_val;
vop2_parse_alpha(&alpha_config, &alpha);
@@ -10702,7 +10705,8 @@ static void rk3576_extra_alpha(struct vop2_video_port *vp, const struct vop2_zpo
vop2_writel(vop2, 0x500, 1);/* enable port0_extra_alpha_en */
} else {
alpha_config.dst_pixel_alpha_en = false;
/* alpha value need transfer to next mix, and the data from last mix is at bottom layer */
alpha_config.dst_pixel_alpha_en = true;
alpha_config.dst_premulti_en = false;
alpha_config.src_pixel_alpha_en = false;
alpha_config.src_glb_alpha_value = 0xff;

1
drivers/iio/imu/Kconfig
View File

@@ -94,6 +94,7 @@ config KMX61
be called kmx61.
source "drivers/iio/imu/inv_icm42600/Kconfig"
source "drivers/iio/imu/inv_icm42670/Kconfig"
source "drivers/iio/imu/inv_mpu6050/Kconfig"
source "drivers/iio/imu/st_lsm6dsr/Kconfig"
source "drivers/iio/imu/st_lsm6dsx/Kconfig"

1
drivers/iio/imu/Makefile
View File

@@ -22,6 +22,7 @@ obj-$(CONFIG_FXOS8700_I2C) += fxos8700_i2c.o
obj-$(CONFIG_FXOS8700_SPI) += fxos8700_spi.o
obj-y += inv_icm42600/
obj-y += inv_icm42670/
obj-y += inv_mpu6050/
obj-$(CONFIG_KMX61) += kmx61.o

29
drivers/iio/imu/inv_icm42670/Kconfig Normal file
View File

@@ -0,0 +1,29 @@
# SPDX-License-Identifier: GPL-2.0-or-later
config INV_ICM42670
tristate
select IIO_BUFFER
config INV_ICM42670_I2C
tristate "InvenSense ICM-42670 I2C driver"
depends on I2C
select INV_ICM42670
select REGMAP_I2C
help
This driver supports the InvenSense ICM-426xx motion tracking
devices over I2C.
This driver can be built as a module. The module will be called
inv-icm42670-i2c.
config INV_ICM42670_SPI
tristate "InvenSense ICM-42670 SPI driver"
depends on SPI_MASTER
select INV_ICM42670
select REGMAP_SPI
help
This driver supports the InvenSense ICM-426xx motion tracking
devices over SPI.
This driver can be built as a module. The module will be called
inv-icm42670-spi.

12
drivers/iio/imu/inv_icm42670/Makefile Normal file
View File

@@ -0,0 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
obj-$(CONFIG_INV_ICM42670) += inv-icm42670.o
inv-icm42670-y += inv_icm42670_core.o
inv-icm42670-y += inv_icm42670_ring.o
inv-icm42670-y += inv_icm42670_trigger.o
obj-$(CONFIG_INV_ICM42670_I2C) += inv-icm42670-i2c.o
inv-icm42670-i2c-y += inv_icm42670_i2c.o
obj-$(CONFIG_INV_ICM42670_SPI) += inv-icm42670-spi.o
inv-icm42670-spi-y += inv_icm42670_spi.o

559
drivers/iio/imu/inv_icm42670/inv_icm42670.h Normal file
View File

@@ -0,0 +1,559 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2024 Rockchip Electronics Co., Ltd.
*/
#ifndef ICM42670_H_
#define ICM42670_H_
#include <linux/bits.h>
#include <linux/bitfield.h>
#include <linux/i2c.h>
#include <linux/i2c-mux.h>
#include <linux/mutex.h>
#include <linux/iio/iio.h>
#include <linux/iio/buffer.h>
#include <linux/regmap.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/kfifo_buf.h>
#include <linux/iio/trigger.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/trigger_consumer.h>
/* Registers and associated bit definitions */
/* Bank 0 */
#define REG_MCLK_RDY 0x00
#define REG_CHIP_CONFIG_REG 0x01
#define REG_SIGNAL_PATH_RESET 0x02
#define REG_DRIVE_CONFIG_REG1 0x03
#define REG_DRIVE_CONFIG_REG2 0x04
#define REG_DRIVE_CONFIG_REG3 0x05
#define REG_INT_CONFIG_REG 0x06
#define REG_TEMP_DATA0_UI 0x09
#define REG_TEMP_DATA1_UI 0x0a
#define REG_ACCEL_DATA_X0_UI 0x0b
#define REG_ACCEL_DATA_X1_UI 0x0c
#define REG_ACCEL_DATA_Y0_UI 0x0d
#define REG_ACCEL_DATA_Y1_UI 0x0e
#define REG_ACCEL_DATA_Z0_UI 0x0f
#define REG_ACCEL_DATA_Z1_UI 0x10
#define REG_GYRO_DATA_X0_UI 0x11
#define REG_GYRO_DATA_X1_UI 0x12
#define REG_GYRO_DATA_Y0_UI 0x13
#define REG_GYRO_DATA_Y1_UI 0x14
#define REG_GYRO_DATA_Z0_UI 0x15
#define REG_GYRO_DATA_Z1_UI 0x16
#define REG_TMST_FSYNC1 0x17
#define REG_TMST_FSYNC2 0x18
#define REG_APEX_DATA4 0x1d
#define REG_APEX_DATA5 0x1e
#define REG_PWR_MGMT_0 0x1f
#define REG_GYRO_CONFIG0 0x20
#define REG_ACCEL_CONFIG0 0x21
#define REG_TEMP_CONFIG0 0x22
#define REG_GYRO_CONFIG1 0x23
#define REG_ACCEL_CONFIG1 0x24
#define REG_APEX_CONFIG0 0x25
#define REG_APEX_CONFIG1 0x26
#define REG_WOM_CONFIG 0x27
#define REG_FIFO_CONFIG1 0x28
#define REG_FIFO_CONFIG2 0x29
#define REG_FIFO_CONFIG3 0x2a
#define REG_INT_SOURCE0 0x2b
#define REG_INT_SOURCE1 0x2c
#define REG_INT_SOURCE3 0x2d
#define REG_INT_SOURCE4 0x2e
#define REG_FIFO_LOST_PKT0 0x2f
#define REG_FIFO_LOST_PKT1 0x30
#define REG_APEX_DATA0 0x31
#define REG_APEX_DATA1 0x32
#define REG_APEX_DATA2 0x33
#define REG_APEX_DATA3 0x34
#define REG_INTF_CONFIG0 0x35
#define REG_INTF_CONFIG1 0x36
#define REG_INT_STATUS_DRDY 0x39
#define REG_INT_STATUS 0x3a
#define REG_INT_STATUS2 0x3b
#define REG_INT_STATUS3 0x3c
#define REG_FIFO_BYTE_COUNT1 0x3d
#define REG_FIFO_BYTE_COUNT2 0x3e
#define REG_FIFO_DATA_REG 0x3f
#define REG_WHO_AM_I 0x75
#define REG_BLK_SEL_W 0x79
#define REG_MADDR_W 0x7a
#define REG_M_W 0x7b
#define REG_BLK_SEL_R 0x7c
#define REG_MADDR_R 0x7d
#define REG_M_R 0x7e
/* MREG_TOP1 */
#define REG_TMST_CONFIG1_MREG_TOP1 0x00
#define REG_FIFO_CONFIG5_MREG_TOP1 0x01
#define REG_FIFO_CONFIG6_MREG_TOP1 0x02
#define REG_FSYNC_CONFIG_MREG_TOP1 0x03
#define REG_INT_CONFIG0_MREG_TOP1 0x04
#define REG_INT_CONFIG1_MREG_TOP1 0x05
#define REG_ST_CONFIG_MREG_TOP1 0x13
#define REG_SELFTEST_MREG_TOP1 0x14
#define REG_INTF_CONFIG6_MREG_TOP1 0x23
#define REG_INTF_CONFIG10_MREG_TOP1 0x25
#define REG_INTF_CONFIG7_MREG_TOP1 0x28
#define REG_OTP_CONFIG_MREG_TOP1 0x2b
#define REG_INT_SOURCE6_MREG_TOP1 0x2f
#define REG_INT_SOURCE7_MREG_TOP1 0x30
#define REG_INT_SOURCE8_MREG_TOP1 0x31
#define REG_INT_SOURCE9_MREG_TOP1 0x32
#define REG_APEX_CONFIG2_MREG_TOP1 0x44
#define REG_APEX_CONFIG3_MREG_TOP1 0x45
#define REG_APEX_CONFIG4_MREG_TOP1 0x46
#define REG_APEX_CONFIG5_MREG_TOP1 0x47
#define REG_APEX_CONFIG9_MREG_TOP1 0x48
#define REG_APEX_CONFIG10_MREG_TOP1 0x49
#define REG_APEX_CONFIG11_MREG_TOP1 0x4a
#define REG_ACCEL_WOM_X_THR_MREG_TOP1 0x4b
#define REG_ACCEL_WOM_Y_THR_MREG_TOP1 0x4c
#define REG_ACCEL_WOM_Z_THR_MREG_TOP1 0x4d
#define REG_GOS_USER0_MREG_TOP1 0x4e
#define REG_GOS_USER1_MREG_TOP1 0x4f
#define REG_GOS_USER2_MREG_TOP1 0x50
#define REG_GOS_USER3_MREG_TOP1 0x51
#define REG_GOS_USER4_MREG_TOP1 0x52
#define REG_GOS_USER5_MREG_TOP1 0x53
#define REG_GOS_USER6_MREG_TOP1 0x54
#define REG_GOS_USER7_MREG_TOP1 0x55
#define REG_GOS_USER8_MREG_TOP1 0x56
#define REG_ST_STATUS1_MREG_TOP1 0x63
#define REG_ST_STATUS2_MREG_TOP1 0x64
#define REG_FDR_CONFIG_MREG_TOP1 0x66
#define REG_APEX_CONFIG12_MREG_TOP1 0x67
/* MREG_TOP2 */
#define REG_OTP_CTRL7_MREG_OTP_TOP2 0x2806
/* MREG_TOP3 */
#define REG_XA_ST_DATA_MMEM_TOP3 0x5000
#define REG_YA_ST_DATA_MMEM_TOP3 0x5001
#define REG_ZA_ST_DATA_MMEM_TOP3 0x5002
#define REG_XG_ST_DATA_MMEM_TOP3 0x5003
#define REG_YG_ST_DATA_MMEM_TOP3 0x5004
#define REG_ZG_ST_DATA_MMEM_TOP3 0x5005
/* Bank0 REG_GYRO_CONFIG0/REG_ACCEL_CONFIG0 */
#define BIT_SENSOR_ODR_1600HZ 0x05 //(LN mode)
#define BIT_SENSOR_ODR_800HZ 0x06 //(LN mode)
#define BIT_SENSOR_ODR_400HZ 0x07 //(LP or LN mode)
#define BIT_SENSOR_ODR_200HZ 0x08 //(LP or LN mode)
#define BIT_SENSOR_ODR_100HZ 0x09 //(LP or LN mode)
#define BIT_SENSOR_ODR_50HZ 0x0A //(LP or LN mode)
#define BIT_SENSOR_ODR_25HZ 0x0B //(LP or LN mode)
#define BIT_SENSOR_ODR_12HZ 0x0C //(LP or LN mode)
#define BIT_SENSOR_ODR_6HZ 0x0D // only accel (LP mode)
#define BIT_SENSOR_ODR_3HZ 0x0E // only accel (LP mode)
#define BIT_SENSOR_ODR_1HZ 0x0F // only accel (LP mode)
#define BIT_ACCEL_FSR_16G 0x00
#define BIT_ACCEL_FSR_8G 0x01
#define BIT_ACCEL_FSR_4G 0x02
#define BIT_ACCEL_FSR_2G 0x03
#define BIT_GYRO_FSR_2000DPS 0X00
#define BIT_GYRO_FSR_1000DPS 0X01
#define BIT_GYRO_FSR_500DPS 0x02
#define BIT_GYRO_FSR_250DPS 0x03
#define BIT_GYRO_UI_FS_SEL_MASK GENMASK(6, 5)
#define BIT_GYRO_ODR_MASK GENMASK(3, 0)
#define BIT_ACCEL_UI_FS_SEL_MASK GENMASK(6, 5)
#define BIT_ACCEL_ODR_MASK GENMASK(3, 0)
/* Bank0 REG_GYRO_CONFIG1 */
#define BIT_GYR_UI_FLT_BW_BYPASS 0x00
#define BIT_GYR_UI_FLT_BW_180HZ 0x01
#define BIT_GYR_UI_FLT_BW_121HZ 0x02
#define BIT_GYR_UI_FLT_BW_73HZ 0x03
#define BIT_GYR_UI_FLT_BW_53HZ 0x04
#define BIT_GYR_UI_FLT_BW_34HZ 0x05
#define BIT_GYR_UI_FLT_BW_25HZ 0x06
#define BIT_GYR_UI_FLT_BW_16HZ 0x07
#define BIT_GYR_UI_AVG_IND_2X 0x00
#define BIT_GYR_UI_AVG_IND_4X 0x10
#define BIT_GYR_UI_AVG_IND_8X 0x20
#define BIT_GYR_UI_AVG_IND_16X 0x30
#define BIT_GYR_UI_AVG_IND_32X 0x40
#define BIT_GYR_UI_AVG_IND_64X 0x50
/* Bank0 REG_ACCEL_CONFIG1 */
#define BIT_ACC_FILT_BW_IND_BYPASS 0x00
#define BIT_ACC_FILT_BW_IND_180HZ 0x01
#define BIT_ACC_FILT_BW_IND_121HZ 0x02
#define BIT_ACC_FILT_BW_IND_73HZ 0x03
#define BIT_ACC_FILT_BW_IND_53HZ 0x04
#define BIT_ACC_FILT_BW_IND_34HZ 0x05
#define BIT_ACC_FILT_BW_IND_25HZ 0x06
#define BIT_ACC_FILT_BW_IND_16HZ 0x07
#define BIT_ACC_UI_AVG_IND_2X 0x00
#define BIT_ACC_UI_AVG_IND_4X 0x10
#define BIT_ACC_UI_AVG_IND_8X 0x20
#define BIT_ACC_UI_AVG_IND_16X 0x30
#define BIT_ACC_UI_AVG_IND_32X 0x40
#define BIT_ACC_UI_AVG_IND_64X 0x50
/* Bank0 REG_INT_CONFIG_REG */
#define SHIFT_INT1_MODE 0x02
#define SHIFT_INT1_DRIVE_CIRCUIT 0x01
#define SHIFT_INT1_POLARITY 0x00
#define BIT_ONLY_INT1_ACTIVE_HIGH \
((1 << SHIFT_INT1_POLARITY) | \
(1 << SHIFT_INT1_DRIVE_CIRCUIT) | \
(0 << SHIFT_INT1_MODE))
#define BIT_ONLY_INT1_ACTIVE_LOW \
((0 << SHIFT_INT1_POLARITY) | \
(1 << SHIFT_INT1_DRIVE_CIRCUIT) | \
(0 << SHIFT_INT1_MODE))
/* Bank0 REG_PWR_MGMT_0 */
#define BIT_PWR_MGMTO_ACCEL_LP_CLK_SEL BIT(7)
#define BIT_PWR_MGMT0_IDLE BIT(4)
#define BIT_PWR_MGMT0_GYRO(_mode) \
FIELD_PREP(GENMASK(3, 2), (_mode))
#define BIT_PWR_MGMT0_ACCEL(_mode) \
FIELD_PREP(GENMASK(1, 0), (_mode))
#define BIT_ACCEL_MODE_OFF 0x00
#define BIT_ACCEL_MODE_LPM 0x02
#define BIT_ACCEL_MODE_LNM 0x03
#define BIT_ACCEL_MODE_MASK 0x03
#define BIT_GYRO_MODE_OFF 0x00
#define BIT_GYRO_MODE_STBY 0x04
#define BIT_GYRO_MODE_LPM 0x08
#define BIT_GYRO_MODE_LNM 0x0c
#define BIT_GYRO_MODE_MASK 0x0c
#define BIT_IDLE 0x10
#define BIT_ACCEL_LP_CLK_SEL 0x80
/* Bank0 REG_SIGNAL_PATH_RESET */
#define BIT_FIFO_FLUSH BIT(2)
#define BIT_SOFT_RESET_CHIP_CONFIG BIT(4)
/* Bank0 REG_INTF_CONFIG0 */
#define BIT_FIFO_COUNT_REC_FIFO_COUNT_REC BIT(6)
#define BIT_FIFO_COUNT_REC_FIFO_COUNT_ENDIAN BIT(5)
#define BIT_FIFO_COUNT_REC_SENSOR_DATA_ENDIAN BIT(4)
#define BIT_FIFO_COUNT_REC_UI_SIFS_CFG_MASK GENMASK(1, 0)
#define BIT_FIFO_COUNT_REC_UI_SIFS_CFG_SPI_DIS \
FIELD_PREP(BIT_FIFO_COUNT_REC_UI_SIFS_CFG_MASK, 2)
#define BIT_FIFO_COUNT_REC_UI_SIFS_CFG_I2C_DIS \
FIELD_PREP(BIT_FIFO_COUNT_REC_UI_SIFS_CFG_MASK, 3)
/* Bank0 REG_INTF_CONFIG1 */
#define BIT_CLK_SEL_RC 0x00
#define BIT_CLK_SEL_PLL 0x01
#define BIT_CLK_SEL_DIS 0x03
#define BIT_I3C_DDR_EN 0x04
#define BIT_I3C_SDR_EN 0x08
#define BIT_GYRO_AFSR_MODE_LFS 0x00
#define BIT_GYRO_AFSR_MODE_HFS 0x20
#define BIT_GYRO_AFSR_MODE_DYN 0x40
/* Bank0 REG_FIFO_CONFIG1 */
#define BIT_FIFO_MODE_NO_BYPASS 0x00
#define BIT_FIFO_MODE_BYPASS 0x01
#define BIT_FIFO_MODE_STREAM 0x00
#define BIT_FIFO_MODE_STOPFULL 0x02
/* Bank0 REG_FIFO_CONFIG2 / REG_FIFO_CONFIG3 */
#define BIT_FIFO_WM5 0x10
#define INT_FIFO_WM5_NUM 16
/* Bank 0 REG_INT_SOURCE0 */
#define BIT_INT_MODE_OFF 0x00
#define BIT_INT_AGC_RDY_INT1_EN 0x01
#define BIT_INT_FIFO_FULL_INT1_EN 0x02
#define BIT_INT_FIFO_THS_INT1_EN 0x04
#define BIT_INT_DRDY_INT_EN 0x08
#define BIT_INT_RESET_DONE_INT1_EN 0x10
#define BIT_INT_PLL_RDY_INT1_EN 0x20
#define BIT_INT_FSYNC_INT1_EN 0x40
#define BIT_INT_ST_DONE_INT1_EN 0x80
/* Bank 0 REG_INT_SOURCE1 */
#define BIT_INT_WOM_X_INT1_EN 0x01
#define BIT_INT_WOM_Y_INT1_EN 0x02
#define BIT_INT_WOM_Z_INT1_EN 0x04
#define BIT_INT_WOM_XYZ_INT1_EN (BIT_INT_WOM_X_INT1_EN | \
BIT_INT_WOM_Y_INT1_EN | BIT_INT_WOM_Z_INT1_EN)
#define BIT_INT_SMD_INT1_EN 0x08
#define BIT_INT_I3C_PROTCL_ERR_INT1_EN 0x40
/* Bank0 REG_INT_STATUS_DRDY */
#define BIT_INT_STATUS_DRDY 0x01
/* Bank0 REG_INT_STATUS */
#define BIT_INT_STATUS_AGC_RDY 0x01
#define BIT_INT_STATUS_FIFO_FULL 0x02
#define BIT_INT_STATUS_FIFO_THS 0x04
#define BIT_INT_STATUS_RESET_DONE 0x10
#define BIT_INT_STATUS_PLL_RDY 0x20
#define BIT_INT_STATUS_FSYNC 0x40
#define BIT_INT_STATUS_ST_DONE 0x80
/* Bank0 REG_INT_STATUS2 */
#define BIT_INT_STATUS_WOM_Z 0x01
#define BIT_INT_STATUS_WOM_Y 0x02
#define BIT_INT_STATUS_WOM_X 0x04
#define BIT_INT_STATUS_WOM_XYZ (BIT_INT_STATUS_WOM_X | \
BIT_INT_STATUS_WOM_Y | BIT_INT_STATUS_WOM_Z)
#define BIT_INT_STATUS_SMD 0x08
/* Bank 0 REG_INT_STATUS3 */
#define BIT_INT_STATUS_LOWG_DET 0x02
#define BIT_INT_STATUS_FF_DET 0x04
#define BIT_INT_STATUS_TILT_DET 0x08
#define BIT_INT_STATUS_STEP_CNT_OVFL 0x10
#define BIT_INT_STATUS_STEP_DET 0x20
/* Bank0 REG_WOM_CONFIG */
#define BIT_WOM_EN_OFF 0x00
#define BIT_WOM_EN_ON 0x01
#define BIT_WOM_MODE_INITIAL 0x00
#define BIT_WOM_MODE_PREV 0x02
#define BIT_WOM_INT_MODE_OR 0x00
#define BIT_WOM_INT_MODE_AND 0x04
#define BIT_WOM_INT_DUR_LEGACY 0x00
#define BIT_WOM_INT_DUR_2ND 0x08
#define BIT_WOM_INT_DUR_3RD 0x10
#define BIT_WOM_INT_DUR_4TH 0x18
/* Bank0 REG_APEX_CONFIG0 */
#define BIT_DMP_SRAM_RESET_APEX 0x01
#define BIT_DMP_INIT_EN 0x04
#define BIT_DMP_POWER_SAVE_EN 0x08
/* Bank0 REG_APEX_CONFIG1 */
#define BIT_DMP_ODR_25HZ 0x00
#define BIT_DMP_ODR_50HZ 0x02
#define BIT_DMP_ODR_100HZ 0x03
#define BIT_DMP_PEDO_EN 0x08
#define BIT_DMP_TILT_EN 0x10
#define BIT_DMP_FF_EN 0x20
#define BIT_DMP_SMD_EN 0x40
/* Bank0 REG_WHO_AM_I */
#define BIT_I_AM_ICM42670 0x67
/* REG_OTP_CONFIG_MREG_TOP1 */
#define BIT_OTP_COPY_NORMAL 0x04
#define BIT_OTP_COPY_ST_DATA 0x0C
#define OTP_COPY_MODE_MASK 0x0C
/* REG_INT_SOURCE6_MREG_TOP1 */
#define BIT_INT_TLT_DET_INT1_EN 0x08
#define BIT_INT_STEP_CNT_OVFL_INT1_EN 0x10
#define BIT_INT_STEP_DET_INT1_EN 0x20
#define BIT_INT_LOWG_INT1_EN 0x40
#define BIT_INT_FF_INT1_EN 0x80
/* REG_TMST_CONFIG1_MREG_TOP1 */
#define BIT_TMST_EN 0x01
#define BIT_TMST_FSYNC_EN 0x02
#define BIT_TMST_DELTA_EN 0x04
#define BIT_TMST_RESOL 0x08
#define BIT_TMST_ON_SREG_EN 0x10
#define BIT_ODR_EN_WITHOUT_SENSOR 0x40
/* REG_FIFO_CONFIG5_MREG_TOP1 */
#define BIT_FIFO_ACCEL_EN 0x01
#define BIT_FIFO_GYRO_EN 0x02
#define BIT_FIFO_TMST_FSYNC_EN 0x04
#define BIT_FIFO_HIRES_EN 0x08
#define BIT_RESUME_PARTIAL_RD 0x10
#define BIT_WM_GT_TH 0x20
/* REG_SELFTEST_MREG_TOP1 */
#define BIT_EN_AX_ST 0x01
#define BIT_EN_AY_ST 0x02
#define BIT_EN_AZ_ST 0x04
#define BIT_EN_GX_ST 0x08
#define BIT_EN_GY_ST 0x10
#define BIT_EN_GZ_ST 0x20
#define BIT_ACCEL_ST_EN 0x40
#define BIT_GYRO_ST_EN 0x80
/* REG_ST_CONFIG_MREG_TOP1 */
#define BIT_PD_ACCEL_CP45_ST_REG 0x80
#define SHIFT_GYRO_ST_LIM 0
#define SHIFT_ACCEL_ST_LIM 3
#define SHIFT_ST_NUM_SAMPLE 6
/* REG_ST_STATUS1_MREG_TOP1 */
#define BIT_DMP_AX_ST_PASS 0x02
#define BIT_DMP_AY_ST_PASS 0x04
#define BIT_DMP_AZ_ST_PASS 0x08
#define BIT_DMP_ACCEL_ST_DONE 0x10
#define BIT_DMP_ACCEL_ST_PASS 0x20
/* REG_ST_STATUS2_MREG_TOP1 */
#define BIT_DMP_GX_ST_PASS 0x02
#define BIT_DMP_GY_ST_PASS 0x04
#define BIT_DMP_GZ_ST_PASS 0x08
#define BIT_DMP_GYRO_ST_DONE 0x10
#define BIT_DMP_GYRO_ST_PASS 0x20
#define BIT_DMP_ST_INCOMPLETE 0x40
/* REG_OTP_CTRL7_MREG_OTP */
#define BIT_OTP_RELOAD 0x08
#define BIT_OTP_PWR_DOWN 0x02
/** FIFO CONTENT DEFINITION */
#define HEADER_SIZE 1
#define ACCEL_DATA_SIZE 6
#define GYRO_DATA_SIZE 6
#define TEMP_DATA_SIZE 1
#define TS_FSYNC_SIZE 2
/* M-reg access wait tile */
#define ICM42670_MCLK_WAIT_US 20
#define ICM42670_BLK_SEL_WAIT_US 10
#define ICM42670_MADDR_WAIT_US 10
#define ICM42670_M_RW_WAIT_US 10
/* Allowed timestamp period jitter in percent */
#define ICM42670_TS_PERIOD_JITTER 4
enum ICM406xx_fio_format {
FIFO_20_BYTE,
FIFO_ACCEL_ONLY,
FIFO_GYRO_ONLY,
FIFO_16_BYTE,
};
enum inv_icm42670_sensor_mode {
INV_ICM42670_SENSOR_MODE_OFF,
INV_ICM42670_SENSOR_MODE_STANDBY,
INV_ICM42670_SENSOR_MODE_LOW_POWER,
INV_ICM42670_SENSOR_MODE_LOW_NOISE,
INV_ICM42670_SENSOR_MODE_NB,
};
#define FIFO_ACCEL_EN 0x40
#define FIFO_GYRO_EN 0x20
#define FIFO_TS_MASK 0x0C
#define FIFO_FSYNC_BITS 0x0C
#define HAVANA_MAX_PACKET_SIZE 20
#define ICM42670_FIFO_COUNT_LIMIT 60
#define ICM42670_DATA_BUFF_SIZE 960
// ODR
enum icm42670_odr_index {
ICM42670_ODR_RESERVED0 = 0,
ICM42670_ODR_RESERVED1,
ICM42670_ODR_RESERVED2,
ICM42670_ODR_8KHZ,
ICM42670_ODR_4KHZ,
ICM42670_ODR_2KHZ,
ICM42670_ODR_1KHZ,
ICM42670_ODR_200HZ,
ICM42670_ODR_100HZ,
ICM42670_ODR_50HZ,
ICM42670_ODR_25HZ,
ICM42670_NUM_ODRS, /* must be last */
};
struct icm42670_chip_config {
unsigned int fsr:2;
unsigned int lpf:3;
unsigned int accl_fs:2;
int gyro_odr:10;
int accel_odr:10;
unsigned int accl_fifo_enable:1;
unsigned int gyro_fifo_enable:1;
unsigned int temp_fifo_enable:1;
unsigned int time_fifo_enable:1;
u8 divider;
u8 user_ctrl;
};
struct icm42670_data {
struct mutex lock;
struct regmap *regmap;
struct iio_trigger *trig;
struct device_node *node;
int int1_gpio;
struct regulator *vdd_supply;
struct regulator *vddio_supply;
u16 accel_frequency;
u16 gyro_frequency;
u16 accel_frequency_buff;
u16 gyro_frequency_buff;
int irq;
u8 irq_mask;
int chip_type; // not used
unsigned int powerup_count;
struct icm42670_chip_config chip_config;
int skip_samples;
s64 it_timestamp; // Timestamp of when the data was read
s64 data_timestamp; // Timestamp of when the data was generated
s64 standard_period; // Standard interrupt period in nanoseconds
s64 interrupt_period; // Actual interrupt period in nanoseconds
s64 period_min; // Minimum interrupt period deviation in nanoseconds
s64 period_max; // Maximum interrupt period deviation in nanoseconds
int period_divider;
int interrupt_regval;
u8 data_buff[ICM42670_DATA_BUFF_SIZE];
};
/* scan indexes follow DATA register order */
enum icm42670_scan_axis {
ICM42670_SCAN_ACCEL_X = 0,
ICM42670_SCAN_ACCEL_Y,
ICM42670_SCAN_ACCEL_Z,
ICM42670_SCAN_GYRO_X,
ICM42670_SCAN_GYRO_Y,
ICM42670_SCAN_GYRO_Z,
ICM42670_SCAN_TEMP,
ICM42670_SCAN_TIMESTAMP,
};
enum icm42670_sensor_type {
ICM42670_ACCEL = 0,
ICM42670_GYRO,
ICM42670_TEMP,
ICM42670_TIMESTAMP,
ICM42670_NUM_SENSORS /* must be last */
};
#define IIO_TRIGGER 1
#define ICM42670_RESET_FLAG 1
#define ICM42670_DEBUG_FLAG 0
// fifo
#define ICM42670_OUTPUT_DATA_SIZE 24 // align 8, last 8 for timestamp
#define ICM42670_OUTPUT_DATA_SIZE_PULS_ONE 25
#define ICM42670_FIFO_DATUM 16
#define ICM42670_BYTES_PER_3AXIS_SENSOR 6
#define ICM42670_FIFO_COUNT_BYTE 2
#define ICM42670_BYTE_FIFO_TEMP 1
#define ICM42670_FIFO_SIZE 1024
typedef int (*icm42670_bus_setup)(struct icm42670_data *);
extern const struct regmap_config icm42670_regmap_config;
extern const struct dev_pm_ops icm42670_pm_ops;
irqreturn_t icm42670_read_fifo(int irq, void *p);
int icm42670_reset_fifo(struct iio_dev *indio_dev);
int icm42670_core_probe(struct regmap *regmap, int irq, const char *name,
int chip_type, icm42670_bus_setup bus_setup);
void icm42670_core_remove(struct device *dev);
int icm42670_probe_trigger(struct iio_dev *indio_dev, int irq_type);
int icm42670_set_enable(struct iio_dev *indio_dev, bool enable);
int icm42670_mreg_single_write(struct icm42670_data *st, int addr, u32 data);
int icm42670_set_mode(struct icm42670_data *data,
enum icm42670_sensor_type t,
bool mode);
int icm42670_mreg_read(struct icm42670_data *st, int addr, int len, u32 *data);
#endif

1122
drivers/iio/imu/inv_icm42670/inv_icm42670_core.c Normal file
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95
drivers/iio/imu/inv_icm42670/inv_icm42670_i2c.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Rockchip Electronics Co., Ltd.
*/
#include "linux/stddef.h"
#include <linux/acpi.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include "inv_icm42670.h"
static int icm42670_i2c_bus_setup(struct icm42670_data *st)
{
/* set slew rates for I2C and SPI */
// TODO
/* disable SPI bus */
return regmap_update_bits(st->regmap, REG_INTF_CONFIG0,
BIT_FIFO_COUNT_REC_UI_SIFS_CFG_MASK,
BIT_FIFO_COUNT_REC_UI_SIFS_CFG_SPI_DIS);
}
static int icm42670_i2c_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct regmap *regmap;
const char *name = NULL;
int chip_type = 0;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
dev_err(&client->dev, "I2c function error\n");
return -EOPNOTSUPP;
}
if (id) {
chip_type = id->driver_data;
name = id->name;
}
regmap = devm_regmap_init_i2c(client, &icm42670_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&client->dev, "Failed to register i2c regmap %d\n",
(int)PTR_ERR(regmap));
return PTR_ERR(regmap);
}
dev_info(&client->dev, "chip_type = %d, name = %s\n", chip_type, name);
return icm42670_core_probe(regmap, client->irq, name, chip_type, icm42670_i2c_bus_setup);
}
static void icm42670_i2c_remove(struct i2c_client *client)
{
icm42670_core_remove(&client->dev);
}
static const struct i2c_device_id icm42670_i2c_id[] = {
{"icm42670", 0},
{}
};
MODULE_DEVICE_TABLE(i2c, icm42670_i2c_id);
static const struct acpi_device_id icm42670_acpi_match[] = {
{"ICM42670", 0},
{ }
};
MODULE_DEVICE_TABLE(acpi, icm42670_acpi_match);
#ifdef CONFIG_OF
static const struct of_device_id icm42670_of_match[] = {
{ .compatible = "invensense,icm42670" },
{ },
};
MODULE_DEVICE_TABLE(of, icm42670_of_match);
#endif
static struct i2c_driver icm42670_i2c_driver = {
.driver = {
.name = "invensense,icm42670",
.acpi_match_table = ACPI_PTR(icm42670_acpi_match),
.of_match_table = of_match_ptr(icm42670_of_match),
.pm = &icm42670_pm_ops,
},
.probe = icm42670_i2c_probe,
.remove = icm42670_i2c_remove,
.id_table = icm42670_i2c_id,
};
module_i2c_driver(icm42670_i2c_driver);
MODULE_AUTHOR("Hangyu Li <hangyu.li@rock-chips.com>");
MODULE_DESCRIPTION("ICM42670 I2C driver");
MODULE_LICENSE("GPL");

244
drivers/iio/imu/inv_icm42670/inv_icm42670_ring.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Rockchip Electronics Co., Ltd.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/sysfs.h>
#include <linux/jiffies.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/poll.h>
#include <linux/math64.h>
#include <asm/unaligned.h>
#include "inv_icm42670.h"
/**
* icm42670_update_period() - Update chip internal period estimation
*
* @st: driver state
* @timestamp: the interrupt timestamp
* @nb: number of data set in the fifo
*
* This function uses interrupt timestamps to estimate the chip period and
* to choose the data timestamp to come.
*/
static void icm42670_update_period(struct icm42670_data *st,
s64 timestamp, size_t nb)
{
s64 interval;
if (st->it_timestamp != 0)
st->interrupt_period = div_s64((timestamp - st->it_timestamp), nb);
interval = (nb - 1) * st->interrupt_period;
st->data_timestamp = timestamp - interval;
/* save it timestamp */
st->it_timestamp = timestamp;
}
/**
* icm42670_get_timestamp() - Return the current data timestamp
*
* @st: driver state
* @return: current data timestamp
*
* This function returns the current data timestamp and prepares for next one.
*/
static s64 icm42670_get_timestamp(struct icm42670_data *st)
{
s64 ts;
/* return current data timestamp and increment */
ts = st->data_timestamp;
st->data_timestamp += st->interrupt_period;
return ts;
}
int icm42670_reset_fifo(struct iio_dev *indio_dev)
{
int ret;
struct icm42670_data *st = iio_priv(indio_dev);
const struct device *dev = regmap_get_device(st->regmap);
/* reset it timestamp validation */
st->it_timestamp = 0;
/* Before setting the FIFO water level, make sure the interrupt source is disabled. */
ret = regmap_write(st->regmap, REG_INT_SOURCE0, BIT_INT_MODE_OFF);
if (ret) {
dev_err(dev, "int_enable failed %d\n",
ret);
goto reset_fifo_fail;
}
/* disable the sensor output to FIFO */
ret = regmap_write(st->regmap, REG_FIFO_CONFIG1, BIT_FIFO_MODE_BYPASS);
if (ret) {
dev_err(dev, "Failed to write to REG_FIFO_CONFIG1 register!\n");
goto reset_fifo_fail;
}
/* reset FIFO*/
ret = regmap_update_bits(st->regmap, REG_SIGNAL_PATH_RESET,
BIT_FIFO_FLUSH, BIT_FIFO_FLUSH);
if (ret) {
dev_err(dev, "Failed to write to REG_SIGNAL_PATH_RESET register!\n");
goto reset_fifo_fail;
}
ndelay(1500); //wait for 1.5us
/* enable sensor output to FIFO */
ret = regmap_write(st->regmap, REG_FIFO_CONFIG1,
BIT_FIFO_MODE_NO_BYPASS | BIT_FIFO_MODE_STOPFULL);
if (ret) {
dev_err(dev, "Failed to write to REG_FIFO_CONFIG1 register!\n");
goto reset_fifo_fail;
}
ret = icm42670_mreg_single_write(st, REG_TMST_CONFIG1_MREG_TOP1,
BIT_TMST_EN | BIT_TMST_FSYNC_EN);
if (ret) {
dev_err(dev, "Failed to write to REG_TMST_CONFIG1_MREG_TOP1 register!\n");
goto reset_fifo_fail;
}
/*
* FIFO_COUNT_FORMAT setting. FIFO_WM_EN must be zero before writing this register.
* Interrupt only fires once. This register should be set to nonzero value,
* before choosing this interrupt source.
* This field should be changed when FIFO is empty to avoid spurious interrupts
*/
ret = regmap_write(st->regmap, REG_FIFO_CONFIG2, BIT_FIFO_WM5);
if (ret) {
dev_err(dev, "Failed to write to REG_FIFO_CONFIG2 register!\n");
goto reset_fifo_fail;
}
ret = icm42670_mreg_single_write(st, REG_FIFO_CONFIG5_MREG_TOP1,
BIT_WM_GT_TH | BIT_FIFO_ACCEL_EN |
BIT_FIFO_GYRO_EN | BIT_FIFO_TMST_FSYNC_EN);
if (ret) {
dev_err(dev, "Failed to write to REG_FIFO_CONFIG5_MREG_TOP1 register!\n");
goto reset_fifo_fail;
}
/* Set FIFO interrupt source to INT1*/
ret = regmap_write(st->regmap, REG_INT_SOURCE0,
BIT_INT_RESET_DONE_INT1_EN | BIT_INT_FIFO_THS_INT1_EN);
if (ret) {
dev_err(dev, "Failed to write to REG_INT_SOURCE0 register!\n");
goto reset_fifo_fail;
}
st->interrupt_period = st->standard_period;
return 0;
reset_fifo_fail:
dev_err(regmap_get_device(st->regmap), "%s :reset fifo failed %d\n", __func__, ret);
ret = regmap_write(st->regmap, REG_INT_SOURCE0,
BIT_INT_RESET_DONE_INT1_EN | BIT_INT_FIFO_THS_INT1_EN);
return ret;
}
/**
* icm42670_read_fifo() - Transfer data from hardware FIFO to KFIFO.
*/
irqreturn_t icm42670_read_fifo(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct icm42670_data *st = iio_priv(indio_dev);
const struct device *dev = regmap_get_device(st->regmap);
size_t bytes_per_datum;
int result, int_status, int_drdy;
u8 data[ICM42670_OUTPUT_DATA_SIZE_PULS_ONE], i;
u16 fifo_count;
u32 data_len;
s64 timestamp = 0;
mutex_lock(&st->lock);
/* ack interrupt and check status */
result = regmap_read(st->regmap, REG_INT_STATUS, &int_status);
if (result) {
dev_err(dev, "failed to ack interrupt\n");
goto flush_fifo;
}
result = regmap_read(st->regmap, REG_INT_STATUS_DRDY, &int_drdy);
if (result) {
dev_err(dev, "failed to ack interrupt\n");
goto flush_fifo;
}
if (!(int_status & BIT_INT_STATUS_FIFO_THS)) {
dev_warn(dev, "spurious interrupt with status 0x%x\n", int_status);
if (!(int_drdy & (BIT_INT_STATUS_DRDY)))
goto flush_fifo;
}
if ((int_status & BIT_INT_STATUS_FIFO_FULL)) {
dev_warn(dev, "the fifo is full\n");
goto flush_fifo;
}
bytes_per_datum = ICM42670_FIFO_DATUM;
result = regmap_bulk_read(st->regmap, REG_FIFO_BYTE_COUNT1,
data, ICM42670_FIFO_COUNT_BYTE);
if (result) {
dev_err(dev, "read fifo count fail: %d\n", result);
goto end_session;
}
fifo_count = get_unaligned_be16(&data[0]);
if (fifo_count > ICM42670_FIFO_COUNT_LIMIT) {
dev_warn(dev, "fifo overflow reset, cnt: %u\n", fifo_count);
goto flush_fifo;
}
icm42670_update_period(st, pf->timestamp, fifo_count);
data_len = bytes_per_datum * fifo_count;
result = regmap_bulk_read(st->regmap, REG_FIFO_DATA_REG,
st->data_buff, data_len);
if (result) {
dev_err(dev,
"regmap_bulk_read failed\n");
goto flush_fifo;
}
for (i = 0; i < fifo_count; ++i) {
/* skip first samples if needed */
if (st->skip_samples) {
st->skip_samples--;
continue;
}
memcpy(data, st->data_buff+i*16, bytes_per_datum);
timestamp = icm42670_get_timestamp(st);
iio_push_to_buffers_with_timestamp(indio_dev, &(data[1]), timestamp);
}
end_session:
mutex_unlock(&st->lock);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
flush_fifo:
/* Flush HW and SW FIFOs. */
dev_info(dev, "flush info\n");
icm42670_reset_fifo(indio_dev);
mutex_unlock(&st->lock);
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}

90
drivers/iio/imu/inv_icm42670/inv_icm42670_spi.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Rockchip Electronics Co., Ltd.
*/
#include "linux/stddef.h"
#include <linux/acpi.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include "inv_icm42670.h"
static int icm42670_spi_bus_setup(struct icm42670_data *st)
{
/* set slew rates for I2C and SPI */
// TODO
/* disable I2C bus */
return regmap_update_bits(st->regmap, REG_INTF_CONFIG0,
BIT_FIFO_COUNT_REC_UI_SIFS_CFG_MASK,
BIT_FIFO_COUNT_REC_UI_SIFS_CFG_I2C_DIS);
}
static int icm42670_spi_probe(struct spi_device *spi)
{
struct regmap *regmap;
const char *name = NULL;
int chip_type = 0;
const struct spi_device_id *id = spi_get_device_id(spi);
if (id) {
chip_type = id->driver_data;
name = id->name;
}
regmap = devm_regmap_init_spi(spi, &icm42670_regmap_config);
if (IS_ERR(regmap)) {
dev_err(&spi->dev, "Failed to register spi regmap %d\n",
(int)PTR_ERR(regmap));
return PTR_ERR(regmap);
}
dev_info(&spi->dev, "chip_type = %d, name = %s\n", chip_type, name);
return icm42670_core_probe(regmap, spi->irq, name, chip_type, icm42670_spi_bus_setup);
}
static void icm42670_spi_remove(struct spi_device *spi)
{
icm42670_core_remove(&spi->dev);
}
static const struct spi_device_id icm42670_spi_id[] = {
{"icm42670", 0},
{}
};
MODULE_DEVICE_TABLE(spi, icm42670_spi_id);
static const struct acpi_device_id icm42670_acpi_match[] = {
{"ICM42670", 0},
{ }
};
MODULE_DEVICE_TABLE(acpi, icm42670_acpi_match);
#ifdef CONFIG_OF
static const struct of_device_id icm42670_of_match[] = {
{ .compatible = "invensense,icm42670" },
{ },
};
MODULE_DEVICE_TABLE(of, icm42670_of_match);
#endif
static struct spi_driver icm42670_spi_driver = {
.driver = {
.name = "invensense,icm42670",
.acpi_match_table = ACPI_PTR(icm42670_acpi_match),
.of_match_table = of_match_ptr(icm42670_of_match),
.pm = &icm42670_pm_ops,
},
.probe = icm42670_spi_probe,
.remove = icm42670_spi_remove,
.id_table = icm42670_spi_id,
};
module_spi_driver(icm42670_spi_driver);
MODULE_AUTHOR("Hangyu Li <hangyu.li@rock-chips.com>");
MODULE_DESCRIPTION("ICM42670 SPI driver");
MODULE_LICENSE("GPL");

125
drivers/iio/imu/inv_icm42670/inv_icm42670_trigger.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Rockchip Electronics Co., Ltd.
*/
#include "inv_icm42670.h"
#include <linux/math64.h>
/**
* icm42670_set_enable() - enable chip functions.
* @indio_dev: Device driver instance.
* @enable: enable/disable
*/
int icm42670_set_enable(struct iio_dev *indio_dev, bool enable)
{
int ret;
struct icm42670_data *data = iio_priv(indio_dev);
const struct device *dev = regmap_get_device(data->regmap);
if (enable) {
ret = icm42670_set_mode(data, ICM42670_ACCEL, true);
if (ret)
goto error_off;
ret = icm42670_set_mode(data, ICM42670_GYRO, true);
if (ret)
goto error_accl_off;
ret = icm42670_reset_fifo(indio_dev);
if (ret)
goto error_gyro_off;
/* Theoretical interrupt period */
data->standard_period = data->period_divider > 0 ?
div_s64(NSEC_PER_SEC, data->period_divider) :
NSEC_PER_USEC * data->period_divider * (-1);
data->interrupt_period = data->standard_period;
/* Set a floating range of 4% */
data->period_min = div_s64((data->standard_period * (100 -
ICM42670_TS_PERIOD_JITTER)), 100);
data->period_max = div_s64((data->standard_period * (100 +
ICM42670_TS_PERIOD_JITTER)), 100);
} else {
ret = regmap_write(data->regmap, REG_FIFO_CONFIG1, BIT_FIFO_MODE_BYPASS);
if (ret) {
dev_err(dev, "set REG_FIFO_CONFIG1 fail: %d\n", ret);
goto error_gyro_off;
}
ret = icm42670_set_mode(data, ICM42670_GYRO, false);
if (ret)
goto error_gyro_off;
ret = icm42670_set_mode(data, ICM42670_ACCEL, false);
if (ret)
goto error_accl_off;
}
dev_info(dev, "set fifo mode end\n");
return ret;
error_gyro_off:
icm42670_set_mode(data, ICM42670_GYRO, false);
error_accl_off:
icm42670_set_mode(data, ICM42670_ACCEL, false);
error_off:
return ret;
}
/**
* inv_mpu_data_rdy_trigger_set_state() - set data ready interrupt state
* @trig: Trigger instance
* @state: Desired trigger state
*/
static int inv_mpu_data_rdy_trigger_set_state(struct iio_trigger *trig,
bool state)
{
struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
struct icm42670_data *data = iio_priv(indio_dev);
int result;
mutex_lock(&data->lock);
dev_info(regmap_get_device(data->regmap), "in data_rdy_trigger_set_state, %d\n", state);
result = icm42670_set_enable(indio_dev, state);
mutex_unlock(&data->lock);
return result;
}
static const struct iio_trigger_ops inv_mpu_trigger_ops = {
.set_trigger_state = &inv_mpu_data_rdy_trigger_set_state,
};
int icm42670_probe_trigger(struct iio_dev *indio_dev, int irq_type)
{
int ret;
struct icm42670_data *data = iio_priv(indio_dev);
data->trig = devm_iio_trigger_alloc(&indio_dev->dev,
"%s-dev%d",
indio_dev->name,
iio_device_id(indio_dev));
if (!data->trig)
return -ENOMEM;
ret = devm_request_irq(&indio_dev->dev, data->irq,
&iio_trigger_generic_data_rdy_poll,
irq_type,
"inv_mpu",
data->trig);
if (ret)
return ret;
data->trig->dev.parent = regmap_get_device(data->regmap);
data->trig->ops = &inv_mpu_trigger_ops;
iio_trigger_set_drvdata(data->trig, indio_dev);
ret = devm_iio_trigger_register(&indio_dev->dev, data->trig);
if (ret)
return ret;
indio_dev->trig = iio_trigger_get(data->trig);
return 0;
}

3
drivers/mmc/host/cqhci-core.c
View File

@@ -1120,6 +1120,9 @@ static void cqhci_recovery_finish(struct mmc_host *mmc)
cqhci_set_irqs(cq_host, CQHCI_IS_MASK);
/* Add emmc hardware reset after cqe recovery. */
mmc_hw_reset(mmc->card);
pr_debug("%s: cqhci: recovery done\n", mmc_hostname(mmc));
}

9
drivers/nvmem/rockchip-otp.c
View File

@@ -769,6 +769,13 @@ static const char * const rk3528_otp_clocks[] = {
"usr", "sbpi", "apb",
};
static const struct rockchip_data rk3506_data = {
.size = 0x78,
.clocks = rk3528_otp_clocks,
.num_clks = ARRAY_SIZE(rk3528_otp_clocks),
.reg_read = rk3568_otp_read,
};
static const struct rockchip_data rk3528_data = {
.size = 0x80,
.clocks = rk3528_otp_clocks,
@@ -870,7 +877,7 @@ static const struct of_device_id rockchip_otp_match[] = {
#ifdef CONFIG_CPU_RK3506
{
.compatible = "rockchip,rk3506-otp",
.data = (void *)&rk3528_data,
.data = (void *)&rk3506_data,
},
#endif
#ifdef CONFIG_CPU_RK3528

17
drivers/ufs/host/ufs-rockchip.c
View File

@@ -182,14 +182,25 @@ static int ufshcd_dme_link_startup(struct ufs_hba *hba)
return ret;
}
static void ufs_rockchip_controller_reset(struct ufs_rockchip_host *host)
{
reset_control_assert(host->rst);
udelay(1);
reset_control_deassert(host->rst);
}
static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status)
{
struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
int err = 0;
if (status == PRE_CHANGE) {
int retry_outer = 3;
int retry_inner;
ufs_rockchip_controller_reset(host);
start:
if (ufshcd_is_hba_active(hba))
/* change controller state to "reset state" */
@@ -374,9 +385,7 @@ static int ufs_rockchip_common_init(struct ufs_hba *hba)
return PTR_ERR(host->rst);
}
reset_control_assert(host->rst);
udelay(1);
reset_control_deassert(host->rst);
ufs_rockchip_controller_reset(host);
host->ref_out_clk = devm_clk_get(dev, "ref_out");
if (IS_ERR(host->ref_out_clk)) {
@@ -441,8 +450,6 @@ static int ufs_rockchip_rk3576_init(struct ufs_hba *hba)
hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
/* Enable putting device into deep sleep */
hba->caps |= UFSHCD_CAP_DEEPSLEEP;
/* Enable devfreq of UFS */
hba->caps |= UFSHCD_CAP_CLK_SCALING;
/* Enable WriteBooster */
hba->caps |= UFSHCD_CAP_WB_EN;

13
drivers/video/rockchip/mpp_osal/mpp_osal.c
View File

@@ -4,6 +4,7 @@
*
*/
#include "mpp_osal.h"
#include <linux/platform_device.h>
struct device_node *mpp_dev_of_node(struct device *dev)
{
@@ -28,3 +29,15 @@ int mpp_device_init_wakeup(struct device *dev, bool enable)
return device_init_wakeup(dev, enable);
}
EXPORT_SYMBOL(mpp_device_init_wakeup);
void mpp_device_add_driver(void *dev, void *drv)
{
#ifdef CONFIG_PM_SLEEP
struct device *kdev = (struct device *)dev;
struct platform_driver *mpi_driver = (struct platform_driver *)drv;
kdev->driver = &mpi_driver->driver;
kdev->power.no_pm_callbacks = 0;
#endif
}
EXPORT_SYMBOL(mpp_device_add_driver);

1
drivers/video/rockchip/mpp_osal/mpp_osal.h
View File

@@ -14,5 +14,6 @@ struct device_node *mpp_dev_of_node(struct device *dev);
void mpp_pm_relax(struct device *dev);
void mpp_pm_stay_awake(struct device *dev);
int mpp_device_init_wakeup(struct device *dev, bool enable);
void mpp_device_add_driver(void *dev, void *drv);
#endif

13
drivers/video/rockchip/rga3/include/rga2_reg_info.h
View File

@@ -292,11 +292,15 @@
/* RGA_SRC_ACT_INFO */
#define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH (0x1fff << 0)
#define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT (0x1fff << 16)
#define m_RGA2_SRC_ACT_INFO_SW_TILE4X4_IN_YOFF (0x3 << 30)
#define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT (0x7ff << 16)
#define m_RGA2_SRC_ACT_INFO_SW_TILE4X4_IN_XOFF (0x3 << 14)
#define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH (0x7ff << 0)
#define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH(x) ((x & 0x1fff) << 0)
#define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT(x) ((x & 0x1fff) << 16)
#define s_RGA2_SRC_ACT_INFO_SW_TILE4X4_IN_YOFF(x) ((x & 0x3) << 30)
#define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT(x) ((x & 0x7ff) << 16)
#define s_RGA2_SRC_ACT_INFO_SW_TILE4X4_IN_XOFF(x) ((x & 0x3) << 14)
#define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH(x) ((x & 0x7ff) << 0)
/* RGA2_OSD_CTRL0 */
#define m_RGA2_OSD_CTRL0_SW_OSD_MODE (0x3 << 0)
@@ -480,6 +484,7 @@
#define s_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH(x) ((x & 0x1) << 13)
#define RGA2_VSP_BICUBIC_LIMIT 1996
#define RGA2_BILINEAR_PREC 12
union rga2_color_ctrl {
uint32_t value;

2
drivers/video/rockchip/rga3/include/rga_drv.h
View File

@@ -88,7 +88,7 @@
#define DRIVER_MAJOR_VERISON 1
#define DRIVER_MINOR_VERSION 3
#define DRIVER_REVISION_VERSION 6
#define DRIVER_REVISION_VERSION 7
#define DRIVER_PATCH_VERSION
#define DRIVER_VERSION (STR(DRIVER_MAJOR_VERISON) "." STR(DRIVER_MINOR_VERSION) \

79
drivers/video/rockchip/rga3/rga2_reg_info.c
View File

@@ -101,17 +101,52 @@ unsigned int rga2_rop_code[256] = {
0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f
};
static void rga2_scale_down_bilinear_protect(u32 *param_fix, u32 *src_fix,
u32 param, u32 offset, u32 src, u32 dst)
{
int final_coor, final_diff, final_steps;
while (1) {
final_coor = offset + param * (dst - 1);
final_diff = (src - 1) * (1 << RGA2_BILINEAR_PREC) - final_coor;
/*
* The hardware requires that the last point of the dst map on
* src must not exceed the range of src.
*/
if (final_diff <= 0)
param = param - 1;
else
break;
}
/*
* The hardware requires that the last point of dst mapping on
* src be between the last two points of each row/column, so
* actual width/height needs to be modified.
*/
final_steps = (final_coor & ((1 << RGA2_BILINEAR_PREC) - 1)) ?
((final_coor >> RGA2_BILINEAR_PREC) + 1) :
(final_coor >> RGA2_BILINEAR_PREC);
*param_fix = param;
*src_fix = final_steps + 1;
}
static void RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
{
u32 *bRGA_SRC_X_FACTOR;
u32 *bRGA_SRC_Y_FACTOR;
u32 *bRGA_SRC_ACT_INFO;
u32 sw, sh;
u32 dw, dh;
u32 param_x, param_y;
u32 scale_x_offset, scale_y_offset;
u32 src_fix, param_fix;
bRGA_SRC_X_FACTOR = (u32 *) (base + RGA2_SRC_X_FACTOR_OFFSET);
bRGA_SRC_Y_FACTOR = (u32 *) (base + RGA2_SRC_Y_FACTOR_OFFSET);
bRGA_SRC_ACT_INFO = (u32 *) (base + RGA2_SRC_ACT_INFO_OFFSET);
if (((msg->rotate_mode & 0x3) == 1) ||
((msg->rotate_mode & 0x3) == 3)) {
@@ -128,10 +163,24 @@ static void RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
if (sw > dw) {
if (msg->interp.horiz == RGA_INTERP_LINEAR) {
/* default to half_pixel mode. */
param_x = (sw << 12) / dw;
scale_x_offset = 0x1ff;
param_x = (sw << RGA2_BILINEAR_PREC) / dw;
scale_x_offset = (1 << RGA2_BILINEAR_PREC) >> 1;
*bRGA_SRC_X_FACTOR = ((param_x & 0xffff) | ((scale_x_offset) << 16));
rga2_scale_down_bilinear_protect(&param_fix, &src_fix,
param_x, scale_x_offset, sw, dw);
if (DEBUGGER_EN(MSG)) {
if (param_x != param_fix)
rga_log("scale: Bi-linear horiz factor %#x fix to %#x\n",
param_x, param_fix);
if (sw != src_fix)
rga_log("scale: Bi-linear src_width %d -> %d\n",
sw, src_fix);
}
*bRGA_SRC_X_FACTOR = ((param_fix & 0xffff) | ((scale_x_offset) << 16));
*bRGA_SRC_ACT_INFO =
((*bRGA_SRC_ACT_INFO & (~m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH)) |
s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH((src_fix - 1)));
} else {
param_x = ((dw << 16) + (sw / 2)) / sw;
@@ -151,10 +200,24 @@ static void RGA2_reg_get_param(unsigned char *base, struct rga2_req *msg)
if (sh > dh) {
if (msg->interp.verti == RGA_INTERP_LINEAR) {
/* default to half_pixel mode. */
param_y = (sh << 12) / dh;
scale_y_offset = 0x1ff;
param_y = (sh << RGA2_BILINEAR_PREC) / dh;
scale_y_offset = (1 << RGA2_BILINEAR_PREC) >> 1;
*bRGA_SRC_Y_FACTOR = ((param_y & 0xffff) | ((scale_y_offset) << 16));
rga2_scale_down_bilinear_protect(&param_fix, &src_fix,
param_y, scale_y_offset, sh, dh);
if (DEBUGGER_EN(MSG)) {
if (param_y != param_fix)
rga_log("scale: Bi-linear verti factor %#x fix to %#x\n",
param_y, param_fix);
if (sh != src_fix)
rga_log("scale: Bi-linear src_height %d fix to %d\n",
sh, src_fix);
}
*bRGA_SRC_Y_FACTOR = ((param_fix & 0xffff) | ((scale_y_offset) << 16));
*bRGA_SRC_ACT_INFO =
((*bRGA_SRC_ACT_INFO & (~m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT)) |
s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT((src_fix - 1)));
} else {
param_y = ((dh << 16) + (sh / 2)) / sh;
@@ -363,10 +426,6 @@ static void RGA2_set_reg_src_info(u8 *base, struct rga2_req *msg)
vsd_scale_mode = 0;
break;
case RGA_INTERP_LINEAR:
if (sh > 4096)
/* force select average */
vsd_scale_mode = 0;
else
vsd_scale_mode = 1;
break;

3
drivers/video/rockchip/rga3/rga_job.c
View File

@@ -234,7 +234,8 @@ struct rga_job *rga_job_done(struct rga_scheduler_t *scheduler)
return NULL;
}
if (!test_bit(RGA_JOB_STATE_FINISH, &job->state)) {
if (!test_bit(RGA_JOB_STATE_FINISH, &job->state) &&
!test_bit(RGA_JOB_STATE_INTR_ERR, &job->state)) {
rga_err("%s(%#x) running job has not yet been completed.",
rga_get_core_name(scheduler->core), scheduler->core);

1
include/dt-bindings/suspend/rockchip-rk3576.h
View File

@@ -31,6 +31,7 @@
#define RKPM_SLP_32K_EXT BIT(24)
#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
#define RKPM_SLP_PMU_DBG BIT(26)
#define RKPM_SLP_ARCH_TIMER_RESET BIT(27)
/* the wake up source */
#define RKPM_CPU0_WKUP_EN BIT(0)

23
include/dt-bindings/suspend/rockchip-rk3588.h
View File

@@ -31,6 +31,7 @@
#define RKPM_SLP_32K_EXT BIT(24)
#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
#define RKPM_SLP_PMU_DBG BIT(26)
#define RKPM_SLP_ARCH_TIMER_RESET BIT(27)
/* the wake up source */
#define RKPM_CPU0_WKUP_EN BIT(0)
@@ -62,4 +63,26 @@
#define RKPM_VCCIO5_RET_EN BIT(5)
#define RKPM_VCCIO6_RET_EN BIT(6)
#define RKPM_PMUIO2_RET_EN BIT(7)
/* sleep pin */
#define RKPM_SLEEP_PIN0_ACT_LOW BIT(0) /* GPIO0_A2 */
#define RKPM_SLEEP_PIN1_ACT_LOW BIT(1) /* GPIO0_A3 */
#define RKPM_SLEEP_PIN_SRC_VD_NPU 0x1
#define RKPM_SLEEP_PIN_SRC_VD_GPU 0x2
#define RKPM_SLEEP_PIN_SRC_VD_BIGCORE0 0x3
#define RKPM_SLEEP_PIN_SRC_VD_BIGCORE1 0x4
#define RKPM_SLEEP_PIN_SRC_VD_DSU 0x5
#define RKPM_SLEEP_PIN_SRC_VD_VCODEC 0x6
#define RKPM_SLEEP_PIN_SRC_VD_DDR 0x7
#define RKPM_SLEEP_PIN_SRC_LP_DEEP_LP 0x8
#define RKPM_SLEEP_PIN_SRC_SFT_EN 0xf
#define RKPM_SLEEP_PIN0_SRC(n) (((n) & 0xf) << 0)
#define RKPM_SLEEP_PIN1_SRC(n) (((n) & 0xf) << 4)
#define RKPM_SLEEP_PIN2_SRC(n) (((n) & 0xf) << 8)
#define RKPM_SLEEP_PIN3_SRC(n) (((n) & 0xf) << 12)
#define RKPM_SLEEP_PIN4_SRC(n) (((n) & 0xf) << 16)
#define RKPM_SLEEP_PIN5_SRC(n) (((n) & 0xf) << 20)
#endif

22
sound/soc/rockchip/rockchip_multicodecs.c
View File

@@ -83,9 +83,9 @@ struct multicodecs_data {
unsigned int rx_slot_mask;
};
static const unsigned int headset_extcon_cable[] = {
EXTCON_JACK_MICROPHONE,
EXTCON_JACK_HEADPHONE,
static unsigned int headset_extcon_cable[] = {
EXTCON_NONE,
EXTCON_NONE,
EXTCON_NONE,
};
@@ -740,6 +740,16 @@ static int rk_multicodecs_probe_keys(struct platform_device *pdev,
return ret;
}
static int rk_multicodecs_resume_post(struct snd_soc_card *card)
{
struct multicodecs_data *mc_data = dev_get_drvdata(card->dev);
if (gpiod_to_irq(mc_data->hp_det_gpio) >= 0)
queue_delayed_work(system_power_efficient_wq, &mc_data->handler,
msecs_to_jiffies(200));
return 0;
}
static int rk_multicodecs_probe(struct platform_device *pdev)
{
struct snd_soc_card *card;
@@ -752,6 +762,7 @@ static int rk_multicodecs_probe(struct platform_device *pdev)
int count, irq;
int ret = 0, i = 0, idx = 0;
const char *prefix = "rockchip,";
int cable = 0;
ret = wait_locked_card(np, &pdev->dev);
if (ret < 0) {
@@ -898,6 +909,7 @@ static int rk_multicodecs_probe(struct platform_device *pdev)
ret = rk_multicodecs_probe_keys(pdev, mc_data);
if (ret)
dev_warn(&pdev->dev, "Has no input keys\n");
headset_extcon_cable[cable++] = EXTCON_JACK_MICROPHONE;
}
INIT_DEFERRABLE_WORK(&mc_data->handler, adc_jack_handler);
@@ -917,6 +929,10 @@ static int rk_multicodecs_probe(struct platform_device *pdev)
mc_data->hp_det_gpio = devm_gpiod_get_optional(&pdev->dev, "hp-det", GPIOD_IN);
if (IS_ERR(mc_data->hp_det_gpio))
return PTR_ERR(mc_data->hp_det_gpio);
if (gpiod_to_irq(mc_data->hp_det_gpio) >= 0) {
headset_extcon_cable[cable++] = EXTCON_JACK_HEADPHONE;
card->resume_post = &rk_multicodecs_resume_post;
}
mc_data->extcon = devm_extcon_dev_allocate(&pdev->dev, headset_extcon_cable);
if (IS_ERR(mc_data->extcon)) {