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clk: rockchip: Fix rk3036 pll rate overflow calculation on 32-bit

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Change-Id: I4e367893e97828b01b3e6ec457714c722d2c0af6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-06-20 14:37:55 +08:00
committed by Tao Huang
parent 816ae96705
commit 2046169992
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-pll.c
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@@ -376,7 +376,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
struct rockchip_pll_rate_table cur;
u64 rate64 = prate;
u64 rate64 = prate, frac_rate64 = prate;
if (pll->sel && pll->scaling)
return pll->scaling;
@@ -388,7 +388,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
if (cur.dsmpd == 0) {
/* fractional mode */
u64 frac_rate64 = prate * cur.frac;
frac_rate64 *= cur.frac;
do_div(frac_rate64, cur.refdiv);
rate64 += frac_rate64 >> 24;