MALI: bifrost: quick_reset: use short timeout (quick_reset) for the case to workaround

Not work for CSF based Valhall GPU.

Change-Id: I38d27d2006e25acbab826efd36b49efffa6b79f1
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>

drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_js_backend.c

@@ -131,10 +131,15 @@ static enum hrtimer_restart timer_callback(struct hrtimer *timer)
 				} else {
 					soft_stop_ticks =
 						js_devdata->soft_stop_ticks;
+					if (kbase_is_quick_reset_enabled(kbdev)) {
+						hard_stop_ticks = 2;
+						gpu_reset_ticks = 3;
+					} else {
 					hard_stop_ticks =
 						js_devdata->hard_stop_ticks_ss;
 					gpu_reset_ticks =
 						js_devdata->gpu_reset_ticks_ss;
+					}
 				}
 
 				/* If timeouts have been changed then ensure

drivers/gpu/arm/bifrost/device/mali_kbase_device.c

@@ -326,6 +326,13 @@ int kbase_device_misc_init(struct kbase_device * const kbdev)
 			"Unable to register OOM notifier for Mali - but will continue\n");
 		kbdev->oom_notifier_block.notifier_call = NULL;
 	}
+
+#if !MALI_USE_CSF
+	spin_lock_init(&kbdev->quick_reset_lock);
+	kbdev->quick_reset_enabled = true;
+	kbdev->num_of_atoms_hw_completed = 0;
+#endif
+
 	return 0;
 
 term_ktrace:
@@ -356,6 +363,33 @@ void kbase_device_misc_term(struct kbase_device *kbdev)
 		unregister_oom_notifier(&kbdev->oom_notifier_block);
 }
 
+#if !MALI_USE_CSF
+void kbase_enable_quick_reset(struct kbase_device *kbdev)
+{
+	spin_lock(&kbdev->quick_reset_lock);
+
+	kbdev->quick_reset_enabled = true;
+	kbdev->num_of_atoms_hw_completed = 0;
+
+	spin_unlock(&kbdev->quick_reset_lock);
+}
+
+void kbase_disable_quick_reset(struct kbase_device *kbdev)
+{
+	spin_lock(&kbdev->quick_reset_lock);
+
+	kbdev->quick_reset_enabled = false;
+	kbdev->num_of_atoms_hw_completed = 0;
+
+	spin_unlock(&kbdev->quick_reset_lock);
+}
+
+bool kbase_is_quick_reset_enabled(struct kbase_device *kbdev)
+{
+	return kbdev->quick_reset_enabled;
+}
+#endif
+
 void kbase_device_free(struct kbase_device *kbdev)
 {
 	kfree(kbdev);

drivers/gpu/arm/bifrost/mali_kbase.h

@@ -115,6 +115,13 @@ struct kbase_device *kbase_device_alloc(void);
 
 int kbase_device_misc_init(struct kbase_device *kbdev);
 void kbase_device_misc_term(struct kbase_device *kbdev);
+
+#if !MALI_USE_CSF
+void kbase_enable_quick_reset(struct kbase_device *kbdev);
+void kbase_disable_quick_reset(struct kbase_device *kbdev);
+bool kbase_is_quick_reset_enabled(struct kbase_device *kbdev);
+#endif
+
 void kbase_device_free(struct kbase_device *kbdev);
 int kbase_device_has_feature(struct kbase_device *kbdev, u32 feature);
 

drivers/gpu/arm/bifrost/mali_kbase_core_linux.c

@@ -5564,6 +5564,11 @@ static int kbase_device_resume(struct device *dev)
 	if (kbdev->devfreq)
 		kbase_devfreq_enqueue_work(kbdev, DEVFREQ_WORK_RESUME);
 #endif
+
+#if !MALI_USE_CSF
+	kbase_enable_quick_reset(kbdev);
+#endif
+
 	return 0;
 }
 

drivers/gpu/arm/bifrost/mali_kbase_defs.h

@@ -1241,6 +1241,18 @@ struct kbase_device {
 
 	struct notifier_block oom_notifier_block;
 
+#if !MALI_USE_CSF
+	spinlock_t quick_reset_lock;
+	bool quick_reset_enabled;
+	/*
+	 * 进入 quck_reset_mode 后 (quick_reset_enabled 为 true),
+	 * 对已经进入 KBASE_JD_ATOM_STATE_HW_COMPLETED 状态的 atom 的计数.
+	 *
+	 * 若 num_of_atoms_hw_completed 达到一定值, 将退出 quck_reset_mode.
+	 * 见 kbase_js_complete_atom() 对 num_of_atoms_hw_completed 的引用.
+	 */
+	u32 num_of_atoms_hw_completed;
+#endif
 };
 
 /**

drivers/gpu/arm/bifrost/mali_kbase_js.c

@@ -3484,6 +3484,11 @@ struct kbase_jd_atom *kbase_js_complete_atom(struct kbase_jd_atom *katom,
 
 	katom->status = KBASE_JD_ATOM_STATE_HW_COMPLETED;
 	dev_dbg(kbdev->dev, "Atom %pK status to HW completed\n", (void *)katom);
+	if (kbase_is_quick_reset_enabled(kbdev)) {
+		kbdev->num_of_atoms_hw_completed++;
+		if (kbdev->num_of_atoms_hw_completed >= 20)
+			kbase_disable_quick_reset(kbdev);
+	}
 
 	if (katom->event_code != BASE_JD_EVENT_DONE) {
 		kbase_js_evict_deps(kctx, katom, katom->slot_nr,