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amvecm: add amvecm driver

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PD#138714: add amvecm driver

Change-Id: Ieb0be7a4b02b7a8daa549544a97ee23e0daeb6da
Signed-off-by: MingLiang Dong <mingliang.dong@amlogic.com>
This commit is contained in:
MingLiang Dong
2017-04-20 20:37:42 +08:00
committed by Jianxin Pan
parent 73f330b0b8
commit 2286b5158a
35 changed files with 20741 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
MAINTAINERS
View File

@@ -13817,3 +13817,22 @@ F: arch/arm/boot/dts/amlogic/meson8b_m400.dts
AMLOGIC LOCAL TIMER
M: Jianxin Pan <jianxin.pan@amlogic.com>
F: drivers/amlogic/clocksource
AMLOGIC AMVECM, PQ, HDR
M: Mingliang Dong <mingliang.dong@amlogic.com>
F: drivers/amlogic/media/enhancement/amvecm/amcm.c
F: drivers/amlogic/media/enhancement/amvecm/amcm.h
F: drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h
F: drivers/amlogic/media/enhancement/amvecm/amcsc.c
F: drivers/amlogic/media/enhancement/amvecm/amcsc.h
F: drivers/amlogic/media/enhancement/amvecm/amdolby_vision.c
F: drivers/amlogic/media/enhancement/amvecm/amve.c
F: drivers/amlogic/media/enhancement/amvecm/amve.h
F: drivers/amlogic/media/enhancement/amvecm/amve_gamma_table.h
F: drivers/amlogic/media/enhancement/amvecm/amvecm.c
F: drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h
F: drivers/amlogic/media/enhancement/amvecm/Kconfig
F: drivers/amlogic/media/enhancement/amvecm/Makefile
F: drivers/amlogic/media/enhancement/amvecm/dolby_vision/*
F: drivers/amlogic/media/enhancement/amvecm/arch/*
F: include/linux/amlogic/media/amvecm/*

9
arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts
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@@ -1057,6 +1057,15 @@
tv_bit_mode = <1>;
};
amlvecm {
compatible = "amlogic, vecm";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <0>;/*1:enabel ;0:disable*/
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
};
unifykey{
compatible = "amlogic, unifykey";
status = "ok";

9
arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts
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@@ -1058,6 +1058,15 @@
tv_bit_mode = <1>;
};
amlvecm {
compatible = "amlogic, vecm";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <0>;/*1:enabel ;0:disable*/
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
};
unifykey{
compatible = "amlogic, unifykey";
status = "ok";

10
arch/arm64/boot/dts/amlogic/gxm_q200_2g.dts
View File

@@ -1077,6 +1077,16 @@
*/
tv_bit_mode = <1>;
};
amlvecm {
compatible = "amlogic, vecm";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <0>;/*1:enabel ;0:disable*/
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
};
unifykey{
compatible = "amlogic, unifykey";
status = "ok";

8
arch/arm64/boot/dts/amlogic/gxm_skt.dts
View File

@@ -877,6 +877,14 @@
tv_bit_mode = <1>;
};
amlvecm {
compatible = "amlogic, vecm";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <0>;/*1:enabel ;0:disable*/
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
};
partitions: partitions{
parts = <11>;

2
arch/arm64/configs/meson64_defconfig
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@@ -221,6 +221,8 @@ CONFIG_AMLOGIC_MEDIA_VIN=y
CONFIG_AMLOGIC_MEDIA_TVIN=y
CONFIG_AMLOGIC_MEDIA_VDIN=y
CONFIG_AMLOGIC_MEDIA_VIUIN=y
CONFIG_AMLOGIC_MEDIA_ENHANCEMENT=y
CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM=y
CONFIG_AMLOGIC_VIDEO_PROCESSOR=y
CONFIG_AMLOGIC_V4L_VIDEO=y
CONFIG_AMLOGIC_V4L_VIDEO2=y

1
drivers/amlogic/media/Kconfig
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@@ -47,6 +47,7 @@ source "drivers/amlogic/media/osd_ext/Kconfig"
source "drivers/amlogic/media/deinterlace/Kconfig"
source "drivers/amlogic/media/vin/Kconfig"
source "drivers/amlogic/media/video_processor/Kconfig"
source "drivers/amlogic/media/enhancement/Kconfig"
endif
endmenu

3
drivers/amlogic/media/Makefile
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@@ -6,4 +6,5 @@ obj-$(CONFIG_AMLOGIC_MEDIA_DRIVERS) += osd/
obj-$(CONFIG_AMLOGIC_MEDIA_DRIVERS) += osd_ext/
obj-$(CONFIG_AMLOGIC_MEDIA_DEINTERLACE) += deinterlace/
obj-$(CONFIG_AMLOGIC_MEDIA_VIN) += vin/
obj-$(CONFIG_AMLOGIC_MEDIA_DRIVERS) += video_processor/
obj-$(CONFIG_AMLOGIC_MEDIA_DRIVERS) += video_processor/
obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT) += enhancement/

20
drivers/amlogic/media/common/vfm/vframe_provider.c
View File

@@ -105,6 +105,26 @@ int vf_notify_provider(const char *receiver_name, int event_type, void *data)
}
EXPORT_SYMBOL(vf_notify_provider);
int vf_notify_provider_by_name(const char *provider_name, int event_type,
void *data)
{
int ret = -1;
struct vframe_provider_s *provider =
vf_get_provider_by_name(provider_name);
if (provider) {
if (provider->ops && provider->ops->event_cb) {
provider->ops->event_cb(event_type, data,
provider->op_arg);
ret = 0;
}
} else{
/* pr_err("Error: %s, fail to get provider of receiver %s\n",*/
/*__func__, receiver_name); */
}
return ret;
}
EXPORT_SYMBOL(vf_notify_provider_by_name);
void vf_provider_init(struct vframe_provider_s *prov,
const char *name, const struct vframe_operations_s *ops, void *op_arg)
{

16
drivers/amlogic/media/enhancement/Kconfig Normal file
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@@ -0,0 +1,16 @@
#
# Amlogic multimedia input configuration
#
menu "Amlogic Enhancement drivers"
config AMLOGIC_MEDIA_ENHANCEMENT
bool "Amlogic driver of enhancement"
depends on AMLOGIC_MEDIA_DRIVERS
default n
help
"Amlogic amvecm module init"
if AMLOGIC_MEDIA_ENHANCEMENT
source "drivers/amlogic/media/enhancement/amvecm/Kconfig"
endif
endmenu

1
drivers/amlogic/media/enhancement/Makefile Normal file
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@@ -0,0 +1 @@
obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) += amvecm/

14
drivers/amlogic/media/enhancement/amvecm/Kconfig Normal file
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@@ -0,0 +1,14 @@
#
# AMLOGIC amvecm devices configuration
#
comment "Amlogic VECM Drivers"
menu "Amlogic amvecm Driver"
config AMLOGIC_MEDIA_ENHANCEMENT_VECM
bool "Amlogic amvecm driver"
default n
help
"Amlogic amvecm module init"
endmenu

8
drivers/amlogic/media/enhancement/amvecm/Makefile Normal file
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@@ -0,0 +1,8 @@
#
# AMLOGIC VE & CM.
#
ccflags-y := -I$(PWD)/$(src)/dolby_vision/
obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) += am_vecm.o
am_vecm-objs := amve.o amcm.o amcsc.o amvecm.o amdolby_vision.o

512
drivers/amlogic/media/enhancement/amvecm/amcm.c Normal file
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@@ -0,0 +1,512 @@
/*
* drivers/amlogic/media/enhancement/amvecm/amcm.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
/* #include <mach/am_regs.h> */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/amlogic/media/amvecm/cm.h>
/* #include <linux/amlogic/aml_common.h> */
#include <linux/amlogic/media/vfm/vframe.h>
#include <linux/amlogic/media/amvecm/amvecm.h>
#include <linux/uaccess.h>
#include "arch/vpp_regs.h"
#include "arch/cm_regs.h"
#include "amcm.h"
#include "amcm_regmap.h"
#define pr_amcm_dbg(fmt, args...)\
do {\
if (debug_amcm)\
pr_info("AMCM: " fmt, ## args);\
} while (0)\
static bool debug_amcm;
module_param(debug_amcm, bool, 0664);
MODULE_PARM_DESC(debug_amcm, "\n debug_amcm\n");
static bool debug_regload;
module_param(debug_regload, bool, 0664);
MODULE_PARM_DESC(debug_regload, "\n debug_regload\n");
static int cm_level = 1;/* 0:optimize;1:enhancement */
module_param(cm_level, int, 0664);
MODULE_PARM_DESC(cm_level, "\n selcet cm lever\n");
int cm_en;/* 0:disabel;1:enable */
module_param(cm_en, int, 0664);
MODULE_PARM_DESC(cm_en, "\n enable or disable cm\n");
static unsigned int cm_width_limit = 50;/* vlsi adjust */
module_param(cm_width_limit, uint, 0664);
MODULE_PARM_DESC(cm_width_limit, "\n cm_width_limit\n");
#if 0
struct cm_region_s cm_region;
struct cm_top_s cm_top;
struct cm_demo_s cm_demo;
#endif
static int cm_level_last = 0xff;/* 0:optimize;1:enhancement */
unsigned int cm2_patch_flag;
unsigned int cm_size;
static struct am_regs_s amregs0;
static struct am_regs_s amregs1;
static struct am_regs_s amregs2;
static struct am_regs_s amregs3;
static struct am_regs_s amregs4;
static struct am_regs_s amregs5;
static struct sr1_regs_s sr1_regs[101];
/* extern unsigned int vecm_latch_flag; */
void am_set_regmap(struct am_regs_s *p)
{
unsigned short i;
unsigned int temp = 0;
unsigned short sr1_temp = 0;
for (i = 0; i < p->length; i++) {
switch (p->am_reg[i].type) {
case REG_TYPE_PHY:
break;
case REG_TYPE_CBUS:
if (p->am_reg[i].mask == 0xffffffff)
/* WRITE_CBUS_REG(p->am_reg[i].addr,*/
/* p->am_reg[i].val); */
aml_write_cbus(p->am_reg[i].addr,
p->am_reg[i].val);
else
/* WRITE_CBUS_REG(p->am_reg[i].addr, */
/* (READ_CBUS_REG(p->am_reg[i].addr) & */
/* (~(p->am_reg[i].mask))) | */
/* (p->am_reg[i].val & p->am_reg[i].mask)); */
aml_write_cbus(p->am_reg[i].addr,
(aml_read_cbus(p->am_reg[i].addr) &
(~(p->am_reg[i].mask))) |
(p->am_reg[i].val & p->am_reg[i].mask));
break;
case REG_TYPE_APB:
/* if (p->am_reg[i].mask == 0xffffffff) */
/* WRITE_APB_REG(p->am_reg[i].addr,*/
/* p->am_reg[i].val); */
/* else */
/* WRITE_APB_REG(p->am_reg[i].addr, */
/* (READ_APB_REG(p->am_reg[i].addr) & */
/* (~(p->am_reg[i].mask))) | */
/* (p->am_reg[i].val & p->am_reg[i].mask)); */
break;
case REG_TYPE_MPEG:
/* if (p->am_reg[i].mask == 0xffffffff) */
/* WRITE_MPEG_REG(p->am_reg[i].addr,*/
/* p->am_reg[i].val); */
/* else */
/* WRITE_MPEG_REG(p->am_reg[i].addr, */
/* (READ_MPEG_REG(p->am_reg[i].addr) & */
/* (~(p->am_reg[i].mask))) | */
/* (p->am_reg[i].val & p->am_reg[i].mask)); */
break;
case REG_TYPE_AXI:
/* if (p->am_reg[i].mask == 0xffffffff) */
/* WRITE_AXI_REG(p->am_reg[i].addr,*/
/* p->am_reg[i].val); */
/* else */
/* WRITE_AXI_REG(p->am_reg[i].addr, */
/* (READ_AXI_REG(p->am_reg[i].addr) & */
/* (~(p->am_reg[i].mask))) | */
/* (p->am_reg[i].val & p->am_reg[i].mask)); */
break;
case REG_TYPE_INDEX_VPPCHROMA:
/* add for vm2 demo frame size setting */
if (p->am_reg[i].addr == 0x20f) {
if ((p->am_reg[i].val & 0xff) != 0) {
cm2_patch_flag = p->am_reg[i].val;
p->am_reg[i].val =
p->am_reg[i].val & 0xffffff00;
} else
cm2_patch_flag = 0;
}
/* add for cm patch size config */
if ((p->am_reg[i].addr == 0x205) ||
(p->am_reg[i].addr == 0x209) ||
(p->am_reg[i].addr == 0x20a)) {
pr_amcm_dbg("[amcm]:%s REG_TYPE_INDEX_VPPCHROMA addr:0x%x",
__func__, p->am_reg[i].addr);
break;
}
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
p->am_reg[i].addr);
if (p->am_reg[i].mask == 0xffffffff)
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
p->am_reg[i].val);
else {
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
p->am_reg[i].addr);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
(temp & (~(p->am_reg[i].mask))) |
(p->am_reg[i].val & p->am_reg[i].mask));
}
break;
case REG_TYPE_INDEX_GAMMA:
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
break;
case REG_TYPE_INDEX_VPP_COEF:
if (((p->am_reg[i].addr&0xf) == 0) ||
((p->am_reg[i].addr&0xf) == 0x8)) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT,
p->am_reg[i].addr);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
p->am_reg[i].val);
} else
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT,
p->am_reg[i].val);
break;
/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESONG9TV) */
case REG_TYPE_VCBUS:
if (p->am_reg[i].mask == 0xffffffff)
/* WRITE_VCBUS_REG(p->am_reg[i].addr,*/
/* p->am_reg[i].val); */
aml_write_vcbus(p->am_reg[i].addr,
p->am_reg[i].val);
else
/* WRITE_VCBUS_REG(p->am_reg[i].addr, */
/* (READ_VCBUS_REG(p->am_reg[i].addr) & */
/* (~(p->am_reg[i].mask))) | */
/* (p->am_reg[i].val & p->am_reg[i].mask)); */
if ((is_meson_gxtvbb_cpu()) &&
(p->am_reg[i].addr >= 0x3280)
&& (p->am_reg[i].addr <= 0x32e4)) {
if (p->am_reg[i].addr == 0x32d7)
break;
sr1_temp = p->am_reg[i].addr - 0x3280;
sr1_regs[sr1_temp].addr =
p->am_reg[i].addr;
sr1_regs[sr1_temp].mask =
p->am_reg[i].mask;
sr1_regs[sr1_temp].val =
(sr1_regs[sr1_temp].val &
(~(p->am_reg[i].mask))) |
(p->am_reg[i].val & p->am_reg[i].mask);
sr1_reg_val[sr1_temp] =
sr1_regs[sr1_temp].val;
aml_write_vcbus(p->am_reg[i].addr,
sr1_regs[sr1_temp].val);
} else {
if (p->am_reg[i].addr == 0x1d26)
break;
aml_write_vcbus(p->am_reg[i].addr,
(aml_read_vcbus(p->am_reg[i].addr) &
(~(p->am_reg[i].mask))) |
(p->am_reg[i].val & p->am_reg[i].mask));
}
break;
/* #endif */
default:
break;
}
}
}
void amcm_disable(void)
{
int temp;
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
if (temp & 0x2) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, temp & 0xfffffffd);
}
}
void amcm_enable(void)
{
int temp;
if (!is_dolby_vision_enable()) {
if (!(READ_VPP_REG(VPP_MISC) & (0x1 << 28)))
WRITE_VPP_REG_BITS(VPP_MISC, 1, 28, 1);
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
if (!(temp & 0x2)) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, temp | 0x2);
}
}
}
void cm_regmap_latch(struct am_regs_s *am_regs, unsigned int reg_map)
{
am_set_regmap(am_regs);
vecm_latch_flag &= ~reg_map;
pr_amcm_dbg("\n[amcm..] load reg %d table OK!!!\n", reg_map);
}
void amcm_level_sel(unsigned int cm_level)
{
int temp;
if (cm_level == 1)
am_set_regmap(&cmreg_lever1);
else if (cm_level == 2)
am_set_regmap(&cmreg_lever2);
else if (cm_level == 3)
am_set_regmap(&cmreg_lever3);
else if (cm_level == 4)
am_set_regmap(&cmreg_enhancement);
else
am_set_regmap(&cmreg_optimize);
if (!is_dolby_vision_enable()) {
if (!(READ_VPP_REG(VPP_MISC) & (0x1 << 28)))
WRITE_VPP_REG_BITS(VPP_MISC, 1, 28, 1);
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT);
if (!(temp & 0x2)) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, temp | 0x2);
}
}
}
void cm2_frame_size_patch(unsigned int width, unsigned int height)
{
unsigned int vpp_size;
if (width < cm_width_limit)
amcm_disable();
if (!cm_en)
return;
vpp_size = width|(height << 16);
if (cm_size != vpp_size) {
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x205);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, vpp_size);
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x209);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, width<<15);
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x20a);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, height<<16);
cm_size = vpp_size;
pr_amcm_dbg("\n[amcm..]cm2_frame_patch: set cm2 framesize %x, ",
vpp_size);
pr_amcm_dbg("set demo mode %x\n", cm2_patch_flag);
}
}
/* set the frame size for cm2 demo*/
void cm2_frame_switch_patch(void)
{
WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x20f);
WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, cm2_patch_flag);
}
void cm_latch_process(void)
{
/*if ((vecm_latch_flag & FLAG_REG_MAP0) ||*/
/*(vecm_latch_flag & FLAG_REG_MAP1) ||*/
/*(vecm_latch_flag & FLAG_REG_MAP2) ||*/
/*(vecm_latch_flag & FLAG_REG_MAP3) ||*/
/*(vecm_latch_flag & FLAG_REG_MAP4) ||*/
/* (vecm_latch_flag & FLAG_REG_MAP5)){*/
do {
if (vecm_latch_flag & FLAG_REG_MAP0) {
cm_regmap_latch(&amregs0, FLAG_REG_MAP0);
break;
}
if (vecm_latch_flag & FLAG_REG_MAP1) {
cm_regmap_latch(&amregs1, FLAG_REG_MAP1);
break;
}
if (vecm_latch_flag & FLAG_REG_MAP2) {
cm_regmap_latch(&amregs2, FLAG_REG_MAP2);
break;
}
if (vecm_latch_flag & FLAG_REG_MAP3) {
cm_regmap_latch(&amregs3, FLAG_REG_MAP3);
break;
}
if (vecm_latch_flag & FLAG_REG_MAP4) {
cm_regmap_latch(&amregs4, FLAG_REG_MAP4);
break;
}
if (vecm_latch_flag & FLAG_REG_MAP5) {
cm_regmap_latch(&amregs5, FLAG_REG_MAP5);
break;
}
if ((cm2_patch_flag & 0xff) > 0)
cm2_frame_switch_patch();
} while (0);
if (cm_en && (cm_level_last != cm_level)) {
cm_level_last = cm_level;
if ((!is_meson_gxtvbb_cpu()) && (!is_meson_txl_cpu()))
amcm_level_sel(cm_level);
amcm_enable();
pr_amcm_dbg("\n[amcm..] set cm2 load OK!!!\n");
} else if ((cm_en == 0) && (cm_level_last != 0xff)) {
cm_level_last = 0xff;
amcm_disable();/* CM manage disable */
}
}
static int amvecm_regmap_info(struct am_regs_s *p)
{
unsigned short i;
for (i = 0; i < p->length; i++) {
switch (p->am_reg[i].type) {
case REG_TYPE_PHY:
pr_info("%s:%d bus type: phy...\n", __func__, i);
break;
case REG_TYPE_CBUS:
pr_info("%s:%-3d cbus: 0x%-4x=0x%-8x (%-5u)=(%-10u)",
__func__, i, p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask));
pr_info(" mask=%-8x(%u)\n",
p->am_reg[i].mask,
p->am_reg[i].mask);
break;
case REG_TYPE_APB:
pr_info("%s:%-3d apb: 0x%-4x=0x%-8x (%-5u)=(%-10u)",
__func__, i, p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask));
pr_info(" mask=%-8x(%u)\n",
p->am_reg[i].mask,
p->am_reg[i].mask);
break;
case REG_TYPE_MPEG:
pr_info("%s:%-3d mpeg: 0x%-4x=0x%-8x (%-5u)=(%-10u)",
__func__, i, p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask));
pr_info(" mask=%-8x(%u)\n",
p->am_reg[i].mask,
p->am_reg[i].mask);
break;
case REG_TYPE_AXI:
pr_info("%s:%-3d axi: 0x%-4x=0x%-8x (%-5u)=(%-10u)",
__func__, i, p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask));
pr_info(" mask=%-8x(%u)\n",
p->am_reg[i].mask,
p->am_reg[i].mask);
break;
case REG_TYPE_INDEX_VPPCHROMA:
pr_info("%s:%-3d chroma: 0x%-4x=0x%-8x (%-5u)=(%-10u)",
__func__, i, p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask));
pr_info(" mask=%-8x(%u)\n",
p->am_reg[i].mask,
p->am_reg[i].mask);
break;
case REG_TYPE_INDEX_GAMMA:
pr_info("%s:%-3d bus type: REG_TYPE_INDEX_GAMMA...\n",
__func__, i);
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
pr_info("%s:%-3d bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS...\n",
__func__, i);
break;
case REG_TYPE_INDEX_VPP_COEF:
pr_info("%s:%-3d vpp coef: 0x%-4x=0x%-8x (%-5u)=(%-10u)",
__func__, i, p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask));
pr_info(" mask=%-8x(%u)\n",
p->am_reg[i].mask,
p->am_reg[i].mask);
break;
case REG_TYPE_VCBUS:
pr_info("%s:%-3d vcbus: 0x%-4x=0x%-8x (%-5u)=(%-10u)",
__func__, i, p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask));
pr_info(" mask=%-8x(%u)\n", p->am_reg[i].mask,
p->am_reg[i].mask);
break;
default:
pr_info("%s:%3d bus type error!!!bustype = 0x%x...\n",
__func__, i, p->am_reg[i].type);
break;
}
}
return 0;
}
static long amvecm_regmap_set(struct am_regs_s *regs,
struct am_regs_s *arg, unsigned int reg_map)
{
int ret = 0;
if (!(memcpy(regs, arg, sizeof(struct am_regs_s)))) {
pr_amcm_dbg(
"[amcm..]0x%x load reg errors: can't get buffer length\n",
reg_map);
return -EFAULT;
}
if (!regs->length || (regs->length > am_reg_size)) {
pr_amcm_dbg(
"[amcm..]0x%x load regs error: buf length error!!!, length=0x%x\n",
reg_map, regs->length);
return -EINVAL;
}
pr_amcm_dbg("\n[amcm..]0x%x reg length=0x%x ......\n",
reg_map, regs->length);
if (debug_regload)
amvecm_regmap_info(regs);
vecm_latch_flag |= reg_map;
return ret;
}
int cm_load_reg(struct am_regs_s *arg)
{
int ret = 0;
/*force set cm size to 0,enable check vpp size*/
cm_size = 0;
if (!(vecm_latch_flag & FLAG_REG_MAP0))
ret = amvecm_regmap_set(&amregs0, arg, FLAG_REG_MAP0);
else if (!(vecm_latch_flag & FLAG_REG_MAP1))
ret = amvecm_regmap_set(&amregs1, arg, FLAG_REG_MAP1);
else if (!(vecm_latch_flag & FLAG_REG_MAP2))
ret = amvecm_regmap_set(&amregs2, arg, FLAG_REG_MAP2);
else if (!(vecm_latch_flag & FLAG_REG_MAP3))
ret = amvecm_regmap_set(&amregs3, arg, FLAG_REG_MAP3);
else if (!(vecm_latch_flag & FLAG_REG_MAP4))
ret = amvecm_regmap_set(&amregs4, arg, FLAG_REG_MAP4);
else if (!(vecm_latch_flag & FLAG_REG_MAP5))
ret = amvecm_regmap_set(&amregs5, arg, FLAG_REG_MAP5);
return ret;
}

88
drivers/amlogic/media/enhancement/amvecm/amcm.h Normal file
View File

@@ -0,0 +1,88 @@
/*
* drivers/amlogic/media/enhancement/amvecm/amcm.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __AM_CM_H
#define __AM_CM_H
#include <linux/amlogic/media/vfm/vframe.h>
#include "linux/amlogic/media/amvecm/cm.h"
struct cm_regs_s {
unsigned int val:32;
unsigned int reg:14;
unsigned int port:2;
/* 0 NA NA direct access */
/* 1 VPP_CHROMA_ADDR_PORT */
/* VPP_CHROMA_DATA_PORT CM port registers */
/* 2 NA NA reserved */
/* 3 NA NA reserved */
unsigned int bit:5;
unsigned int wid:5;
unsigned int mode:1;
unsigned int rsv:5;
};
struct sr1_regs_s {
unsigned int addr;
unsigned int mask;
unsigned int val;
};
extern unsigned int vecm_latch_flag;
extern unsigned int cm_size;
extern unsigned int cm2_patch_flag;
extern int cm_en; /* 0:disabel;1:enable */
extern int dnlp_en;/*0:disabel;1:enable */
extern unsigned int sr1_reg_val[101];
/* *********************************************************************** */
/* *** IOCTL-oriented functions ****************************************** */
/* *********************************************************************** */
void am_set_regmap(struct am_regs_s *p);
extern void amcm_disable(void);
extern void amcm_enable(void);
extern void amcm_level_sel(unsigned int cm_level);
extern void cm2_frame_size_patch(unsigned int width, unsigned int height);
extern void cm2_frame_switch_patch(void);
extern void cm_latch_process(void);
extern int cm_load_reg(struct am_regs_s *arg);
/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8) */
/* #define WRITE_VPP_REG(x,val) */
/* WRITE_VCBUS_REG(x,val) */
/* #define WRITE_VPP_REG_BITS(x,val,start,length) */
/* WRITE_VCBUS_REG_BITS(x,val,start,length) */
/* #define READ_VPP_REG(x) */
/* READ_VCBUS_REG(x) */
/* #define READ_VPP_REG_BITS(x,start,length) */
/* READ_VCBUS_REG_BITS(x,start,length) */
/* #else */
/* #define WRITE_VPP_REG(x,val) */
/* WRITE_CBUS_REG(x,val) */
/* #define WRITE_VPP_REG_BITS(x,val,start,length) */
/* WRITE_CBUS_REG_BITS(x,val,start,length) */
/* #define READ_VPP_REG(x) */
/* READ_CBUS_REG(x) */
/* #define READ_VPP_REG_BITS(x,start,length) */
/* READ_CBUS_REG_BITS(x,start,length) */
/* #endif */
#endif

922
drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h Normal file
View File

@@ -0,0 +1,922 @@
/*
* drivers/amlogic/media/enhancement/amvecm/amcm_regmap.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __AM_CM_REGMAP_H
#define __AM_CM_REGMAP_H
#include <linux/amlogic/media/amvecm/cm.h>
static struct am_regs_s cmreg_lever1 = {
172,
{
/* optimize */
{REG_TYPE_INDEX_VPPCHROMA, 512, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 513, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 514, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 515, 0xffffffff, 134218752 },
{REG_TYPE_INDEX_VPPCHROMA, 516, 0xffffffff, 144 },
{REG_TYPE_INDEX_VPPCHROMA, 518, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 519, 0xffffffff, 33554432 },
{REG_TYPE_INDEX_VPPCHROMA, 520, 0xffffffff, 118 },
{REG_TYPE_INDEX_VPPCHROMA, 521, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 522, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 527, 0xf, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 517, 0xffffffff, 70715263 },
{REG_TYPE_INDEX_VPP_COEF, 256, 0xffffffff, 532992 },
{REG_TYPE_INDEX_VPP_COEF, 257, 0xffffffff, 0xf3f600af },
{REG_TYPE_INDEX_VPP_COEF, 258, 0xffffffff, 0xe3000000 },
{REG_TYPE_INDEX_VPP_COEF, 259, 0xffffffff, 240 },
{REG_TYPE_INDEX_VPP_COEF, 260, 0xffffffff, 63506 },
{REG_TYPE_INDEX_VPP_COEF, 264, 0xffffffff, 16650496 },
{REG_TYPE_INDEX_VPP_COEF, 265, 0xffffffff, 249 },
{REG_TYPE_INDEX_VPP_COEF, 266, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 267, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 268, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 272, 0xffffffff, 135936 },
{REG_TYPE_INDEX_VPP_COEF, 273, 0xffffffff, 253 },
{REG_TYPE_INDEX_VPP_COEF, 274, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 275, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 276, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 280, 0xffffffff, 0xf3f11300 },
{REG_TYPE_INDEX_VPP_COEF, 281, 0xffffffff, 214 },
{REG_TYPE_INDEX_VPP_COEF, 282, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 283, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 284, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 288, 0xffffffff, 0xede91300 },
{REG_TYPE_INDEX_VPP_COEF, 289, 0xffffffff, 177 },
{REG_TYPE_INDEX_VPP_COEF, 290, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 291, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 292, 0xffffffff, 15660544 },
{REG_TYPE_INDEX_VPP_COEF, 296, 0xffffffff, 0xe9e61100 },
{REG_TYPE_INDEX_VPP_COEF, 297, 0xffffffff, 184 },
{REG_TYPE_INDEX_VPP_COEF, 298, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 299, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 300, 0xffffffff, 15464448 },
{REG_TYPE_INDEX_VPP_COEF, 304, 0xffffffff, 0xeff80f00 },
{REG_TYPE_INDEX_VPP_COEF, 305, 0xffffffff, 232 },
{REG_TYPE_INDEX_VPP_COEF, 306, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 307, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 308, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 312, 0xffffffff, 0xf60a0d00 },
{REG_TYPE_INDEX_VPP_COEF, 313, 0xffffffff, 245 },
{REG_TYPE_INDEX_VPP_COEF, 314, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 315, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 316, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 320, 0xffffffff, 526848 },
{REG_TYPE_INDEX_VPP_COEF, 321, 0xffffffff, 238 },
{REG_TYPE_INDEX_VPP_COEF, 322, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 323, 0xffffffff, 10 },
{REG_TYPE_INDEX_VPP_COEF, 324, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 328, 0xffffffff, 527616 },
{REG_TYPE_INDEX_VPP_COEF, 329, 0xffffffff, 134742245 },
{REG_TYPE_INDEX_VPP_COEF, 330, 0xffffffff, 167903232 },
{REG_TYPE_INDEX_VPP_COEF, 331, 0xffffffff, 21 },
{REG_TYPE_INDEX_VPP_COEF, 332, 0xffffffff, 3328 },
{REG_TYPE_INDEX_VPP_COEF, 336, 0xffffffff, 397056 },
{REG_TYPE_INDEX_VPP_COEF, 337, 0xffffffff, 0xf80d00da },
{REG_TYPE_INDEX_VPP_COEF, 338, 0xffffffff, 0xf80500fb },
{REG_TYPE_INDEX_VPP_COEF, 339, 0xffffffff, 2 },
{REG_TYPE_INDEX_VPP_COEF, 340, 0xffffffff, 132357 },
{REG_TYPE_INDEX_VPP_COEF, 344, 0xffffffff, 526848 },
{REG_TYPE_INDEX_VPP_COEF, 345, 0xffffffff, 0xfb0a00c7 },
{REG_TYPE_INDEX_VPP_COEF, 346, 0xffffffff, 0xf6020002 },
{REG_TYPE_INDEX_VPP_COEF, 347, 0xffffffff, 251 },
{REG_TYPE_INDEX_VPP_COEF, 348, 0xffffffff, 16646656 },
{REG_TYPE_INDEX_VPP_COEF, 352, 0xffffffff, 657408 },
{REG_TYPE_INDEX_VPP_COEF, 353, 0xffffffff, 327857 },
{REG_TYPE_INDEX_VPP_COEF, 354, 0xffffffff, 0xf6050000 },
{REG_TYPE_INDEX_VPP_COEF, 355, 0xffffffff, 2 },
{REG_TYPE_INDEX_VPP_COEF, 356, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 360, 0xffffffff, 526336 },
{REG_TYPE_INDEX_VPP_COEF, 361, 0xffffffff, 162 },
{REG_TYPE_INDEX_VPP_COEF, 362, 0xffffffff, 0xf600f600 },
{REG_TYPE_INDEX_VPP_COEF, 363, 0xffffffff, 254 },
{REG_TYPE_INDEX_VPP_COEF, 364, 0xffffffff, 33554432 },
{REG_TYPE_INDEX_VPP_COEF, 368, 0xffffffff, 986368 },
{REG_TYPE_INDEX_VPP_COEF, 369, 0xffffffff, 166 },
{REG_TYPE_INDEX_VPP_COEF, 370, 0xffffffff, 0xf300eef6 },
{REG_TYPE_INDEX_VPP_COEF, 371, 0xffffffff, 243 },
{REG_TYPE_INDEX_VPP_COEF, 372, 0xffffffff, 0xfb050000 },
{REG_TYPE_INDEX_VPP_COEF, 376, 0xffffffff, 34541312 },
{REG_TYPE_INDEX_VPP_COEF, 377, 0xffffffff, 83886277 },
{REG_TYPE_INDEX_VPP_COEF, 378, 0xffffffff, 0xfbfef8f8 },
{REG_TYPE_INDEX_VPP_COEF, 379, 0xffffffff, 246 },
{REG_TYPE_INDEX_VPP_COEF, 380, 0xffffffff, 0xf8080200 },
{REG_TYPE_INDEX_VPP_COEF, 384, 0xffffffff, 286331136 },
{REG_TYPE_INDEX_VPP_COEF, 385, 0xffffffff, 353698041 },
{REG_TYPE_INDEX_VPP_COEF, 386, 0xffffffff, 168427768 },
{REG_TYPE_INDEX_VPP_COEF, 387, 0xffffffff, 13 },
{REG_TYPE_INDEX_VPP_COEF, 388, 0xffffffff, 0xfb081000 },
{REG_TYPE_INDEX_VPP_COEF, 392, 0xffffffff, 218960128 },
{REG_TYPE_INDEX_VPP_COEF, 393, 0xffffffff, 674758687 },
{REG_TYPE_INDEX_VPP_COEF, 394, 0xffffffff, 573177856 },
{REG_TYPE_INDEX_VPP_COEF, 395, 0xffffffff, 21 },
{REG_TYPE_INDEX_VPP_COEF, 396, 0xffffffff, 854766 },
{REG_TYPE_INDEX_VPP_COEF, 400, 0xffffffff, 168430080 },
{REG_TYPE_INDEX_VPP_COEF, 401, 0xffffffff, 809304110 },
{REG_TYPE_INDEX_VPP_COEF, 402, 0xffffffff, 674234389 },
{REG_TYPE_INDEX_VPP_COEF, 403, 0xffffffff, 13 },
{REG_TYPE_INDEX_VPP_COEF, 404, 0xffffffff, 716515 },
{REG_TYPE_INDEX_VPP_COEF, 408, 0xffffffff, 134745344 },
{REG_TYPE_INDEX_VPP_COEF, 409, 0xffffffff, 807731246 },
{REG_TYPE_INDEX_VPP_COEF, 410, 0xffffffff, 403308562 },
{REG_TYPE_INDEX_VPP_COEF, 411, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 412, 0xffffffff, 59590 },
{REG_TYPE_INDEX_VPP_COEF, 416, 0xffffffff, 67504640 },
{REG_TYPE_INDEX_VPP_COEF, 417, 0xffffffff, 269484072 },
{REG_TYPE_INDEX_VPP_COEF, 418, 0xffffffff, 182845440 },
{REG_TYPE_INDEX_VPP_COEF, 419, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 420, 0xffffffff, 61139 },
{REG_TYPE_INDEX_VPP_COEF, 424, 0xffffffff, 396544 },
{REG_TYPE_INDEX_VPP_COEF, 425, 0xffffffff, 134217757 },
{REG_TYPE_INDEX_VPP_COEF, 426, 0xffffffff, 0xfb0b0000 },
{REG_TYPE_INDEX_VPP_COEF, 427, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 428, 0xffffffff, 246 },
{REG_TYPE_INDEX_VPP_COEF, 432, 0xffffffff, 527616 },
{REG_TYPE_INDEX_VPP_COEF, 433, 0xffffffff, 12 },
{REG_TYPE_INDEX_VPP_COEF, 434, 0xffffffff, 15597568 },
{REG_TYPE_INDEX_VPP_COEF, 435, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 436, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 440, 0xffffffff, 658688 },
{REG_TYPE_INDEX_VPP_COEF, 441, 0xffffffff, 7 },
{REG_TYPE_INDEX_VPP_COEF, 442, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 443, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 444, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 448, 0xffffffff, 986880 },
{REG_TYPE_INDEX_VPP_COEF, 449, 0xffffffff, 255 },
{REG_TYPE_INDEX_VPP_COEF, 450, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 451, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 452, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 456, 0xffffffff, 219811584 },
{REG_TYPE_INDEX_VPP_COEF, 457, 0xffffffff, 238 },
{REG_TYPE_INDEX_VPP_COEF, 458, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 459, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 460, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 464, 0xffffffff, 287183104 },
{REG_TYPE_INDEX_VPP_COEF, 465, 0xffffffff, 197 },
{REG_TYPE_INDEX_VPP_COEF, 466, 0xffffffff, 0xf3000000 },
{REG_TYPE_INDEX_VPP_COEF, 467, 0xffffffff, 246 },
{REG_TYPE_INDEX_VPP_COEF, 468, 0xffffffff, 0xfb000000 },
{REG_TYPE_INDEX_VPP_COEF, 472, 0xffffffff, 219943168 },
{REG_TYPE_INDEX_VPP_COEF, 473, 0xffffffff, 169 },
{REG_TYPE_INDEX_VPP_COEF, 474, 0xffffffff, 0xf0000000 },
{REG_TYPE_INDEX_VPP_COEF, 475, 0xffffffff, 232 },
{REG_TYPE_INDEX_VPP_COEF, 476, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 480, 0xffffffff, 1707264 },
{REG_TYPE_INDEX_VPP_COEF, 481, 0xffffffff, 0xfb0000ab },
{REG_TYPE_INDEX_VPP_COEF, 482, 0xffffffff, 0xe300f3f3 },
{REG_TYPE_INDEX_VPP_COEF, 483, 0xffffffff, 219 },
{REG_TYPE_INDEX_VPP_COEF, 484, 0xffffffff, 15597568 },
{REG_TYPE_INDEX_VPP_COEF, 488, 0xffffffff, 1509888 },
{REG_TYPE_INDEX_VPP_COEF, 489, 0xffffffff, 0xf30000b6 },
{REG_TYPE_INDEX_VPP_COEF, 490, 0xffffffff, 0xd800e8e3 },
{REG_TYPE_INDEX_VPP_COEF, 491, 0xffffffff, 222 },
{REG_TYPE_INDEX_VPP_COEF, 492, 0xffffffff, 14876680 },
{REG_TYPE_INDEX_VPP_COEF, 496, 0xffffffff, 1117440 },
{REG_TYPE_INDEX_VPP_COEF, 497, 0xffffffff, 0xf3fb00ba },
{REG_TYPE_INDEX_VPP_COEF, 498, 0xffffffff, 0xd300ebe6 },
{REG_TYPE_INDEX_VPP_COEF, 499, 0xffffffff, 232 },
{REG_TYPE_INDEX_VPP_COEF, 500, 0xffffffff, 15661840 },
{REG_TYPE_INDEX_VPP_COEF, 504, 0xffffffff, 989696 },
{REG_TYPE_INDEX_VPP_COEF, 505, 0xffffffff, 0xf6f800b6 },
{REG_TYPE_INDEX_VPP_COEF, 506, 0xffffffff, 0xe600f3f3 },
{REG_TYPE_INDEX_VPP_COEF, 507, 0xffffffff, 235 },
{REG_TYPE_INDEX_VPP_COEF, 508, 0xffffffff, 18 },
{0}
}
};
static struct am_regs_s cmreg_lever2 = {
172,
{
/* optimize */
{REG_TYPE_INDEX_VPPCHROMA, 512, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 513, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 514, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 515, 0xffffffff, 134218752 },
{REG_TYPE_INDEX_VPPCHROMA, 516, 0xffffffff, 144 },
{REG_TYPE_INDEX_VPPCHROMA, 518, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 519, 0xffffffff, 33554432 },
{REG_TYPE_INDEX_VPPCHROMA, 520, 0xffffffff, 122 },
{REG_TYPE_INDEX_VPPCHROMA, 521, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 522, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 527, 0xf, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 517, 0xffffffff, 70715263 },
{REG_TYPE_INDEX_VPP_COEF, 256, 0xffffffff, 2840064 },
{REG_TYPE_INDEX_VPP_COEF, 257, 0xffffffff, 12 },
{REG_TYPE_INDEX_VPP_COEF, 258, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 259, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 260, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 264, 0xffffffff, 2708992 },
{REG_TYPE_INDEX_VPP_COEF, 265, 0xffffffff, 31 },
{REG_TYPE_INDEX_VPP_COEF, 266, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 267, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 268, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 272, 0xffffffff, 2708992 },
{REG_TYPE_INDEX_VPP_COEF, 273, 0xffffffff, 51 },
{REG_TYPE_INDEX_VPP_COEF, 274, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 275, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 276, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 280, 0xffffffff, 2840064 },
{REG_TYPE_INDEX_VPP_COEF, 281, 0xffffffff, 63 },
{REG_TYPE_INDEX_VPP_COEF, 282, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 283, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 284, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 288, 0xffffffff, 2840064 },
{REG_TYPE_INDEX_VPP_COEF, 289, 0xffffffff, 63 },
{REG_TYPE_INDEX_VPP_COEF, 290, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 291, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 292, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 296, 0xffffffff, 2708992 },
{REG_TYPE_INDEX_VPP_COEF, 297, 0xffffffff, 63 },
{REG_TYPE_INDEX_VPP_COEF, 298, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 299, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 300, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 304, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 305, 0xffffffff, 63 },
{REG_TYPE_INDEX_VPP_COEF, 306, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 307, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 308, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 312, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 313, 0xffffffff, 51 },
{REG_TYPE_INDEX_VPP_COEF, 314, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 315, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 316, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 320, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 321, 0xffffffff, 9 },
{REG_TYPE_INDEX_VPP_COEF, 322, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 323, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 324, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 328, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 329, 0xffffffff, 234 },
{REG_TYPE_INDEX_VPP_COEF, 330, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 331, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 332, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 336, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 337, 0xffffffff, 212 },
{REG_TYPE_INDEX_VPP_COEF, 338, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 339, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 340, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 344, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 345, 0xffffffff, 197 },
{REG_TYPE_INDEX_VPP_COEF, 346, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 347, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 348, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 352, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 353, 0xffffffff, 193 },
{REG_TYPE_INDEX_VPP_COEF, 354, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 355, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 356, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 360, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 361, 0xffffffff, 203 },
{REG_TYPE_INDEX_VPP_COEF, 362, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 363, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 364, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 368, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 369, 0xffffffff, 214 },
{REG_TYPE_INDEX_VPP_COEF, 370, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 371, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 372, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 376, 0xffffffff, 2708992 },
{REG_TYPE_INDEX_VPP_COEF, 377, 0xffffffff, 219 },
{REG_TYPE_INDEX_VPP_COEF, 378, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 379, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 380, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 384, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 385, 0xffffffff, 236 },
{REG_TYPE_INDEX_VPP_COEF, 386, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 387, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 388, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 392, 0xffffffff, 2708992 },
{REG_TYPE_INDEX_VPP_COEF, 393, 0xffffffff, 249 },
{REG_TYPE_INDEX_VPP_COEF, 394, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 395, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 396, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 400, 0xffffffff, 2708992 },
{REG_TYPE_INDEX_VPP_COEF, 401, 0xffffffff, 3 },
{REG_TYPE_INDEX_VPP_COEF, 402, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 403, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 404, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 408, 0xffffffff, 2708992 },
{REG_TYPE_INDEX_VPP_COEF, 409, 0xffffffff, 9 },
{REG_TYPE_INDEX_VPP_COEF, 410, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 411, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 412, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 416, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 417, 0xffffffff, 12 },
{REG_TYPE_INDEX_VPP_COEF, 418, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 419, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 420, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 424, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 425, 0xffffffff, 14 },
{REG_TYPE_INDEX_VPP_COEF, 426, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 427, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 428, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 432, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 433, 0xffffffff, 12 },
{REG_TYPE_INDEX_VPP_COEF, 434, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 435, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 436, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 440, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 441, 0xffffffff, 7 },
{REG_TYPE_INDEX_VPP_COEF, 442, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 443, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 444, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 448, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 449, 0xffffffff, 251 },
{REG_TYPE_INDEX_VPP_COEF, 450, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 451, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 452, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 456, 0xffffffff, 2708480 },
{REG_TYPE_INDEX_VPP_COEF, 457, 0xffffffff, 242 },
{REG_TYPE_INDEX_VPP_COEF, 458, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 459, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 460, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 464, 0xffffffff, 36262912 },
{REG_TYPE_INDEX_VPP_COEF, 465, 0xffffffff, 238 },
{REG_TYPE_INDEX_VPP_COEF, 466, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 467, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 468, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 472, 0xffffffff, 69817344 },
{REG_TYPE_INDEX_VPP_COEF, 473, 0xffffffff, 245 },
{REG_TYPE_INDEX_VPP_COEF, 474, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 475, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 476, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 480, 0xffffffff, 136926208 },
{REG_TYPE_INDEX_VPP_COEF, 481, 0xffffffff, 1 },
{REG_TYPE_INDEX_VPP_COEF, 482, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 483, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 484, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 488, 0xffffffff, 136926208 },
{REG_TYPE_INDEX_VPP_COEF, 489, 0xffffffff, 5 },
{REG_TYPE_INDEX_VPP_COEF, 490, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 491, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 492, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 496, 0xffffffff, 136926208 },
{REG_TYPE_INDEX_VPP_COEF, 497, 0xffffffff, 5 },
{REG_TYPE_INDEX_VPP_COEF, 498, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 499, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 500, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 504, 0xffffffff, 69817344 },
{REG_TYPE_INDEX_VPP_COEF, 505, 0xffffffff, 7 },
{REG_TYPE_INDEX_VPP_COEF, 506, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 507, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 508, 0xffffffff, 0 },
{0}
}
};
static struct am_regs_s cmreg_lever3 = {
172,
{
/* optimize */
{REG_TYPE_INDEX_VPPCHROMA, 512, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 513, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 514, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 515, 0xffffffff, 134218752 },
{REG_TYPE_INDEX_VPPCHROMA, 516, 0xffffffff, 144 },
{REG_TYPE_INDEX_VPPCHROMA, 518, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPPCHROMA, 519, 0xffffffff, 33554432 },
{REG_TYPE_INDEX_VPPCHROMA, 520, 0xffffffff, 118 },
{REG_TYPE_INDEX_VPPCHROMA, 521, 0xffffffff, 62914560 },
{REG_TYPE_INDEX_VPPCHROMA, 522, 0xffffffff, 70778880 },
{REG_TYPE_INDEX_VPPCHROMA, 527, 0xf, 1 },
{REG_TYPE_INDEX_VPPCHROMA, 517, 0xffffffff, 70780799 },
{REG_TYPE_INDEX_VPP_COEF, 256, 0xffffffff, 16648704 },
{REG_TYPE_INDEX_VPP_COEF, 257, 0xffffffff, 0xf3f6000b },
{REG_TYPE_INDEX_VPP_COEF, 258, 0xffffffff, 0xe3000000 },
{REG_TYPE_INDEX_VPP_COEF, 259, 0xffffffff, 240 },
{REG_TYPE_INDEX_VPP_COEF, 260, 0xffffffff, 63742 },
{REG_TYPE_INDEX_VPP_COEF, 264, 0xffffffff, 16650496 },
{REG_TYPE_INDEX_VPP_COEF, 265, 0xffffffff, 14 },
{REG_TYPE_INDEX_VPP_COEF, 266, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 267, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 268, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 272, 0xffffffff, 135936 },
{REG_TYPE_INDEX_VPP_COEF, 273, 0xffffffff, 253 },
{REG_TYPE_INDEX_VPP_COEF, 274, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 275, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 276, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 280, 0xffffffff, 0xf3f11300 },
{REG_TYPE_INDEX_VPP_COEF, 281, 0xffffffff, 214 },
{REG_TYPE_INDEX_VPP_COEF, 282, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 283, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 284, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 288, 0xffffffff, 0xede91300 },
{REG_TYPE_INDEX_VPP_COEF, 289, 0xffffffff, 177 },
{REG_TYPE_INDEX_VPP_COEF, 290, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 291, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 292, 0xffffffff, 15660544 },
{REG_TYPE_INDEX_VPP_COEF, 296, 0xffffffff, 0xe9e61100 },
{REG_TYPE_INDEX_VPP_COEF, 297, 0xffffffff, 184 },
{REG_TYPE_INDEX_VPP_COEF, 298, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 299, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 300, 0xffffffff, 15464448 },
{REG_TYPE_INDEX_VPP_COEF, 304, 0xffffffff, 0xeff80f00 },
{REG_TYPE_INDEX_VPP_COEF, 305, 0xffffffff, 232 },
{REG_TYPE_INDEX_VPP_COEF, 306, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 307, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 308, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 312, 0xffffffff, 0xf60a0d00 },
{REG_TYPE_INDEX_VPP_COEF, 313, 0xffffffff, 5 },
{REG_TYPE_INDEX_VPP_COEF, 314, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 315, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 316, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 320, 0xffffffff, 526848 },
{REG_TYPE_INDEX_VPP_COEF, 321, 0xffffffff, 5 },
{REG_TYPE_INDEX_VPP_COEF, 322, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 323, 0xffffffff, 10 },
{REG_TYPE_INDEX_VPP_COEF, 324, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 328, 0xffffffff, 526848 },
{REG_TYPE_INDEX_VPP_COEF, 329, 0xffffffff, 134742265 },
{REG_TYPE_INDEX_VPP_COEF, 330, 0xffffffff, 167903232 },
{REG_TYPE_INDEX_VPP_COEF, 331, 0xffffffff, 21 },
{REG_TYPE_INDEX_VPP_COEF, 332, 0xffffffff, 3328 },
{REG_TYPE_INDEX_VPP_COEF, 336, 0xffffffff, 131072 },
{REG_TYPE_INDEX_VPP_COEF, 337, 0xffffffff, 0xf80d00ea },
{REG_TYPE_INDEX_VPP_COEF, 338, 0xffffffff, 0xf80500fb },
{REG_TYPE_INDEX_VPP_COEF, 339, 0xffffffff, 2 },
{REG_TYPE_INDEX_VPP_COEF, 340, 0xffffffff, 132357 },
{REG_TYPE_INDEX_VPP_COEF, 344, 0xffffffff, 131584 },
{REG_TYPE_INDEX_VPP_COEF, 345, 0xffffffff, 0xfb0100da },
{REG_TYPE_INDEX_VPP_COEF, 346, 0xffffffff, 0xf6020002 },
{REG_TYPE_INDEX_VPP_COEF, 347, 0xffffffff, 251 },
{REG_TYPE_INDEX_VPP_COEF, 348, 0xffffffff, 16646656 },
{REG_TYPE_INDEX_VPP_COEF, 352, 0xffffffff, 657408 },
{REG_TYPE_INDEX_VPP_COEF, 353, 0xffffffff, 327872 },
{REG_TYPE_INDEX_VPP_COEF, 354, 0xffffffff, 0xf6050000 },
{REG_TYPE_INDEX_VPP_COEF, 355, 0xffffffff, 2 },
{REG_TYPE_INDEX_VPP_COEF, 356, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 360, 0xffffffff, 526336 },
{REG_TYPE_INDEX_VPP_COEF, 361, 0xffffffff, 175 },
{REG_TYPE_INDEX_VPP_COEF, 362, 0xffffffff, 0xf600f600 },
{REG_TYPE_INDEX_VPP_COEF, 363, 0xffffffff, 254 },
{REG_TYPE_INDEX_VPP_COEF, 364, 0xffffffff, 33554432 },
{REG_TYPE_INDEX_VPP_COEF, 368, 0xffffffff, 986368 },
{REG_TYPE_INDEX_VPP_COEF, 369, 0xffffffff, 169 },
{REG_TYPE_INDEX_VPP_COEF, 370, 0xffffffff, 0xf300eef6 },
{REG_TYPE_INDEX_VPP_COEF, 371, 0xffffffff, 243 },
{REG_TYPE_INDEX_VPP_COEF, 372, 0xffffffff, 0xfb050000 },
{REG_TYPE_INDEX_VPP_COEF, 376, 0xffffffff, 34541312 },
{REG_TYPE_INDEX_VPP_COEF, 377, 0xffffffff, 83886277 },
{REG_TYPE_INDEX_VPP_COEF, 378, 0xffffffff, 0xfbfef8f8 },
{REG_TYPE_INDEX_VPP_COEF, 379, 0xffffffff, 246 },
{REG_TYPE_INDEX_VPP_COEF, 380, 0xffffffff, 0xf8080200 },
{REG_TYPE_INDEX_VPP_COEF, 384, 0xffffffff, 135339520 },
{REG_TYPE_INDEX_VPP_COEF, 385, 0xffffffff, 353697836 },
{REG_TYPE_INDEX_VPP_COEF, 386, 0xffffffff, 168427768 },
{REG_TYPE_INDEX_VPP_COEF, 387, 0xffffffff, 13 },
{REG_TYPE_INDEX_VPP_COEF, 388, 0xffffffff, 0xfb080800 },
{REG_TYPE_INDEX_VPP_COEF, 392, 0xffffffff, 219356160 },
{REG_TYPE_INDEX_VPP_COEF, 393, 0xffffffff, 674758739 },
{REG_TYPE_INDEX_VPP_COEF, 394, 0xffffffff, 573177856 },
{REG_TYPE_INDEX_VPP_COEF, 395, 0xffffffff, 21 },
{REG_TYPE_INDEX_VPP_COEF, 396, 0xffffffff, 657920 },
{REG_TYPE_INDEX_VPP_COEF, 400, 0xffffffff, 219223808 },
{REG_TYPE_INDEX_VPP_COEF, 401, 0xffffffff, 809304160 },
{REG_TYPE_INDEX_VPP_COEF, 402, 0xffffffff, 674562069 },
{REG_TYPE_INDEX_VPP_COEF, 403, 0xffffffff, 13 },
{REG_TYPE_INDEX_VPP_COEF, 404, 0xffffffff, 657920 },
{REG_TYPE_INDEX_VPP_COEF, 408, 0xffffffff, 168629504 },
{REG_TYPE_INDEX_VPP_COEF, 409, 0xffffffff, 807731289 },
{REG_TYPE_INDEX_VPP_COEF, 410, 0xffffffff, 403308562 },
{REG_TYPE_INDEX_VPP_COEF, 411, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 412, 0xffffffff, 526848 },
{REG_TYPE_INDEX_VPP_COEF, 416, 0xffffffff, 395776 },
{REG_TYPE_INDEX_VPP_COEF, 417, 0xffffffff, 269484098 },
{REG_TYPE_INDEX_VPP_COEF, 418, 0xffffffff, 167772160 },
{REG_TYPE_INDEX_VPP_COEF, 419, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 420, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 424, 0xffffffff, 396544 },
{REG_TYPE_INDEX_VPP_COEF, 425, 0xffffffff, 134217757 },
{REG_TYPE_INDEX_VPP_COEF, 426, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 427, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 428, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 432, 0xffffffff, 527616 },
{REG_TYPE_INDEX_VPP_COEF, 433, 0xffffffff, 12 },
{REG_TYPE_INDEX_VPP_COEF, 434, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 435, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 436, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 440, 0xffffffff, 658688 },
{REG_TYPE_INDEX_VPP_COEF, 441, 0xffffffff, 7 },
{REG_TYPE_INDEX_VPP_COEF, 442, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 443, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 444, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 448, 0xffffffff, 986880 },
{REG_TYPE_INDEX_VPP_COEF, 449, 0xffffffff, 5 },
{REG_TYPE_INDEX_VPP_COEF, 450, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 451, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 452, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 456, 0xffffffff, 219811584 },
{REG_TYPE_INDEX_VPP_COEF, 457, 0xffffffff, 244 },
{REG_TYPE_INDEX_VPP_COEF, 458, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 459, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 460, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 464, 0xffffffff, 287183104 },
{REG_TYPE_INDEX_VPP_COEF, 465, 0xffffffff, 186 },
{REG_TYPE_INDEX_VPP_COEF, 466, 0xffffffff, 0xf3000000 },
{REG_TYPE_INDEX_VPP_COEF, 467, 0xffffffff, 246 },
{REG_TYPE_INDEX_VPP_COEF, 468, 0xffffffff, 0xfb000000 },
{REG_TYPE_INDEX_VPP_COEF, 472, 0xffffffff, 219944192 },
{REG_TYPE_INDEX_VPP_COEF, 473, 0xffffffff, 158 },
{REG_TYPE_INDEX_VPP_COEF, 474, 0xffffffff, 0xf0000000 },
{REG_TYPE_INDEX_VPP_COEF, 475, 0xffffffff, 232 },
{REG_TYPE_INDEX_VPP_COEF, 476, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 480, 0xffffffff, 1382912 },
{REG_TYPE_INDEX_VPP_COEF, 481, 0xffffffff, 0xfb0000a4 },
{REG_TYPE_INDEX_VPP_COEF, 482, 0xffffffff, 0xe300f3f3 },
{REG_TYPE_INDEX_VPP_COEF, 483, 0xffffffff, 219 },
{REG_TYPE_INDEX_VPP_COEF, 484, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 488, 0xffffffff, 1514496 },
{REG_TYPE_INDEX_VPP_COEF, 489, 0xffffffff, 0xf30000ba },
{REG_TYPE_INDEX_VPP_COEF, 490, 0xffffffff, 0xe600f3f0 },
{REG_TYPE_INDEX_VPP_COEF, 491, 0xffffffff, 222 },
{REG_TYPE_INDEX_VPP_COEF, 492, 0xffffffff, 0 },
{REG_TYPE_INDEX_VPP_COEF, 496, 0xffffffff, 1120000 },
{REG_TYPE_INDEX_VPP_COEF, 497, 0xffffffff, 0xf3fb00db },
{REG_TYPE_INDEX_VPP_COEF, 498, 0xffffffff, 0xe800f6ee },
{REG_TYPE_INDEX_VPP_COEF, 499, 0xffffffff, 232 },
{REG_TYPE_INDEX_VPP_COEF, 500, 0xffffffff, 64256 },
{REG_TYPE_INDEX_VPP_COEF, 504, 0xffffffff, 397056 },
{REG_TYPE_INDEX_VPP_COEF, 505, 0xffffffff, 0xf6f800f7 },
{REG_TYPE_INDEX_VPP_COEF, 506, 0xffffffff, 0xe60000f8 },
{REG_TYPE_INDEX_VPP_COEF, 507, 0xffffffff, 235 },
{REG_TYPE_INDEX_VPP_COEF, 508, 0xffffffff, 65278 },
{0}
}
};
static struct am_regs_s cmreg_optimize = {
172,
{
/* optimize */
{REG_TYPE_INDEX_VPPCHROMA, 0x200, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x201, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x202, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x203, 0xffffffff, 0x8000400},
{REG_TYPE_INDEX_VPPCHROMA, 0x204, 0xffffffff, 0x90 },
{REG_TYPE_INDEX_VPPCHROMA, 0x205, 0xffffffff, 0x437077f},
{REG_TYPE_INDEX_VPPCHROMA, 0x206, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x207, 0xffffffff, 0x1f60000},
{REG_TYPE_INDEX_VPPCHROMA, 0x208, 0xffffffff, 0x76 },
{REG_TYPE_INDEX_VPPCHROMA, 0x209, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x20a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x20f, 0xf, 0x0, },
{REG_TYPE_INDEX_VPP_COEF, 0x100, 0xffffffff, 0xa1100 },
{REG_TYPE_INDEX_VPP_COEF, 0x101, 0xffffffff, 0xc },
{REG_TYPE_INDEX_VPP_COEF, 0x102, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x103, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x104, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x108, 0xffffffff, 0xd1100 },
{REG_TYPE_INDEX_VPP_COEF, 0x109, 0xffffffff, 0x1f },
{REG_TYPE_INDEX_VPP_COEF, 0x10a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x10b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x10c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x110, 0xffffffff, 0xf1300 },
{REG_TYPE_INDEX_VPP_COEF, 0x111, 0xffffffff, 0x33 },
{REG_TYPE_INDEX_VPP_COEF, 0x112, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x113, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x114, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x118, 0xffffffff, 0xf1300 },
{REG_TYPE_INDEX_VPP_COEF, 0x119, 0xffffffff, 0x3f },
{REG_TYPE_INDEX_VPP_COEF, 0x11a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x11b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x11c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x120, 0xffffffff, 0xf1300 },
{REG_TYPE_INDEX_VPP_COEF, 0x121, 0xffffffff, 0x40 },
{REG_TYPE_INDEX_VPP_COEF, 0x122, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x123, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x124, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x128, 0xffffffff, 0xf1100 },
{REG_TYPE_INDEX_VPP_COEF, 0x129, 0xffffffff, 0x40 },
{REG_TYPE_INDEX_VPP_COEF, 0x12a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x12b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x12c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x130, 0xffffffff, 0xd0f00 },
{REG_TYPE_INDEX_VPP_COEF, 0x131, 0xffffffff, 0x3f },
{REG_TYPE_INDEX_VPP_COEF, 0x132, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x133, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x134, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x138, 0xffffffff, 0xa0d00 },
{REG_TYPE_INDEX_VPP_COEF, 0x139, 0xffffffff, 0x32 },
{REG_TYPE_INDEX_VPP_COEF, 0x13a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x13b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x13c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x140, 0xffffffff, 0x80a00 },
{REG_TYPE_INDEX_VPP_COEF, 0x141, 0xffffffff, 0x9 },
{REG_TYPE_INDEX_VPP_COEF, 0x142, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x143, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x144, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x148, 0xffffffff, 0x80a00 },
{REG_TYPE_INDEX_VPP_COEF, 0x149, 0xffffffff, 0xea },
{REG_TYPE_INDEX_VPP_COEF, 0x14a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x14b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x14c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x150, 0xffffffff, 0xa0a00 },
{REG_TYPE_INDEX_VPP_COEF, 0x151, 0xffffffff, 0xd4 },
{REG_TYPE_INDEX_VPP_COEF, 0x152, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x153, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x154, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x158, 0xffffffff, 0xa0800 },
{REG_TYPE_INDEX_VPP_COEF, 0x159, 0xffffffff, 0xc3 },
{REG_TYPE_INDEX_VPP_COEF, 0x15a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x15b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x15c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x160, 0xffffffff, 0xa0800 },
{REG_TYPE_INDEX_VPP_COEF, 0x161, 0xffffffff, 0xc0 },
{REG_TYPE_INDEX_VPP_COEF, 0x162, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x163, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x164, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x168, 0xffffffff, 0x80800 },
{REG_TYPE_INDEX_VPP_COEF, 0x169, 0xffffffff, 0xcb },
{REG_TYPE_INDEX_VPP_COEF, 0x16a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x16b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x16c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x170, 0xffffffff, 0x60800 },
{REG_TYPE_INDEX_VPP_COEF, 0x171, 0xffffffff, 0xd4 },
{REG_TYPE_INDEX_VPP_COEF, 0x172, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x173, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x174, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x178, 0xffffffff, 0x40600 },
{REG_TYPE_INDEX_VPP_COEF, 0x179, 0xffffffff, 0xdb },
{REG_TYPE_INDEX_VPP_COEF, 0x17a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x17b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x17c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x180, 0xffffffff, 0x60600 },
{REG_TYPE_INDEX_VPP_COEF, 0x181, 0xffffffff, 0xea },
{REG_TYPE_INDEX_VPP_COEF, 0x182, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x183, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x184, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x188, 0xffffffff, 0x60600 },
{REG_TYPE_INDEX_VPP_COEF, 0x189, 0xffffffff, 0xf7 },
{REG_TYPE_INDEX_VPP_COEF, 0x18a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x18b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x18c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x190, 0xffffffff, 0x60600 },
{REG_TYPE_INDEX_VPP_COEF, 0x191, 0xffffffff, 0x3 },
{REG_TYPE_INDEX_VPP_COEF, 0x192, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x193, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x194, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x198, 0xffffffff, 0x80800 },
{REG_TYPE_INDEX_VPP_COEF, 0x199, 0xffffffff, 0x9 },
{REG_TYPE_INDEX_VPP_COEF, 0x19a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x19b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x19c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a0, 0xffffffff, 0x60a00 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a1, 0xffffffff, 0xc },
{REG_TYPE_INDEX_VPP_COEF, 0x1a2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a8, 0xffffffff, 0x60d00 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a9, 0xffffffff, 0xe },
{REG_TYPE_INDEX_VPP_COEF, 0x1aa, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ab, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ac, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b0, 0xffffffff, 0x80d00 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b1, 0xffffffff, 0xc },
{REG_TYPE_INDEX_VPP_COEF, 0x1b2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b8, 0xffffffff, 0xa0d00 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b9, 0xffffffff, 0x7 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ba, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1bb, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1bc, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c0, 0xffffffff, 0xf0f00 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c1, 0xffffffff, 0xfb },
{REG_TYPE_INDEX_VPP_COEF, 0x1c2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c8, 0xffffffff, 0x110f00 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c9, 0xffffffff, 0xf2 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ca, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1cb, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1cc, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1d0, 0xffffffff, 0x131100 },
{REG_TYPE_INDEX_VPP_COEF, 0x1d1, 0xffffffff, 0xee },
{REG_TYPE_INDEX_VPP_COEF, 0x1d2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1d3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1d4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1d8, 0xffffffff, 0x131500 },
{REG_TYPE_INDEX_VPP_COEF, 0x1d9, 0xffffffff, 0xf5 },
{REG_TYPE_INDEX_VPP_COEF, 0x1da, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1db, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1dc, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e0, 0xffffffff, 0x151a00 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e1, 0xffffffff, 0x1 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e8, 0xffffffff, 0x171c00 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e9, 0xffffffff, 0x5 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ea, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1eb, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ec, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f0, 0xffffffff, 0x171a00 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f1, 0xffffffff, 0x5 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f8, 0xffffffff, 0x131500 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f9, 0xffffffff, 0x7 },
{REG_TYPE_INDEX_VPP_COEF, 0x1fa, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1fb, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1fc, 0xffffffff, 0x0 },
{0}
}
};
static struct am_regs_s cmreg_enhancement = {
172,
{
/* enhancement */
{REG_TYPE_INDEX_VPPCHROMA, 0x200, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x201, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x202, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x203, 0xffffffff, 0x8000400},
{REG_TYPE_INDEX_VPPCHROMA, 0x204, 0xffffffff, 0x90 },
{REG_TYPE_INDEX_VPPCHROMA, 0x205, 0xffffffff, 0x437077f},
{REG_TYPE_INDEX_VPPCHROMA, 0x206, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x207, 0xffffffff, 0x2640000},
{REG_TYPE_INDEX_VPPCHROMA, 0x208, 0xffffffff, 0x7a },
{REG_TYPE_INDEX_VPPCHROMA, 0x209, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x20a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPPCHROMA, 0x20f, 0xf, 0x0, },
{REG_TYPE_INDEX_VPP_COEF, 0x100, 0xffffffff, 0x2b5600 },
{REG_TYPE_INDEX_VPP_COEF, 0x101, 0xffffffff, 0xc },
{REG_TYPE_INDEX_VPP_COEF, 0x102, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x103, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x104, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x108, 0xffffffff, 0x295600 },
{REG_TYPE_INDEX_VPP_COEF, 0x109, 0xffffffff, 0x1f },
{REG_TYPE_INDEX_VPP_COEF, 0x10a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x10b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x10c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x110, 0xffffffff, 0x295600 },
{REG_TYPE_INDEX_VPP_COEF, 0x111, 0xffffffff, 0x33 },
{REG_TYPE_INDEX_VPP_COEF, 0x112, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x113, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x114, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x118, 0xffffffff, 0x2b5600 },
{REG_TYPE_INDEX_VPP_COEF, 0x119, 0xffffffff, 0x3f },
{REG_TYPE_INDEX_VPP_COEF, 0x11a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x11b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x11c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x120, 0xffffffff, 0x2b5600 },
{REG_TYPE_INDEX_VPP_COEF, 0x121, 0xffffffff, 0x3f },
{REG_TYPE_INDEX_VPP_COEF, 0x122, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x123, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x124, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x128, 0xffffffff, 0x295600 },
{REG_TYPE_INDEX_VPP_COEF, 0x129, 0xffffffff, 0x3f },
{REG_TYPE_INDEX_VPP_COEF, 0x12a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x12b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x12c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x130, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x131, 0xffffffff, 0x3f },
{REG_TYPE_INDEX_VPP_COEF, 0x132, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x133, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x134, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x138, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x139, 0xffffffff, 0x33 },
{REG_TYPE_INDEX_VPP_COEF, 0x13a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x13b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x13c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x140, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x141, 0xffffffff, 0x9 },
{REG_TYPE_INDEX_VPP_COEF, 0x142, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x143, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x144, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x148, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x149, 0xffffffff, 0xea },
{REG_TYPE_INDEX_VPP_COEF, 0x14a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x14b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x14c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x150, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x151, 0xffffffff, 0xd4 },
{REG_TYPE_INDEX_VPP_COEF, 0x152, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x153, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x154, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x158, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x159, 0xffffffff, 0xc5 },
{REG_TYPE_INDEX_VPP_COEF, 0x15a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x15b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x15c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x160, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x161, 0xffffffff, 0xc1 },
{REG_TYPE_INDEX_VPP_COEF, 0x162, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x163, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x164, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x168, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x169, 0xffffffff, 0xcb },
{REG_TYPE_INDEX_VPP_COEF, 0x16a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x16b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x16c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x170, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x171, 0xffffffff, 0xd6 },
{REG_TYPE_INDEX_VPP_COEF, 0x172, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x173, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x174, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x178, 0xffffffff, 0x295600 },
{REG_TYPE_INDEX_VPP_COEF, 0x179, 0xffffffff, 0xdb },
{REG_TYPE_INDEX_VPP_COEF, 0x17a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x17b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x17c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x180, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x181, 0xffffffff, 0xec },
{REG_TYPE_INDEX_VPP_COEF, 0x182, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x183, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x184, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x188, 0xffffffff, 0x295600 },
{REG_TYPE_INDEX_VPP_COEF, 0x189, 0xffffffff, 0xf9 },
{REG_TYPE_INDEX_VPP_COEF, 0x18a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x18b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x18c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x190, 0xffffffff, 0x295600 },
{REG_TYPE_INDEX_VPP_COEF, 0x191, 0xffffffff, 0x3 },
{REG_TYPE_INDEX_VPP_COEF, 0x192, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x193, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x194, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x198, 0xffffffff, 0x295600 },
{REG_TYPE_INDEX_VPP_COEF, 0x199, 0xffffffff, 0x9 },
{REG_TYPE_INDEX_VPP_COEF, 0x19a, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x19b, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x19c, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a0, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a1, 0xffffffff, 0xc },
{REG_TYPE_INDEX_VPP_COEF, 0x1a2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a8, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x1a9, 0xffffffff, 0xe },
{REG_TYPE_INDEX_VPP_COEF, 0x1aa, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ab, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ac, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b0, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b1, 0xffffffff, 0xc },
{REG_TYPE_INDEX_VPP_COEF, 0x1b2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b8, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x1b9, 0xffffffff, 0x7 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ba, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1bb, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1bc, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c0, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c1, 0xffffffff, 0xfb },
{REG_TYPE_INDEX_VPP_COEF, 0x1c2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c8, 0xffffffff, 0x295400 },
{REG_TYPE_INDEX_VPP_COEF, 0x1c9, 0xffffffff, 0xf2 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ca, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1cb, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1cc, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1d0, 0xffffffff, 0x2295400},
{REG_TYPE_INDEX_VPP_COEF, 0x1d1, 0xffffffff, 0xee },
{REG_TYPE_INDEX_VPP_COEF, 0x1d2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1d3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1d4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1d8, 0xffffffff, 0x4295400},
{REG_TYPE_INDEX_VPP_COEF, 0x1d9, 0xffffffff, 0xf5 },
{REG_TYPE_INDEX_VPP_COEF, 0x1da, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1db, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1dc, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e0, 0xffffffff, 0x8295400},
{REG_TYPE_INDEX_VPP_COEF, 0x1e1, 0xffffffff, 0x1 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1e8, 0xffffffff, 0x8295400},
{REG_TYPE_INDEX_VPP_COEF, 0x1e9, 0xffffffff, 0x5 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ea, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1eb, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1ec, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f0, 0xffffffff, 0x8295400},
{REG_TYPE_INDEX_VPP_COEF, 0x1f1, 0xffffffff, 0x5 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f2, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f3, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f4, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1f8, 0xffffffff, 0x4295400},
{REG_TYPE_INDEX_VPP_COEF, 0x1f9, 0xffffffff, 0x7 },
{REG_TYPE_INDEX_VPP_COEF, 0x1fa, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1fb, 0xffffffff, 0x0 },
{REG_TYPE_INDEX_VPP_COEF, 0x1fc, 0xffffffff, 0x0 },
{0}
}
};
#endif

4415
drivers/amlogic/media/enhancement/amvecm/amcsc.c Normal file
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File diff suppressed because it is too large Load Diff

123
drivers/amlogic/media/enhancement/amvecm/amcsc.h Normal file
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@@ -0,0 +1,123 @@
/*
* drivers/amlogic/media/enhancement/amvecm/amcsc.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef AM_CSC_H
#define AM_CSC_H
/* white balance value */
extern void ve_ogo_param_update(void);
extern struct tcon_rgb_ogo_s video_rgb_ogo;
enum vpp_matrix_sel_e {
VPP_MATRIX_0 = 0, /* OSD convert matrix - new from GXL */
VPP_MATRIX_1, /* vd1 matrix before post-blend */
VPP_MATRIX_2, /* post matrix */
VPP_MATRIX_3, /* xvycc matrix */
VPP_MATRIX_4, /* in video eotf - new from GXL */
VPP_MATRIX_5, /* in osd eotf - new from GXL */
VPP_MATRIX_6 /* vd2 matrix before pre-blend */
};
#define NUM_MATRIX 6
/* matrix names */
#define VPP_MATRIX_OSD VPP_MATRIX_0
#define VPP_MATRIX_VD1 VPP_MATRIX_1
#define VPP_MATRIX_POST VPP_MATRIX_2
#define VPP_MATRIX_XVYCC VPP_MATRIX_3
#define VPP_MATRIX_EOTF VPP_MATRIX_4
#define VPP_MATRIX_OSD_EOTF VPP_MATRIX_5
#define VPP_MATRIX_VD2 VPP_MATRIX_6
/* osd->eotf->matrix5->oetf->matrix0-+->post blend*/
/* ->vadj2->matrix2->eotf->matrix4->oetf->matrix3*/
/* video1->cm->lut->vadj1->matrix1-^*/
/* video2->matrix6-^*/
enum vpp_matrix_csc_e {
VPP_MATRIX_NULL = 0,
VPP_MATRIX_RGB_YUV601 = 0x1,
VPP_MATRIX_RGB_YUV601F = 0x2,
VPP_MATRIX_RGB_YUV709 = 0x3,
VPP_MATRIX_RGB_YUV709F = 0x4,
VPP_MATRIX_YUV601_RGB = 0x10,
VPP_MATRIX_YUV601_YUV601F = 0x11,
VPP_MATRIX_YUV601_YUV709 = 0x12,
VPP_MATRIX_YUV601_YUV709F = 0x13,
VPP_MATRIX_YUV601F_RGB = 0x14,
VPP_MATRIX_YUV601F_YUV601 = 0x15,
VPP_MATRIX_YUV601F_YUV709 = 0x16,
VPP_MATRIX_YUV601F_YUV709F = 0x17,
VPP_MATRIX_YUV709_RGB = 0x20,
VPP_MATRIX_YUV709_YUV601 = 0x21,
VPP_MATRIX_YUV709_YUV601F = 0x22,
VPP_MATRIX_YUV709_YUV709F = 0x23,
VPP_MATRIX_YUV709F_RGB = 0x24,
VPP_MATRIX_YUV709F_YUV601 = 0x25,
VPP_MATRIX_YUV709F_YUV709 = 0x26,
VPP_MATRIX_BT2020YUV_BT2020RGB = 0x40,
VPP_MATRIX_BT2020RGB_709RGB,
VPP_MATRIX_BT2020RGB_CUSRGB,
};
#define CSC_ON 1
#define CSC_OFF 0
enum vpp_lut_sel_e {
VPP_LUT_OSD_EOTF = 0,
VPP_LUT_OSD_OETF,
VPP_LUT_EOTF,
VPP_LUT_OETF,
VPP_LUT_INV_EOTF
};
#define NUM_LUT 5
/* matrix registers */
struct matrix_s {
u16 pre_offset[3];
u16 matrix[3][3];
u16 offset[3];
u16 right_shift;
};
#define LUT_289_SIZE 289
extern unsigned int lut_289_mapping[LUT_289_SIZE];
extern int dnlp_en;
/*extern int cm_en;*/
extern unsigned int vecm_latch_flag;
extern signed int vd1_contrast_offset;
extern signed int saturation_offset;
extern uint sdr_mode;
extern uint hdr_flag;
extern int video_rgb_ogo_xvy_mtx_latch;
extern void amvecm_matrix_process(struct vframe_s *vf);
extern int amvecm_hdr_dbg(u32 sel);
#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val)
#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr)
#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
WRITE_VPP_REG_BITS(adr, val, start, len)
#else
extern int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
extern u32 VSYNC_RD_MPEG_REG(u32 adr);
extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
#endif
#endif /* AM_CSC_H */

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/*
* drivers/amlogic/media/enhancement/amvecm/amve.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __AM_VE_H
#define __AM_VE_H
#include <linux/amlogic/media/vfm/vframe.h>
#include <linux/amlogic/media/amvecm/ve.h>
/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8) */
/* #define WRITE_VPP_REG(x,val) */
/* WRITE_VCBUS_REG(x,val) */
/* #define WRITE_VPP_REG_BITS(x,val,start,length) */
/* WRITE_VCBUS_REG_BITS(x,val,start,length) */
/* #define READ_VPP_REG(x) */
/* READ_VCBUS_REG(x) */
/* #define READ_VPP_REG_BITS(x,start,length) */
/* READ_VCBUS_REG_BITS(x,start,length) */
/* #else */
/* #define WRITE_VPP_REG(x,val) */
/* WRITE_CBUS_REG(x,val) */
/* #define WRITE_VPP_REG_BITS(x,val,start,length) */
/* WRITE_CBUS_REG_BITS(x,val,start,length) */
/* #define READ_VPP_REG(x) */
/* READ_CBUS_REG(x) */
/* #define READ_VPP_REG_BITS(x,start,length) */
/* READ_CBUS_REG_BITS(x,start,length) */
/* #endif */
struct ve_regs_s {
unsigned int val:32;
unsigned int reg:14;
unsigned int port:2;
/* 0 NA NA direct access */
/* 1 VPP_CHROMA_ADDR_PORT */
/* VPP_CHROMA_DATA_PORT CM port registers */
/* 2 NA NA reserved */
/* 3 NA NA reserved */
unsigned int bit:5;
unsigned int wid:5;
unsigned int mode:1;
unsigned int rsv:5;
};
enum vlock_param_e {
VLOCK_EN = 0x0,
VLOCK_ADAPT,
VLOCK_MODE,
VLOCK_DIS_CNT_LIMIT,
VLOCK_DELTA_LIMIT_FRAC,
VLOCK_DELTA_LIMIT_M,
VLOCK_DEBUG,
VLOCK_DYNAMIC_ADJUST,
VLOCK_STATE,
VLOCK_SYNC_LIMIT_FLAG,
VLOCK_DIS_CNT_STEP1_LIMIT,
VLOCK_EN_CNT_STEP1_LIMIT,
VLOCK_PARAM_MAX,
};
extern struct ve_hist_s video_ve_hist;
extern unsigned int ve_size;
extern struct ve_dnlp_s am_ve_dnlp;
extern struct ve_dnlp_table_s am_ve_new_dnlp;
extern struct tcon_gamma_table_s video_gamma_table_r;
extern struct tcon_gamma_table_s video_gamma_table_g;
extern struct tcon_gamma_table_s video_gamma_table_b;
extern struct tcon_gamma_table_s video_gamma_table_r_adj;
extern struct tcon_gamma_table_s video_gamma_table_g_adj;
extern struct tcon_gamma_table_s video_gamma_table_b_adj;
extern struct tcon_rgb_ogo_s video_rgb_ogo;
extern spinlock_t vpp_lcd_gamma_lock;
void ve_on_vs(struct vframe_s *vf);
void ve_set_bext(struct ve_bext_s *p);
void ve_set_dnlp(struct ve_dnlp_s *p);
void ve_set_new_dnlp(struct ve_dnlp_table_s *p);
void ve_set_dnlp_2(void);
void ve_set_hsvs(struct ve_hsvs_s *p);
void ve_set_ccor(struct ve_ccor_s *p);
void ve_set_benh(struct ve_benh_s *p);
void ve_set_demo(struct ve_demo_s *p);
void ve_set_regs(struct ve_regs_s *p);
void ve_set_regmap(struct ve_regmap_s *p);
extern void ve_enable_dnlp(void);
extern void ve_disable_dnlp(void);
extern void vpp_enable_lcd_gamma_table(void);
extern void vpp_disable_lcd_gamma_table(void);
extern void vpp_set_lcd_gamma_table(u16 *data, u32 rgb_mask);
extern void init_write_gamma_table(u16 *data, u32 rgb_mask);
extern void vpp_set_rgb_ogo(struct tcon_rgb_ogo_s *p);
extern void vpp_phase_lock_on_vs(unsigned int cycle,
unsigned int stamp,
bool lock50,
unsigned int range_fast,
unsigned int range_slow);
/* #if (MESON_CPU_TYPE>=MESON_CPU_TYPE_MESON6TVD) */
extern void ve_frame_size_patch(unsigned int width, unsigned int height);
/* #endif */
extern void ve_dnlp_latch_process(void);
extern void ve_lcd_gamma_process(void);
extern void lvds_freq_process(void);
extern void ve_dnlp_param_update(void);
extern void ve_new_dnlp_param_update(void);
extern void ve_ogo_param_update(void);
extern void am_set_regmap(struct am_regs_s *p);
extern void sharpness_process(struct vframe_s *vf);
extern void amvecm_bricon_process(signed int bri_val,
signed int cont_val, struct vframe_s *vf);
extern void amvecm_color_process(signed int sat_val,
signed int hue_val, struct vframe_s *vf);
extern void amvecm_3d_black_process(void);
extern void amvecm_3d_sync_process(void);
extern void amve_vlock_process(struct vframe_s *vf);
extern void amve_vlock_resume(void);
extern void vlock_param_set(unsigned int val, enum vlock_param_e sel);
extern void vlock_status(void);
extern void vlock_reg_dump(void);
int amvecm_hiu_reg_read(unsigned int reg, unsigned int *val);
int amvecm_hiu_reg_write(unsigned int reg, unsigned int val);
extern unsigned int vecm_latch_flag;
extern unsigned int cm_size;
extern unsigned int sync_3d_h_start;
extern unsigned int sync_3d_h_end;
extern unsigned int sync_3d_v_start;
extern unsigned int sync_3d_v_end;
extern unsigned int sync_3d_polarity;
extern unsigned int sync_3d_out_inv;
extern unsigned int sync_3d_black_color;
extern unsigned int sync_3d_sync_to_vbo;
extern void __iomem *amvecm_hiu_reg_base;
#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val)
#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr)
#else
extern u32 VSYNC_RD_MPEG_REG(u32 adr);
extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
#endif
/* #if defined(CONFIG_ARCH_MESON2) */
/* unsigned long long ve_get_vs_cnt(void); */
/* #endif */
#define VLOCK_STATE_NULL 0
#define VLOCK_STATE_ENABLE_STEP1_DONE 1
#define VLOCK_STATE_ENABLE_STEP2_DONE 2
#define VLOCK_STATE_DISABLE_STEP1_DONE 3
#define VLOCK_STATE_DISABLE_STEP2_DONE 4
#define VLOCK_STATE_ENABLE_FORCE_RESET 5
#define VLOCK_STATE_ENABLE_STEP1 6
#define VLOCK_STATE_DISABLE_STEP1 7
#endif

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/*
* drivers/amlogic/media/enhancement/amvecm/amve_gamma_table.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __AM_VE_GAMMATABLE_H
#define __AM_VE_GAMMATABLE_H
/* #include <linux/amlogic/amports/amstream.h> */
struct tcon_gamma_table_s video_curve_2d2_inv = {
{
0, 82, 113, 136, 155, 171, 186, 199, 212, 223,
234, 245, 255, 264, 273, 282, 290, 298, 306, 314,
321, 328, 335, 342, 349, 356, 362, 368, 374, 380,
386, 392, 398, 403, 409, 414, 420, 425, 430, 435,
440, 445, 450, 455, 460, 464, 469, 474, 478, 483,
487, 492, 496, 500, 505, 509, 513, 517, 521, 525,
529, 533, 537, 541, 545, 549, 553, 556, 560, 564,
568, 571, 575, 579, 582, 586, 589, 593, 596, 600,
603, 607, 610, 613, 617, 620, 623, 627, 630, 633,
636, 640, 643, 646, 649, 652, 655, 658, 661, 665,
668, 671, 674, 677, 680, 683, 686, 688, 691, 694,
697, 700, 703, 706, 709, 711, 714, 717, 720, 723,
725, 728, 731, 733, 736, 739, 742, 744, 747, 750,
752, 755, 757, 760, 763, 765, 768, 770, 773, 775,
778, 780, 783, 785, 788, 790, 793, 795, 798, 800,
803, 805, 808, 810, 812, 815, 817, 820, 822, 824,
827, 829, 831, 834, 836, 838, 841, 843, 845, 847,
850, 852, 854, 856, 859, 861, 863, 865, 868, 870,
872, 874, 876, 879, 881, 883, 885, 887, 889, 892,
894, 896, 898, 900, 902, 904, 906, 909, 911, 913,
915, 917, 919, 921, 923, 925, 927, 929, 931, 933,
935, 937, 939, 941, 943, 945, 947, 949, 951, 953,
955, 957, 959, 961, 963, 965, 967, 969, 971, 973,
975, 977, 979, 981, 982, 984, 986, 988, 990, 992,
994, 996, 998, 999, 1001, 1003, 1005, 1007, 1009, 1011,
1012, 1014, 1016, 1018, 1020, 1022,
},
};
struct tcon_gamma_table_s video_curve_2d2 = {
{
0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
1, 1, 1, 1, 2, 2, 2, 3, 3, 3,
4, 4, 5, 5, 6, 6, 7, 7, 8, 9,
9, 10, 11, 11, 12, 13, 14, 15, 15, 16,
17, 18, 19, 20, 21, 22, 23, 25, 26, 27,
28, 29, 31, 32, 33, 35, 36, 38, 39, 41,
42, 44, 45, 47, 49, 50, 52, 54, 55, 57,
59, 61, 63, 65, 67, 69, 71, 73, 75, 77,
79, 82, 84, 86, 88, 91, 93, 95, 98, 100,
103, 105, 108, 110, 113, 116, 118, 121, 124, 127,
130, 132, 135, 138, 141, 144, 147, 150, 154, 157,
160, 163, 166, 170, 173, 176, 180, 183, 187, 190,
194, 197, 201, 204, 208, 212, 216, 219, 223, 227,
231, 235, 239, 243, 247, 251, 255, 259, 263, 267,
272, 276, 280, 285, 289, 294, 298, 303, 307, 312,
316, 321, 326, 330, 335, 340, 345, 350, 355, 360,
365, 370, 375, 380, 385, 390, 395, 401, 406, 411,
417, 422, 427, 433, 438, 444, 450, 455, 461, 467,
472, 478, 484, 490, 496, 502, 508, 514, 520, 526,
532, 538, 544, 551, 557, 563, 570, 576, 583, 589,
596, 602, 609, 615, 622, 629, 636, 642, 649, 656,
663, 670, 677, 684, 691, 698, 705, 713, 720, 727,
735, 742, 749, 757, 764, 772, 779, 787, 795, 802,
810, 818, 826, 833, 841, 849, 857, 865, 873, 881,
889, 898, 906, 914, 922, 931, 939, 948, 956, 965,
973, 982, 990, 999, 1008, 1016,
},
};
#endif

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/*
* drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __AMVECM_VLOCK_REGMAP_H
#define __AMVECM_VLOCK_REGMAP_H
#include <linux/amlogic/media/amvecm/cm.h>
/* #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */
/* TV_ENC_LCD720x480 */
static struct am_regs_s vlock_enc_lcd720x480 = {
20,
{
/* optimize */
{REG_TYPE_VCBUS, 0x3000, 0xffffffff, 0xE0f50f1b },
{REG_TYPE_VCBUS, 0x3001, 0xffffffff, 0x41E3c3c },
{REG_TYPE_VCBUS, 0x3002, 0xffffffff, 0x6000000 },
{REG_TYPE_VCBUS, 0x3003, 0xffffffff, 0x40280280 },
{REG_TYPE_VCBUS, 0x3004, 0xffffffff, 0x280280 },
{REG_TYPE_VCBUS, 0x3005, 0xffffffff, 0x8020000 },
{REG_TYPE_VCBUS, 0x3006, 0xffffffff, 0x0008000 },
{REG_TYPE_VCBUS, 0x3007, 0xffffffff, 0x6000000 },
{REG_TYPE_VCBUS, 0x3008, 0xffffffff, 0x6000000 },
{REG_TYPE_VCBUS, 0x3009, 0xffffffff, 0x0008000 },
{REG_TYPE_VCBUS, 0x300a, 0xffffffff, 0x8000000 },
{REG_TYPE_VCBUS, 0x300b, 0xffffffff, 0x0008000 },
{REG_TYPE_VCBUS, 0x300c, 0xffffffff, 0xa000000 },
{REG_TYPE_VCBUS, 0x300d, 0xffffffff, 0x0004000 },
{REG_TYPE_VCBUS, 0x3010, 0xffffffff, 0x20001000 },
{REG_TYPE_VCBUS, 0x3016, 0xffffffff, 0x18000 },
{REG_TYPE_VCBUS, 0x3017, 0xffffffff, 0x01080 },
{REG_TYPE_VCBUS, 0x301d, 0xffffffff, 0x30501080 },
{REG_TYPE_VCBUS, 0x301e, 0xffffffff, 0x7 },
{REG_TYPE_VCBUS, 0x301f, 0xffffffff, 0x6000000 },
{0}
}
};
/* out:TV_ENC_LCD1920x1080P60;in:50hz pal av */
static struct am_regs_s vlock_pll_in50hz_out60hz = {
20,
{
/* optimize */
{REG_TYPE_VCBUS, 0x3000, 0xffffffff, 0x07f13f1b },
{REG_TYPE_VCBUS, 0x3001, 0xffffffff, 0x04053c32 },
{REG_TYPE_VCBUS, 0x3002, 0xffffffff, 0x06000000 },
{REG_TYPE_VCBUS, 0x3003, 0xffffffff, 0x2055c55c },
{REG_TYPE_VCBUS, 0x3004, 0xffffffff, 0x0065c65c },
{REG_TYPE_VCBUS, 0x3005, 0xffffffff, 0x00080000 },
{REG_TYPE_VCBUS, 0x3006, 0xffffffff, 0x00070000 },
{REG_TYPE_VCBUS, 0x3007, 0xffffffff, 0x00000000 },
{REG_TYPE_VCBUS, 0x3008, 0xffffffff, 0x00000000 },
{REG_TYPE_VCBUS, 0x3009, 0xffffffff, 0x00100000 },
{REG_TYPE_VCBUS, 0x300a, 0xffffffff, 0x00100000 },
{REG_TYPE_VCBUS, 0x300b, 0xffffffff, 0x00100000 },
{REG_TYPE_VCBUS, 0x300c, 0xffffffff, 0x00010000 },
{REG_TYPE_VCBUS, 0x300d, 0xffffffff, 0x00004000 },
{REG_TYPE_VCBUS, 0x3010, 0xffffffff, 0x20001000 },
{REG_TYPE_VCBUS, 0x3016, 0xffffffff, 0x0003de00 },
{REG_TYPE_VCBUS, 0x3017, 0xffffffff, 0x00001080 },
{REG_TYPE_VCBUS, 0x301d, 0xffffffff, 0x30501080 },
{REG_TYPE_VCBUS, 0x301e, 0xffffffff, 0x00000007 },
{REG_TYPE_VCBUS, 0x301f, 0xffffffff, 0x06000000 },
{0}
}
};
/* #endif */
#endif

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/*
* drivers/amlogic/media/enhancement/amvecm/arch/cm_regs.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __CM_REG_H
#define __CM_REG_H
/* ********************************************************** */
/* ******** COLOR MANAGEMENT INDIRECT REGISTERS ******** */
/* ******************************************************* */
/* #define CHROMA_GAIN_REG00 0x00 */
/* #define CHROMA_GAIN_REG01 0x06 */
/* #define CHROMA_GAIN_REG02 0x0C */
/* #define CHROMA_GAIN_REG03 0x12 */
/* #define CHROMA_GAIN_REG04 0x18 */
/* #define CHROMA_GAIN_REG05 0x1E */
/* #define CHROMA_GAIN_REG06 0x24 */
/* #define CHROMA_GAIN_REG07 0x2A */
#define SAT_EN_BIT 31
#define SAT_EN_WID 1
#define SAT_INC_BIT 27
#define SAT_INC_WID 1
#define SAT_CENTRAL_EN_BIT 25
#define SAT_CENTRAL_EN_WID 2
#define SAT_SHAPE_BIT 24
#define SAT_SHAPE_WID 1
#define SAT_GAIN_BIT 16
#define SAT_GAIN_WID 8
#define HUE_EN_BIT 15
#define HUE_EN_WID 1
#define HUE_CLOCKWISE_BIT 11
#define HUE_CLOCKWISE_WID 1
#define HUE_CENTRAL_EN_BIT 9
#define HUE_CENTRAL_EN_WID 2
#define HUE_SHAPE_BIT 8
#define HUE_SHAPE_WID 1
#define HUE_GAIN_BIT 0
#define HUE_GAIN_WID 8
/* #define HUE_HUE_RANGE_REG00 0x01 */
/* #define HUE_HUE_RANGE_REG01 0x07 */
/* #define HUE_HUE_RANGE_REG02 0x0D */
/* #define HUE_HUE_RANGE_REG03 0x13 */
/* #define HUE_HUE_RANGE_REG04 0x19 */
/* #define HUE_HUE_RANGE_REG05 0x1F */
/* #define HUE_HUE_RANGE_REG06 0x25 */
/* #define HUE_HUE_RANGE_REG07 0x2B */
#define HUE_SHF_RAN_BIT 16
#define HUE_SHF_RAN_WID 8
#define SYM_EN_BIT 15
#define SYM_EN_WID 1
#define HUE_SHF_STA_BIT 0
#define HUE_SHF_STA_WID 15
/* #define HUE_RANGE_INV_REG00 0x02 */
/* #define HUE_RANGE_INV_REG01 0x08 */
/* #define HUE_RANGE_INV_REG02 0x0E */
/* #define HUE_RANGE_INV_REG03 0x14 */
/* #define HUE_RANGE_INV_REG04 0x1A */
/* #define HUE_RANGE_INV_REG05 0x20 */
/* #define HUE_RANGE_INV_REG06 0x26 */
/* #define HUE_RANGE_INV_REG07 0x2C */
#define HUE_SHF_RAN_INV_BIT 0
#define HUE_SHF_RAN_INV_WID 16
/* #define HUE_LUM_RANGE_REG00 0x03 */
/* #define HUE_LUM_RANGE_REG01 0x09 */
/* #define HUE_LUM_RANGE_REG02 0x0F */
/* #define HUE_LUM_RANGE_REG03 0x15 */
/* #define HUE_LUM_RANGE_REG04 0x1B */
/* #define HUE_LUM_RANGE_REG05 0x21 */
/* #define HUE_LUM_RANGE_REG06 0x27 */
/* #define HUE_LUM_RANGE_REG07 0x2D */
/* for belowing each low, high, low_slope, high_slope group: */
/* a_____________b */
/* / \ */
/* / \ */
/* / \ */
/* / \ */
/* ______/_____________________\________ */
/* low high */
/* a = low + 2^low_slope */
/* low_slope <= 7; high_slope <= 7 */
/* b >= a */
#define SAT_LUM_L_BIT 24
#define SAT_LUM_L_WID 8
#define HUE_LUM_H_SLOPE_BIT 20
#define HUE_LUM_H_SLOPE_WID 4
#define HUE_LUM_L_SLOPE_BIT 16
#define HUE_LUM_L_SLOPE_WID 4
#define HUE_LUM_H_BIT 8
#define HUE_LUM_H_WID 8
#define HUE_LUM_L_BIT 0
#define HUE_LUM_L_WID 8
/* #define HUE_SAT_RANGE_REG00 0x04 */
/* #define HUE_SAT_RANGE_REG01 0x0A */
/* #define HUE_SAT_RANGE_REG02 0x10 */
/* #define HUE_SAT_RANGE_REG03 0x16 */
/* #define HUE_SAT_RANGE_REG04 0x1C */
/* #define HUE_SAT_RANGE_REG05 0x22 */
/* #define HUE_SAT_RANGE_REG06 0x28 */
/* #define HUE_SAT_RANGE_REG07 0x2E */
#define SAT_LUM_H_BIT 24
#define SAT_LUM_H_WID 8
#define HUE_SAT_H_SLOPE_BIT 20
#define HUE_SAT_H_SLOPE_WID 4
#define HUE_SAT_L_SLOPE_BIT 16
#define HUE_SAT_L_SLOPE_WID 4
#define HUE_SAT_H_BIT 8
#define HUE_SAT_H_WID 8
#define HUE_SAT_L_BIT 0
#define HUE_SAT_L_WID 8
/* #define SAT_SAT_RANGE_REG00 0x05 */
/* #define SAT_SAT_RANGE_REG01 0x0B */
/* #define SAT_SAT_RANGE_REG02 0x11 */
/* #define SAT_SAT_RANGE_REG03 0x17 */
/* #define SAT_SAT_RANGE_REG04 0x1D */
/* #define SAT_SAT_RANGE_REG05 0x23 */
/* #define SAT_SAT_RANGE_REG06 0x29 */
/* #define SAT_SAT_RANGE_REG07 0x2F */
#define SAT_LUM_H_SLOPE_BIT 28
#define SAT_LUM_H_SLOPE_WID 4
#define SAT_LUM_L_SLOPE_BIT 24
#define SAT_LUM_L_SLOPE_WID 4
#define SAT_SAT_H_SLOPE_BIT 20
#define SAT_SAT_H_SLOPE_WID 4
#define SAT_SAT_L_SLOPE_BIT 16
#define SAT_SAT_L_SLOPE_WID 4
#define SAT_SAT_H_BIT 8
#define SAT_SAT_H_WID 8
#define SAT_SAT_L_BIT 0
#define SAT_SAT_L_WID 8
/* #define REG_CHROMA_CONTROL 0x30 */
#define CHROMA_EN_BIT 31
#define CHROMA_EN_WID 1
#if defined(CONFIG_ARCH_MESON)
/* 1'b0: demo adjust on right, 1'b1: demo adjust on left */
#elif defined(CONFIG_ARCH_MESON2)
/* 2'b00: demo adjust on top, 2'b01: demo adjust on bottom */
/* 2'b10: demo adjust on left,2'b11: demo adjust on right */
#endif
#define CM_DEMO_POS_BIT 22
#define CM_DEMO_POS_WID 2
#define DEMO_HLIGHT_ADJ_BIT 21
#define DEMO_HLIGHT_ADJ_WID 1
#define DEMO_EN_BIT 20
#define DEMO_EN_WID 1
#define CM_DEMO_WID_BIT 8
#define CM_DEMO_WID_WID 12
#define SAT_SEL_BIT 6
#define SAT_SEL_WID 1
#define UV_ADJ_EN_BIT 5
#define UV_ADJ_EN_WID 1
#define RGB_TO_HUE_EN_BIT 2
#define RGB_TO_HUE_EN_WID 1
/* 2'b00: 601(16-235) 2'b01: 709(16-235) */
/* 2'b10: 601(0-255) 2'b11: 709(0-255) */
#define CSC_SEL_BIT 0
#define CSC_SEL_WID 2
/* #if defined(CONFIG_ARCH_MESON2) */
/* #define REG_DEMO_CENTER_BAR 0x31 // default 32h'0 */
#define CM_CBAR_EN_BIT 31 /* center bar enable */
#define CM_CBAR_EN_WID 1
#define CM_CBAR_WID_BIT 24 /* center bar width (*2) */
#define CM_CBAR_WID_WID 4
#define CM_CBAR_CR_BIT 16 /* center bar Cr (*4) */
#define CM_CBAR_CR_WID 8
#define CM_CBAR_CB_BIT 8 /* center bar Cb (*4) */
#define CM_CBAR_CB_WID 8
#define CM_CBAR_Y_BIT 0 /* center bar y (*4) */
#define CM_CBAR_Y_WID 8
/* #endif */
#endif /* _CM_REG_H */

1130
drivers/amlogic/media/enhancement/amvecm/arch/hdr_curve.h Normal file
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529
drivers/amlogic/media/enhancement/amvecm/arch/ve_regs.h Normal file
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@@ -0,0 +1,529 @@
/*
* drivers/amlogic/media/enhancement/amvecm/arch/ve_regs.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _VE_REG_H
#define _VE_REG_H
/* ********************************************************************* */
/* ******** GAMMA REGISTERS ******** */
/* ********************************************************************* */
#define L_GAMMA_CNTL_PORT 0x1400
#define GAMMA_VCOM_POL 7 /* RW */
#define GAMMA_RVS_OUT 6 /* RW */
#define ADR_RDY 5 /* Read Only */
#define WR_RDY 4 /* Read Only */
#define RD_RDY 3 /* Read Only */
#define GAMMA_TR 2 /* RW */
#define GAMMA_SET 1 /* RW */
#define GAMMA_EN 0 /* RW */
#define L_GAMMA_DATA_PORT 0x1401
#define L_GAMMA_ADDR_PORT 0x1402
#define H_RD 12
#define H_AUTO_INC 11
#define H_SEL_R 10
#define H_SEL_G 9
#define H_SEL_B 8
#define HADR_MSB 7 /* 7:0 */
#define HADR 0 /* 7:0 */
/* ********************************************************************* */
/* ******** VIDEO ENHANCEMENT REGISTERS ******** */
/* ********************************************************************* */
/* #define VPP_BLACKEXT_CTRL 0x1d80 */
#define BEXT_START_BIT 24
#define BEXT_START_WID 8
#define BEXT_SLOPE1_BIT 16
#define BEXT_SLOPE1_WID 8
#define BEXT_MIDPT_BIT 8
#define BEXT_MIDPT_WID 8
#define BEXT_SLOPE2_BIT 0
#define BEXT_SLOPE2_WID 8
/* #define VPP_DNLP_CTRL_00 0x1d81 */
#define DNLP_GAMMA03_BIT 24
#define DNLP_GAMMA03_WID 8
#define DNLP_GAMMA02_BIT 16
#define DNLP_GAMMA02_WID 8
#define DNLP_GAMMA01_BIT 8
#define DNLP_GAMMA01_WID 8
#define DNLP_GAMMA00_BIT 0
#define DNLP_GAMMA00_WID 8
/* #define VPP_DNLP_CTRL_01 0x1d82 */
#define DNLP_GAMMA07_BIT 24
#define DNLP_GAMMA07_WID 8
#define DNLP_GAMMA06_BIT 16
#define DNLP_GAMMA06_WID 8
#define DNLP_GAMMA05_BIT 8
#define DNLP_GAMMA05_WID 8
#define DNLP_GAMMA04_BIT 0
#define DNLP_GAMMA04_WID 8
/* #define VPP_DNLP_CTRL_02 0x1d83 */
#define DNLP_GAMMA11_BIT 24
#define DNLP_GAMMA11_WID 8
#define DNLP_GAMMA10_BIT 16
#define DNLP_GAMMA10_WID 8
#define DNLP_GAMMA09_BIT 8
#define DNLP_GAMMA09_WID 8
#define DNLP_GAMMA08_BIT 0
#define DNLP_GAMMA08_WID 8
/* #define VPP_DNLP_CTRL_03 0x1d84 */
#define DNLP_GAMMA15_BIT 24
#define DNLP_GAMMA15_WID 8
#define DNLP_GAMMA14_BIT 16
#define DNLP_GAMMA14_WID 8
#define DNLP_GAMMA13_BIT 8
#define DNLP_GAMMA13_WID 8
#define DNLP_GAMMA12_BIT 0
#define DNLP_GAMMA12_WID 8
/* #define VPP_DNLP_CTRL_04 0x1d85 */
#define DNLP_GAMMA19_BIT 24
#define DNLP_GAMMA19_WID 8
#define DNLP_GAMMA18_BIT 16
#define DNLP_GAMMA18_WID 8
#define DNLP_GAMMA17_BIT 8
#define DNLP_GAMMA17_WID 8
#define DNLP_GAMMA16_BIT 0
#define DNLP_GAMMA16_WID 8
/* #define VPP_DNLP_CTRL_05 0x1d86 */
#define DNLP_GAMMA23_BIT 24
#define DNLP_GAMMA23_WID 8
#define DNLP_GAMMA22_BIT 16
#define DNLP_GAMMA22_WID 8
#define DNLP_GAMMA21_BIT 8
#define DNLP_GAMMA21_WID 8
#define DNLP_GAMMA20_BIT 0
#define DNLP_GAMMA20_WID 8
/* #define VPP_DNLP_CTRL_06 0x1d87 */
#define DNLP_GAMMA27_BIT 24
#define DNLP_GAMMA27_WID 8
#define DNLP_GAMMA26_BIT 16
#define DNLP_GAMMA26_WID 8
#define DNLP_GAMMA25_BIT 8
#define DNLP_GAMMA25_WID 8
#define DNLP_GAMMA24_BIT 0
#define DNLP_GAMMA24_WID 8
/* #define VPP_DNLP_CTRL_07 0x1d88 */
#define DNLP_GAMMA31_BIT 24
#define DNLP_GAMMA31_WID 8
#define DNLP_GAMMA30_BIT 16
#define DNLP_GAMMA30_WID 8
#define DNLP_GAMMA29_BIT 8
#define DNLP_GAMMA29_WID 8
#define DNLP_GAMMA28_BIT 0
#define DNLP_GAMMA28_WID 8
/* #define VPP_DNLP_CTRL_08 0x1d89 */
#define DNLP_GAMMA35_BIT 24
#define DNLP_GAMMA35_WID 8
#define DNLP_GAMMA34_BIT 16
#define DNLP_GAMMA34_WID 8
#define DNLP_GAMMA33_BIT 8
#define DNLP_GAMMA33_WID 8
#define DNLP_GAMMA32_BIT 0
#define DNLP_GAMMA32_WID 8
/* #define VPP_DNLP_CTRL_09 0x1d8a */
#define DNLP_GAMMA39_BIT 24
#define DNLP_GAMMA39_WID 8
#define DNLP_GAMMA38_BIT 16
#define DNLP_GAMMA38_WID 8
#define DNLP_GAMMA37_BIT 8
#define DNLP_GAMMA37_WID 8
#define DNLP_GAMMA36_BIT 0
#define DNLP_GAMMA36_WID 8
/* #define VPP_DNLP_CTRL_10 0x1d8b */
#define DNLP_GAMMA43_BIT 24
#define DNLP_GAMMA43_WID 8
#define DNLP_GAMMA42_BIT 16
#define DNLP_GAMMA42_WID 8
#define DNLP_GAMMA41_BIT 8
#define DNLP_GAMMA41_WID 8
#define DNLP_GAMMA40_BIT 0
#define DNLP_GAMMA40_WID 8
/* #define VPP_DNLP_CTRL_11 0x1d8c */
#define DNLP_GAMMA47_BIT 24
#define DNLP_GAMMA47_WID 8
#define DNLP_GAMMA46_BIT 16
#define DNLP_GAMMA46_WID 8
#define DNLP_GAMMA45_BIT 8
#define DNLP_GAMMA45_WID 8
#define DNLP_GAMMA44_BIT 0
#define DNLP_GAMMA44_WID 8
/* #define VPP_DNLP_CTRL_12 0x1d8d */
#define DNLP_GAMMA51_BIT 24
#define DNLP_GAMMA51_WID 8
#define DNLP_GAMMA50_BIT 16
#define DNLP_GAMMA50_WID 8
#define DNLP_GAMMA49_BIT 8
#define DNLP_GAMMA49_WID 8
#define DNLP_GAMMA48_BIT 0
#define DNLP_GAMMA48_WID 8
/* #define VPP_DNLP_CTRL_13 0x1d8e */
#define DNLP_GAMMA55_BIT 24
#define DNLP_GAMMA55_WID 8
#define DNLP_GAMMA54_BIT 16
#define DNLP_GAMMA54_WID 8
#define DNLP_GAMMA53_BIT 8
#define DNLP_GAMMA53_WID 8
#define DNLP_GAMMA52_BIT 0
#define DNLP_GAMMA52_WID 8
/* #define VPP_DNLP_CTRL_14 0x1d8f */
#define DNLP_GAMMA59_BIT 24
#define DNLP_GAMMA59_WID 8
#define DNLP_GAMMA58_BIT 16
#define DNLP_GAMMA58_WID 8
#define DNLP_GAMMA57_BIT 8
#define DNLP_GAMMA57_WID 8
#define DNLP_GAMMA56_BIT 0
#define DNLP_GAMMA56_WID 8
/* #define VPP_DNLP_CTRL_15 0x1d90 */
#define DNLP_GAMMA63_BIT 24
#define DNLP_GAMMA63_WID 8
#define DNLP_GAMMA62_BIT 16
#define DNLP_GAMMA62_WID 8
#define DNLP_GAMMA61_BIT 8
#define DNLP_GAMMA61_WID 8
#define DNLP_GAMMA60_BIT 0
#define DNLP_GAMMA60_WID 8
/* #define VPP_PEAKING_HGAIN 0x1d91 */
#define VLTI_STEP_BIT 28
#define VLTI_STEP_WID 1
#define VLTI_STEP2_BIT 27
#define VLTI_STEP2_WID 1
#define HLTI_STEP_BIT 25
#define HLTI_STEP_WID 2
#define PEAK_GAIN_H1_BIT 20
#define PEAK_GAIN_H1_WID 5
#define PEAK_GAIN_H2_BIT 15
#define PEAK_GAIN_H2_WID 5
#define PEAK_GAIN_H3_BIT 10
#define PEAK_GAIN_H3_WID 5
#define PEAK_GAIN_H4_BIT 5
#define PEAK_GAIN_H4_WID 5
#define PEAK_GAIN_H5_BIT 0
#define PEAK_GAIN_H5_WID 5
/* #define VPP_PEAKING_VGAIN 0x1d92 */
#define VCTI_BUF_EN_BIT 31
#define VCTI_BUF_EN_WID 1
#define VCTI_BUF_MODE_C5L_BIT 30
#define VCTI_BUF_MODE_C5L_WID 1
#define PEAK_GAIN_V1_BIT 25
#define PEAK_GAIN_V1_WID 5
#define PEAK_GAIN_V2_BIT 20
#define PEAK_GAIN_V2_WID 5
#define PEAK_GAIN_V3_BIT 15
#define PEAK_GAIN_V3_WID 5
#define PEAK_GAIN_V4_BIT 10
#define PEAK_GAIN_V4_WID 5
#define PEAK_GAIN_V5_BIT 5
#define PEAK_GAIN_V5_WID 5
#define PEAK_GAIN_V6_BIT 0
#define PEAK_GAIN_V6_WID 5
/* #define VPP_PEAKING_NLP_1 0x1d93 */
#define HPEAK_SLOPE1_BIT 26
#define HPEAK_SLOPE1_WID 6
#define HPEAK_SLOPE2_BIT 20
#define HPEAK_SLOPE2_WID 6
#define HPEAK_THR1_BIT 12
#define HPEAK_THR1_WID 8
#define VPEAK_SLOPE1_BIT 6
#define VPEAK_SLOPE1_WID 6
#define VPEAK_SLOPE2_BIT 0
#define VPEAK_SLOPE2_WID 6
/* #define VPP_PEAKING_NLP_2 0x1d94 */
#define HPEAK_THR2_BIT 24
#define HPEAK_THR2_WID 8
#define HPEAK_NLP_COR_THR_BIT 16
#define HPEAK_NLP_COR_THR_WID 8
#define HPEAK_NLP_GAIN_POS_BIT 8
#define HPEAK_NLP_GAIN_POS_WID 8
#define HPEAK_NLP_GAIN_NEG_BIT 0
#define HPEAK_NLP_GAIN_NEG_WID 8
/* #define VPP_PEAKING_NLP_3 0x1d95 */
#define VPEAK_THR1_BIT 24
#define VPEAK_THR1_WID 8
#define SPEAK_SLOPE1_BIT 18
#define SPEAK_SLOPE1_WID 6
#define SPEAK_SLOPE2_BIT 12
#define SPEAK_SLOPE2_WID 6
#define SPEAK_THR1_BIT 4
#define SPEAK_THR1_WID 8
#define PEAK_COR_GAIN_BIT 0
#define PEAK_COR_GAIN_WID 4
/* #define VPP_PEAKING_NLP_4 0x1d96 */
#define VPEAK_THR2_BIT 24
#define VPEAK_THR2_WID 8
#define VPEAK_NLP_COR_THR_BIT 16
#define VPEAK_NLP_COR_THR_WID 8
#define VPEAK_NLP_GAIN_POS_BIT 8
#define VPEAK_NLP_GAIN_POS_WID 8
#define VPEAK_NLP_GAIN_NEG_BIT 0
#define VPEAK_NLP_GAIN_NEG_WID 8
/* #define VPP_PEAKING_NLP_5 0x1d97 */
#define SPEAK_THR2_BIT 24
#define SPEAK_THR2_WID 8
#define SPEAK_NLP_COR_THR_BIT 16
#define SPEAK_NLP_COR_THR_WID 8
#define SPEAK_NLP_GAIN_POS_BIT 8
#define SPEAK_NLP_GAIN_POS_WID 8
#define SPEAK_NLP_GAIN_NEG_BIT 0
#define SPEAK_NLP_GAIN_NEG_WID 8
/* #define VPP_HSVS_LIMIT 0x1d98 */
#define PEAK_COR_THR_L_BIT 24
#define PEAK_COR_THR_L_WID 8
#define PEAK_COR_THR_H_BIT 16
#define PEAK_COR_THR_H_WID 8
#define VLIMIT_COEF_H_BIT 12
#define VLIMIT_COEF_H_WID 4
#define VLIMIT_COEF_L_BIT 8
#define VLIMIT_COEF_L_WID 4
#define HLIMIT_COEF_H_BIT 4
#define HLIMIT_COEF_H_WID 4
#define HLIMIT_COEF_L_BIT 0
#define HLIMIT_COEF_L_WID 4
/* #define VPP_VLTI_CTRL 0x1d99 */
#define VLTI_GAIN_NEG_BIT 24
#define VLTI_GAIN_NEG_WID 8
#define VLTI_GAIN_POS_BIT 16
#define VLTI_GAIN_POS_WID 8
#define VLTI_THR_BIT 8
#define VLTI_THR_WID 8
#define VLTI_BLEND_FACTOR_BIT 0
#define VLTI_BLEND_FACTOR_WID 8
/* #define VPP_HLTI_CTRL 0x1d9a */
#define HLTI_GAIN_NEG_BIT 24
#define HLTI_GAIN_NEG_WID 8
#define HLTI_GAIN_POS_BIT 16
#define HLTI_GAIN_POS_WID 8
#define HLTI_THR_BIT 8
#define HLTI_THR_WID 8
#define HLTI_BLEND_FACTOR_BIT 0
#define HLTI_BLEND_FACTOR_WID 8
/* #define VPP_CTI_CTRL 0x1d9b */
#define CTI_C444TO422_EN_BIT 30
#define CTI_C444TO422_EN_WID 1
/* 2'b00: no filter, 2'b01: (1, 0, 1), */
/* 2'b10: (1, 2, 1), 2'b11: (1, 2, 2, 2, 1), */
#define VCTI_FILTER_BIT 28
#define VCTI_FILTER_WID 2
#define CTI_C422TO444_EN_BIT 27
#define CTI_C422TO444_EN_WID 1
#define HCTI_STEP2_BIT 24
#define HCTI_STEP2_WID 3
#define HCTI_STEP_BIT 21
#define HCTI_STEP_WID 3
#define CTI_BLEND_FACTOR_BIT 16
#define CTI_BLEND_FACTOR_WID 5
#define HCTI_MODE_MEDIAN_BIT 15
#define HCTI_MODE_MEDIAN_WID 1
#define HCTI_THR_BIT 8
#define HCTI_THR_WID 7
#define HCTI_GAIN_BIT 0
#define HCTI_GAIN_WID 8
/* #define VPP_BLUE_STRETCH_1 0x1d9c */
#define BENH_CB_INC_BIT 29
#define BENH_CB_INC_WID 1
#define BENH_CR_INC_BIT 28
#define BENH_CR_INC_WID 1
#define BENH_ERR_CRP_INV_H_BIT 27
#define BENH_ERR_CRP_INV_H_WID 1
#define BENH_ERR_CRN_INV_H_BIT 26
#define BENH_ERR_CRN_INV_H_WID 1
#define BENH_ERR_CBP_INV_H_BIT 25
#define BENH_ERR_CBP_INV_H_WID 1
#define BENH_ERR_CBN_INV_H_BIT 24
#define BENH_ERR_CBN_INV_H_WID 1
#define BENH_GAIN_CR_BIT 16
#define BENH_GAIN_CR_WID 8
#define BENH_GAIN_CB4CR_BIT 8
#define BENH_GAIN_CB4CR_WID 8
#define BENH_LUMA_H_BIT 0
#define BENH_LUMA_H_WID 8
/* #define VPP_BLUE_STRETCH_2 0x1d9d */
#define BENH_ERR_CRP_BIT 27
#define BENH_ERR_CRP_WID 5
#define BENH_ERR_CRP_INV_L_BIT 16
#define BENH_ERR_CRP_INV_L_WID 11
#define BENH_ERR_CRN_BIT 11
#define BENH_ERR_CRN_WID 5
#define BENH_ERR_CRN_INV_L_BIT 0
#define BENH_ERR_CRN_INV_L_WID 11
/* #define VPP_BLUE_STRETCH_3 0x1d9e */
#define BENH_ERR_CBP_BIT 27
#define BENH_ERR_CBP_WID 5
#define BENH_ERR_CBP_INV_L_BIT 16
#define BENH_ERR_CBP_INV_L_WID 11
#define BENH_ERR_CBN_BIT 11
#define BENH_ERR_CBN_WID 5
#define BENH_ERR_CBN_INV_L_BIT 0
#define BENH_ERR_CBN_INV_L_WID 11
/* #define VPP_CCORING_CTRL 0x1da0 */
#define CCOR_THR_BIT 8
#define CCOR_THR_WID 8
#define CCOR_SLOPE_BIT 0
#define CCOR_SLOPE_WID 4
/* #define VPP_VE_ENABLE_CTRL 0x1da1 */
#define DEMO_CCOR_BIT 20
#define DEMO_CCOR_WID 1
#define DEMO_BEXT_BIT 19
#define DEMO_BEXT_WID 1
#define DEMO_DNLP_BIT 18
#define DEMO_DNLP_WID 1
#define DEMO_HSVS_BIT 17
#define DEMO_HSVS_WID 1
#define DEMO_BENH_BIT 16
#define DEMO_BENH_WID 1
#if defined(CONFIG_ARCH_MESON)
/* 1'b0: demo adjust on right, 1'b1: demo adjust on left */
#define VE_DEMO_POS_BIT 15
#define VE_DEMO_POS_WID 1
#elif defined(CONFIG_ARCH_MESON2)
/* 2'b00: demo adjust on top, 2'b01: demo adjust on bottom, */
/* 2'b10: demo adjust on left, 2'b11: demo adjust on right */
#define VE_DEMO_POS_BIT 14
#define VE_DEMO_POS_WID 2
#endif
#define CCOR_EN_BIT 4
#define CCOR_EN_WID 1
#define BEXT_EN_BIT 3
#define BEXT_EN_WID 1
#define DNLP_EN_BIT 2
#define DNLP_EN_WID 1
#define HSVS_EN_BIT 1
#define HSVS_EN_WID 1
#define BENH_EN_BIT 0
#define BENH_EN_WID 1
#if defined(CONFIG_ARCH_MESON)
/* #define VPP_VE_DEMO_LEFT_SCREEN_WIDTH 0x1da2 */
#elif defined(CONFIG_ARCH_MESON2)
/* #define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2 */
#endif
#define VE_DEMO_WID_BIT 0
#define VE_DEMO_WID_WID 12
#if defined(CONFIG_ARCH_MESON2)
/* #define VPP_VE_DEMO_CENTER_BAR 0x1da3 */
#define VE_CBAR_EN_BIT 31 /* center bar enable */
#define VE_CBAR_EN_WID 1
#define VE_CBAR_WID_BIT 24 /* center bar width (*2) */
#define VE_CBAR_WID_WID 4
#define VE_CBAR_CR_BIT 16 /* center bar Cr (*4) */
#define VE_CBAR_CR_WID 8
#define VE_CBAR_CB_BIT 8 /* center bar Cb (*4) */
#define VE_CBAR_CB_WID 8
#define VE_CBAR_Y_BIT 0 /* center bar y (*4) */
#define VE_CBAR_Y_WID 8
#endif
#if defined(CONFIG_ARCH_MESON2)
/* #define VPP_VDO_MEAS_CTRL 0x1da8 */
/* reset bit, high active */
#define VDO_MEAS_RST_BIT 10
#define VDO_MEAS_RST_WID 1
/* 0: rising edge, 1: falling edge */
#define VDO_MEAS_EDGE_BIT 9
#define VDO_MEAS_EDGE_WID 1
/* 1: accumulate the counter number, 0: not */
#define VDO_MEAS_ACCUM_CNT_BIT 8
#define VDO_MEAS_ACCUM_CNT_WID 1
/* how many vsync span need to measure */
#define VDO_MEAS_VS_SPAN_BIT 0
#define VDO_MEAS_VS_SPAN_WID 8
#endif
/* #if defined(CONFIG_ARCH_MESON2) */
/* #define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 //Read only */
/* every number of sync_span vsyncs, this counter add 1 */
#define VDO_IND_MEAS_CNT_N_BIT 16
#define VDO_IND_MEAS_CNT_N_WID 4
/* high bit portion of counter */
#define VDO_MEAS_VS_CNT_HI_BIT 0
#define VDO_MEAS_VS_CNT_HI_WID 16
/* #endif */
/* #if defined(CONFIG_ARCH_MESON2) */
/* #define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa //Read only */
/* low bit portion of counter */
#define VDO_MEAS_VS_CNT_LO_BIT 0
#define VDO_MEAS_VS_CNT_LO_WID 32
/* #endif */
/* bit 15:8 peaking_factor */
/* bit 5 peaking_dnlp_demo_en */
/* bit 4 peaking_dnlp_en */
/* bit 3:0 peaking_filter_sel */
/* #define VPP_PEAKING_DNLP 0x1db8 */
#define PEAKING_FACTOR_BIT 8
#define PEAKING_FACTOR_WID 8
#define PEAKING_DNLP_DEMO_EN_BIT 5
#define PEAKING_DNLP_DEMO_EN_WID 1
#define PEAKING_DNLP_EN_BIT 4
#define PEAKING_DNLP_EN_WID 1
#define PEAKING_FILTER_SEL_BIT 0
#define PEAKING_FILTER_SEL_WID 4
#define VPP_VE_H_V_SIZE 0x1da4
#define SRSHARP0_DNLP_EN 0x3245
#define SRSHARP0_DNLP_00 0x3246
#define SRSHARP0_DNLP_01 0x3247
#define SRSHARP0_DNLP_02 0x3248
#define SRSHARP0_DNLP_03 0x3249
#define SRSHARP0_DNLP_04 0x324a
#define SRSHARP0_DNLP_05 0x324b
#define SRSHARP0_DNLP_06 0x324c
#define SRSHARP0_DNLP_07 0x324d
#define SRSHARP0_DNLP_08 0x324e
#define SRSHARP0_DNLP_09 0x324f
#define SRSHARP0_DNLP_10 0x3250
#define SRSHARP0_DNLP_11 0x3251
#define SRSHARP0_DNLP_12 0x3252
#define SRSHARP0_DNLP_13 0x3253
#define SRSHARP0_DNLP_14 0x3254
#define SRSHARP0_DNLP_15 0x3255
#define SRSHARP0_DEMO_CRTL 0x3256
#endif /* _VE_REG_H */

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drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h Normal file
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/*
* drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef VPP_DOLBYVISION_REGS_H
#define VPP_DOLBYVISION_REGS_H
#define DOLBY_CORE1_REG_START 0x3300
#define DOLBY_CORE1_CLKGATE_CTRL 0x33f2
#define DOLBY_CORE1_SWAP_CTRL0 0x33f3
#define DOLBY_CORE1_SWAP_CTRL1 0x33f4
#define DOLBY_CORE1_SWAP_CTRL2 0x33f5
#define DOLBY_CORE1_SWAP_CTRL3 0x33f6
#define DOLBY_CORE1_SWAP_CTRL4 0x33f7
#define DOLBY_CORE1_SWAP_CTRL5 0x33f8
#define DOLBY_CORE1_DMA_CTRL 0x33f9
#define DOLBY_CORE1_DMA_STATUS 0x33fa
#define DOLBY_CORE1_STATUS0 0x33fb
#define DOLBY_CORE1_STATUS1 0x33fc
#define DOLBY_CORE1_STATUS2 0x33fd
#define DOLBY_CORE1_STATUS3 0x33fe
#define DOLBY_CORE1_DMA_PORT 0x33ff
#define DOLBY_CORE2A_REG_START 0x3400
#define DOLBY_CORE2A_CTRL 0x3401
#define DOLBY_CORE2A_CLKGATE_CTRL 0x3432
#define DOLBY_CORE2A_SWAP_CTRL0 0x3433
#define DOLBY_CORE2A_SWAP_CTRL1 0x3434
#define DOLBY_CORE2A_SWAP_CTRL2 0x3435
#define DOLBY_CORE2A_SWAP_CTRL3 0x3436
#define DOLBY_CORE2A_SWAP_CTRL4 0x3437
#define DOLBY_CORE2A_SWAP_CTRL5 0x3438
#define DOLBY_CORE2A_DMA_CTRL 0x3439
#define DOLBY_CORE2A_DMA_STATUS 0x343a
#define DOLBY_CORE2A_STATUS0 0x343b
#define DOLBY_CORE2A_STATUS1 0x343c
#define DOLBY_CORE2A_STATUS2 0x343d
#define DOLBY_CORE2A_STATUS3 0x343e
#define DOLBY_CORE2A_DMA_PORT 0x343f
#define DOLBY_CORE3_REG_START 0x3600
#define DOLBY_CORE3_CLKGATE_CTRL 0x36f0
#define DOLBY_CORE3_SWAP_CTRL0 0x36f1
#define DOLBY_CORE3_SWAP_CTRL1 0x36f2
#define DOLBY_CORE3_SWAP_CTRL2 0x36f3
#define DOLBY_CORE3_SWAP_CTRL3 0x36f4
#define DOLBY_CORE3_SWAP_CTRL4 0x36f5
#define DOLBY_CORE3_SWAP_CTRL5 0x36f6
#define DOLBY_CORE3_SWAP_CTRL6 0x36f7
#define DOLBY_CORE3_CRC_CTRL 0x36fb
#define DOLBY_CORE3_INPUT_CSC_CRC 0x36fc
#define DOLBY_CORE3_OUTPUT_CSC_CRC 0x36fd
#define VIU_MISC_CTRL1 0x1a07
#define VPP_DOLBY_CTRL 0x1d93
#define VIU_SW_RESET 0x1a01
#define VPU_HDMI_FMT_CTRL 0x2743
#if 0
/* core 1 display manager 24 registers */
struct dm_register_ipcore_1_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Frame_Format_1;
uint32_t Frame_Format_2;
uint32_t Frame_Pixel_Def;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t EOTF;
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
};
/* core 1 composer 173 registers */
struct composer_register_ipcore_s {
uint32_t Composer_Mode;
uint32_t VDR_Resolution;
uint32_t Bit_Depth;
uint32_t Coefficient_Log2_Denominator;
uint32_t BL_Num_Pivots_Y;
uint32_t BL_Pivot[5];
uint32_t BL_Order;
uint32_t BL_Coefficient_Y[8][3];
uint32_t EL_NLQ_Offset_Y;
uint32_t EL_Coefficient_Y[3];
uint32_t Mapping_IDC_U;
uint32_t BL_Num_Pivots_U;
uint32_t BL_Pivot_U[3];
uint32_t BL_Order_U;
uint32_t BL_Coefficient_U[4][3];
uint32_t MMR_Coefficient_U[22][2];
uint32_t MMR_Order_U;
uint32_t EL_NLQ_Offset_U;
uint32_t EL_Coefficient_U[3];
uint32_t Mapping_IDC_V;
uint32_t BL_Num_Pivots_V;
uint32_t BL_Pivot_V[3];
uint32_t BL_Order_V;
uint32_t BL_Coefficient_V[4][3];
uint32_t MMR_Coefficient_V[22][2];
uint32_t MMR_Order_V;
uint32_t EL_NLQ_Offset_V;
uint32_t EL_Coefficient_V[3];
};
/* core 2 display manager 24 registers */
struct dm_register_ipcore_2_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t Frame_Format;
uint32_t EOTF;
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
uint32_t C2D_Offset;
uint32_t VDR_Resolution;
};
/* core 3 display manager 26 registers */
struct dm_register_ipcore_3_s {
uint32_t D2C_coefficient_1;
uint32_t D2C_coefficient_2;
uint32_t D2C_coefficient_3;
uint32_t D2C_coefficient_4;
uint32_t D2C_coefficient_5;
uint32_t B2A_Coefficient_1;
uint32_t B2A_Coefficient_2;
uint32_t B2A_Coefficient_3;
uint32_t B2A_Coefficient_4;
uint32_t B2A_Coefficient_5;
uint32_t Eotf_param_1;
uint32_t Eotf_param_2;
uint32_t IPT_Scale;
uint32_t IPT_Offset_1;
uint32_t IPT_Offset_2;
uint32_t IPT_Offset_3;
uint32_t Output_range_1;
uint32_t Output_range_2;
uint32_t RGB2YUV_coefficient_register1;
uint32_t RGB2YUV_coefficient_register2;
uint32_t RGB2YUV_coefficient_register3;
uint32_t RGB2YUV_coefficient_register4;
uint32_t RGB2YUV_coefficient_register5;
uint32_t RGB2YUV_offset_0;
uint32_t RGB2YUV_offset_1;
uint32_t RGB2YUV_offset_2;
};
/* lut 5 * 256 for core 1 and core 2 */
struct dm_lut_ipcore_s {
uint32_t TmLutI[64*4];
uint32_t TmLutS[64*4];
uint32_t SmLutI[64*4];
uint32_t SmLutS[64*4];
uint32_t G2L[256];
};
/* core 3 metadata 128 registers */
struct md_reister_ipcore_3_s {
uint32_t raw_metadata[128];
};
#endif
#endif

39
drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h Normal file
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/*
* drivers/amlogic/media/enhancement/amvecm/arch/vpp_hdr_regs.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef VPP_HDR_REGS_H
#define VPP_HDR_REGS_H
#define XVYCC_LUT_R_ADDR_PORT 0x315e
#define XVYCC_LUT_R_DATA_PORT 0x315f
#define XVYCC_LUT_G_ADDR_PORT 0x3160
#define XVYCC_LUT_G_DATA_PORT 0x3161
#define XVYCC_LUT_B_ADDR_PORT 0x3162
#define XVYCC_LUT_B_DATA_PORT 0x3163
#define XVYCC_INV_LUT_CTL 0x3164
#define XVYCC_LUT_CTL 0x3165
#define XVYCC_INV_LUT_Y_ADDR_PORT 0x3158
#define XVYCC_INV_LUT_Y_DATA_PORT 0x3159
extern struct am_regs_s r_lut_hdr_hdr;
extern struct am_regs_s r_lut_sdr_sdr;
extern struct am_regs_s r_lut_hdr_sdr_level1;
extern struct am_regs_s r_lut_hdr_sdr_level2;
extern struct am_regs_s r_lut_hdr_sdr_level3;
#endif

747
drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h Normal file
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/*
* drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef VPP_REGS_HEADER_
#define VPP_REGS_HEADER_
#define VPP_DUMMY_DATA 0x1d00
#define VPP_LINE_IN_LENGTH 0x1d01
#define VPP_PIC_IN_HEIGHT 0x1d02
#define VPP_SCALE_COEF_IDX 0x1d03
#define VPP_SCALE_COEF 0x1d04
#define VPP_VSC_REGION12_STARTP 0x1d05
#define VPP_VSC_REGION34_STARTP 0x1d06
#define VPP_VSC_REGION4_ENDP 0x1d07
#define VPP_VSC_START_PHASE_STEP 0x1d08
#define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09
#define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a
#define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b
#define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c
#define VPP_VSC_PHASE_CTRL 0x1d0d
#define VPP_VSC_INI_PHASE 0x1d0e
#define VPP_HSC_REGION12_STARTP 0x1d10
#define VPP_HSC_REGION34_STARTP 0x1d11
#define VPP_HSC_REGION4_ENDP 0x1d12
#define VPP_HSC_START_PHASE_STEP 0x1d13
#define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14
#define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15
#define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16
#define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17
#define VPP_HSC_PHASE_CTRL 0x1d18
#define VPP_SC_MISC 0x1d19
#define VPP_PREBLEND_VD1_H_START_END 0x1d1a
#define VPP_PREBLEND_VD1_V_START_END 0x1d1b
#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c
#define VPP_POSTBLEND_VD1_V_START_END 0x1d1d
#define VPP_BLEND_VD2_H_START_END 0x1d1e
#define VPP_BLEND_VD2_V_START_END 0x1d1f
#define VPP_PREBLEND_H_SIZE 0x1d20
#define VPP_POSTBLEND_H_SIZE 0x1d21
#define VPP_HOLD_LINES 0x1d22
#define VPP_BLEND_ONECOLOR_CTRL 0x1d23
#define VPP_PREBLEND_CURRENT_XY 0x1d24
#define VPP_POSTBLEND_CURRENT_XY 0x1d25
#define VPP_MISC 0x1d26
#define VPP_OFIFO_SIZE 0x1d27
#define VPP_FIFO_STATUS 0x1d28
#define VPP_SMOKE_CTRL 0x1d29
#define VPP_SMOKE1_VAL 0x1d2a
#define VPP_SMOKE2_VAL 0x1d2b
#define VPP_SMOKE3_VAL 0x1d2c
#define VPP_SMOKE1_H_START_END 0x1d2d
#define VPP_SMOKE1_V_START_END 0x1d2e
#define VPP_SMOKE2_H_START_END 0x1d2f
#define VPP_SMOKE2_V_START_END 0x1d30
#define VPP_SMOKE3_H_START_END 0x1d31
#define VPP_SMOKE3_V_START_END 0x1d32
#define VPP_SCO_FIFO_CTRL 0x1d33
#define VPP_HSC_PHASE_CTRL1 0x1d34
#define VPP_HSC_INI_PAT_CTRL 0x1d35
#define VPP_VADJ_CTRL 0x1d40
#define VPP_VADJ1_Y 0x1d41
#define VPP_VADJ1_MA_MB 0x1d42
#define VPP_VADJ1_MC_MD 0x1d43
#define VPP_VADJ2_Y 0x1d44
#define VPP_VADJ2_MA_MB 0x1d45
#define VPP_VADJ2_MC_MD 0x1d46
#define VPP_HSHARP_CTRL 0x1d50
#define VPP_HSHARP_LUMA_THRESH01 0x1d51
#define VPP_HSHARP_LUMA_THRESH23 0x1d52
#define VPP_HSHARP_CHROMA_THRESH01 0x1d53
#define VPP_HSHARP_CHROMA_THRESH23 0x1d54
#define VPP_HSHARP_LUMA_GAIN 0x1d55
#define VPP_HSHARP_CHROMA_GAIN 0x1d56
#define VPP_MATRIX_PROBE_COLOR 0x1d5c
#define VPP_MATRIX_PROBE_COLOR1 0x1dd7
#define VPP_MATRIX_HL_COLOR 0x1d5d
#define VPP_MATRIX_PROBE_POS 0x1d5e
#define VPP_MATRIX_CTRL 0x1d5f
#define VPP_MATRIX_COEF00_01 0x1d60
#define VPP_MATRIX_COEF02_10 0x1d61
#define VPP_MATRIX_COEF11_12 0x1d62
#define VPP_MATRIX_COEF20_21 0x1d63
#define VPP_MATRIX_COEF22 0x1d64
#define VPP_MATRIX_OFFSET0_1 0x1d65
#define VPP_MATRIX_OFFSET2 0x1d66
#define VPP_MATRIX_PRE_OFFSET0_1 0x1d67
#define VPP_MATRIX_PRE_OFFSET2 0x1d68
#define VPP_DUMMY_DATA1 0x1d69
#define VPP_GAINOFF_CTRL0 0x1d6a
#define VPP_GAINOFF_CTRL1 0x1d6b
#define VPP_GAINOFF_CTRL2 0x1d6c
#define VPP_GAINOFF_CTRL3 0x1d6d
#define VPP_GAINOFF_CTRL4 0x1d6e
#define VPP_CHROMA_ADDR_PORT 0x1d70
#define VPP_CHROMA_DATA_PORT 0x1d71
#define VPP_GCLK_CTRL0 0x1d72
#define VPP_GCLK_CTRL1 0x1d73
#define VPP_SC_GCLK_CTRL 0x1d74
#define VPP_MISC1 0x1d76
#define VPP_BLACKEXT_CTRL 0x1d80
#define VPP_DNLP_CTRL_00 0x1d81
#define VPP_DNLP_CTRL_01 0x1d82
#define VPP_DNLP_CTRL_02 0x1d83
#define VPP_DNLP_CTRL_03 0x1d84
#define VPP_DNLP_CTRL_04 0x1d85
#define VPP_DNLP_CTRL_05 0x1d86
#define VPP_DNLP_CTRL_06 0x1d87
#define VPP_DNLP_CTRL_07 0x1d88
#define VPP_DNLP_CTRL_08 0x1d89
#define VPP_DNLP_CTRL_09 0x1d8a
#define VPP_DNLP_CTRL_10 0x1d8b
#define VPP_DNLP_CTRL_11 0x1d8c
#define VPP_DNLP_CTRL_12 0x1d8d
#define VPP_DNLP_CTRL_13 0x1d8e
#define VPP_DNLP_CTRL_14 0x1d8f
#define VPP_DNLP_CTRL_15 0x1d90
#define VPP_SRSHARP0_CTRL 0x1d91
#define VPP_SRSHARP1_CTRL 0x1d92
#define VPP_PEAKING_NLP_1 0x1d93
#define VPP_PEAKING_NLP_2 0x1d94
#define VPP_PEAKING_NLP_3 0x1d95
#define VPP_PEAKING_NLP_4 0x1d96
#define VPP_PEAKING_NLP_5 0x1d97
#define VPP_SHARP_LIMIT 0x1d98
#define VPP_VLTI_CTRL 0x1d99
#define VPP_HLTI_CTRL 0x1d9a
#define VPP_CTI_CTRL 0x1d9b
#define VPP_BLUE_STRETCH_1 0x1d9c
#define VPP_BLUE_STRETCH_2 0x1d9d
#define VPP_BLUE_STRETCH_3 0x1d9e
#define VPP_CCORING_CTRL 0x1da0
#define VPP_VE_ENABLE_CTRL 0x1da1
#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2
#define VPP_VE_DEMO_CENTER_BAR 0x1da3
#define VPP_VE_H_V_SIZE 0x1da4
#define VPP_PSR_H_V_SIZE 0x1da5
#define VPP_VDO_MEAS_CTRL 0x1da8
#define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9
#define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa
#define VPP_INPUT_CTRL 0x1dab
#define VPP_CTI_CTRL2 0x1dac
#define VPP_PEAKING_SAT_THD1 0x1dad
#define VPP_PEAKING_SAT_THD2 0x1dae
#define VPP_PEAKING_SAT_THD3 0x1daf
#define VPP_PEAKING_SAT_THD4 0x1db0
#define VPP_PEAKING_SAT_THD5 0x1db1
#define VPP_PEAKING_SAT_THD6 0x1db2
#define VPP_PEAKING_SAT_THD7 0x1db3
#define VPP_PEAKING_SAT_THD8 0x1db4
#define VPP_PEAKING_SAT_THD9 0x1db5
#define VPP_PEAKING_GAIN_ADD1 0x1db6
#define VPP_PEAKING_GAIN_ADD2 0x1db7
#define VPP_PEAKING_DNLP 0x1db8
#define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9
#define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba
#define VPP_FRONT_HLTI_CTRL 0x1dbb
#define VPP_FRONT_CTI_CTRL 0x1dbc
#define VPP_FRONT_CTI_CTRL2 0x1dbd
#define VPP_OSD_VSC_PHASE_STEP 0x1dc0
#define VPP_OSD_VSC_INI_PHASE 0x1dc1
#define VPP_OSD_VSC_CTRL0 0x1dc2
#define VPP_OSD_HSC_PHASE_STEP 0x1dc3
#define VPP_OSD_HSC_INI_PHASE 0x1dc4
#define VPP_OSD_HSC_CTRL0 0x1dc5
#define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6
#define VPP_OSD_SC_DUMMY_DATA 0x1dc7
#define VPP_OSD_SC_CTRL0 0x1dc8
#define VPP_OSD_SCI_WH_M1 0x1dc9
#define VPP_OSD_SCO_H_START_END 0x1dca
#define VPP_OSD_SCO_V_START_END 0x1dcb
#define VPP_OSD_SCALE_COEF_IDX 0x1dcc
#define VPP_OSD_SCALE_COEF 0x1dcd
#define VPP_INT_LINE_NUM 0x1dce
#define VPP_XVYCC_MISC 0x1dcf
#define VPP_CLIP_MISC0 0x1dd9
#define VPP_MATRIX_CLIP 0x1dde
#define VPP_CLIP_MISC1 0x1dda
#define VPP_MATRIX_COEF13_14 0x1ddb
#define VPP_MATRIX_COEF23_24 0x1ddc
#define VPP_MATRIX_COEF15_25 0x1ddd
#define VPP_MATRIX_CLIP 0x1dde
#define VPP_XVYCC_MISC0 0x1ddf
#define VPP_XVYCC_MISC1 0x1de0
#define VPP_VD1_CLIP_MISC0 0x1de1
#define VPP_VD1_CLIP_MISC1 0x1de2
#define VPP_VD2_CLIP_MISC0 0x1de3
#define VPP_VD2_CLIP_MISC1 0x1de4
#define VPP2_DUMMY_DATA 0x1900
#define VPP2_LINE_IN_LENGTH 0x1901
#define VPP2_PIC_IN_HEIGHT 0x1902
#define VPP2_SCALE_COEF_IDX 0x1903
#define VPP2_SCALE_COEF 0x1904
#define VPP2_VSC_REGION12_STARTP 0x1905
#define VPP2_VSC_REGION34_STARTP 0x1906
#define VPP2_VSC_REGION4_ENDP 0x1907
#define VPP2_VSC_START_PHASE_STEP 0x1908
#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a
#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b
#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c
#define VPP2_VSC_PHASE_CTRL 0x190d
#define VPP2_VSC_INI_PHASE 0x190e
#define VPP2_HSC_REGION12_STARTP 0x1910
#define VPP2_HSC_REGION34_STARTP 0x1911
#define VPP2_HSC_REGION4_ENDP 0x1912
#define VPP2_HSC_START_PHASE_STEP 0x1913
#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914
#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915
#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916
#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917
#define VPP2_HSC_PHASE_CTRL 0x1918
#define VPP2_SC_MISC 0x1919
#define VPP2_PREBLEND_VD1_H_START_END 0x191a
#define VPP2_PREBLEND_VD1_V_START_END 0x191b
#define VPP2_POSTBLEND_VD1_H_START_END 0x191c
#define VPP2_POSTBLEND_VD1_V_START_END 0x191d
#define VPP2_PREBLEND_H_SIZE 0x1920
#define VPP2_POSTBLEND_H_SIZE 0x1921
#define VPP2_HOLD_LINES 0x1922
#define VPP2_BLEND_ONECOLOR_CTRL 0x1923
#define VPP2_PREBLEND_CURRENT_XY 0x1924
#define VPP2_POSTBLEND_CURRENT_XY 0x1925
#define VPP2_MISC 0x1926
#define VPP2_OFIFO_SIZE 0x1927
#define VPP2_FIFO_STATUS 0x1928
#define VPP2_SMOKE_CTRL 0x1929
#define VPP2_SMOKE1_VAL 0x192a
#define VPP2_SMOKE2_VAL 0x192b
#define VPP2_SMOKE1_H_START_END 0x192d
#define VPP2_SMOKE1_V_START_END 0x192e
#define VPP2_SMOKE2_H_START_END 0x192f
#define VPP2_SMOKE2_V_START_END 0x1930
#define VPP2_SCO_FIFO_CTRL 0x1933
#define VPP2_HSC_PHASE_CTRL1 0x1934
#define VPP2_HSC_INI_PAT_CTRL 0x1935
#define VPP2_VADJ_CTRL 0x1940
#define VPP2_VADJ1_Y 0x1941
#define VPP2_VADJ1_MA_MB 0x1942
#define VPP2_VADJ1_MC_MD 0x1943
#define VPP2_VADJ2_Y 0x1944
#define VPP2_VADJ2_MA_MB 0x1945
#define VPP2_VADJ2_MC_MD 0x1946
#define VPP2_MATRIX_PROBE_COLOR 0x195c
#define VPP2_MATRIX_HL_COLOR 0x195d
#define VPP2_MATRIX_PROBE_POS 0x195e
#define VPP2_MATRIX_CTRL 0x195f
#define VPP2_MATRIX_COEF00_01 0x1960
#define VPP2_MATRIX_COEF02_10 0x1961
#define VPP2_MATRIX_COEF11_12 0x1962
#define VPP2_MATRIX_COEF20_21 0x1963
#define VPP2_MATRIX_COEF22 0x1964
#define VPP2_MATRIX_OFFSET0_1 0x1965
#define VPP2_MATRIX_OFFSET2 0x1966
#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967
#define VPP2_MATRIX_PRE_OFFSET2 0x1968
#define VPP2_DUMMY_DATA1 0x1969
#define VPP2_GAINOFF_CTRL0 0x196a
#define VPP2_GAINOFF_CTRL1 0x196b
#define VPP2_GAINOFF_CTRL2 0x196c
#define VPP2_GAINOFF_CTRL3 0x196d
#define VPP2_GAINOFF_CTRL4 0x196e
#define VPP2_CHROMA_ADDR_PORT 0x1970
#define VPP2_CHROMA_DATA_PORT 0x1971
#define VPP2_GCLK_CTRL0 0x1972
#define VPP2_GCLK_CTRL1 0x1973
#define VPP2_SC_GCLK_CTRL 0x1974
#define VPP2_MISC1 0x1976
#define VPP2_DNLP_CTRL_00 0x1981
#define VPP2_DNLP_CTRL_01 0x1982
#define VPP2_DNLP_CTRL_02 0x1983
#define VPP2_DNLP_CTRL_03 0x1984
#define VPP2_DNLP_CTRL_04 0x1985
#define VPP2_DNLP_CTRL_05 0x1986
#define VPP2_DNLP_CTRL_06 0x1987
#define VPP2_DNLP_CTRL_07 0x1988
#define VPP2_DNLP_CTRL_08 0x1989
#define VPP2_DNLP_CTRL_09 0x198a
#define VPP2_DNLP_CTRL_10 0x198b
#define VPP2_DNLP_CTRL_11 0x198c
#define VPP2_DNLP_CTRL_12 0x198d
#define VPP2_DNLP_CTRL_13 0x198e
#define VPP2_DNLP_CTRL_14 0x198f
#define VPP2_DNLP_CTRL_15 0x1990
#define VPP2_VE_ENABLE_CTRL 0x19a1
#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2
#define VPP2_VE_DEMO_CENTER_BAR 0x19a3
#define VPP2_VE_H_V_SIZE 0x19a4
#define VPP2_VDO_MEAS_CTRL 0x19a8
#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9
#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa
#define VPP2_OSD_VSC_PHASE_STEP 0x19c0
#define VPP2_OSD_VSC_INI_PHASE 0x19c1
#define VPP2_OSD_VSC_CTRL0 0x19c2
#define VPP2_OSD_HSC_PHASE_STEP 0x19c3
#define VPP2_OSD_HSC_INI_PHASE 0x19c4
#define VPP2_OSD_HSC_CTRL0 0x19c5
#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6
#define VPP2_OSD_SC_DUMMY_DATA 0x19c7
#define VPP2_OSD_SC_CTRL0 0x19c8
#define VPP2_OSD_SCI_WH_M1 0x19c9
#define VPP2_OSD_SCO_H_START_END 0x19ca
#define VPP2_OSD_SCO_V_START_END 0x19cb
#define VPP2_OSD_SCALE_COEF_IDX 0x19cc
#define VPP2_OSD_SCALE_COEF 0x19cd
#define VPP2_INT_LINE_NUM 0x19ce
#define VIU_OSD1_BLK0_CFG_W0 0x1a1b
#define VIU_OSD1_MATRIX_CTRL 0x1a90
#define VIU_OSD1_MATRIX_COEF00_01 0x1a91
#define VIU_OSD1_MATRIX_COEF02_10 0x1a92
#define VIU_OSD1_MATRIX_COEF11_12 0x1a93
#define VIU_OSD1_MATRIX_COEF20_21 0x1a94
#define VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95
#define VIU_OSD1_MATRIX_OFFSET0_1 0x1a96
#define VIU_OSD1_MATRIX_OFFSET2 0x1a97
#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98
#define VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99
#define VIU_OSD1_MATRIX_COEF22_30 0x1a9d
#define VIU_OSD1_MATRIX_COEF31_32 0x1a9e
#define VIU_OSD1_MATRIX_COEF40_41 0x1a9f
#define VIU_OSD1_EOTF_CTL 0x1ad4
#define VIU_OSD1_EOTF_COEF00_01 0x1ad5
#define VIU_OSD1_EOTF_COEF02_10 0x1ad6
#define VIU_OSD1_EOTF_COEF11_12 0x1ad7
#define VIU_OSD1_EOTF_COEF20_21 0x1ad8
#define VIU_OSD1_EOTF_COEF22_RS 0x1ad9
#define VIU_OSD1_EOTF_LUT_ADDR_PORT 0x1ada
#define VIU_OSD1_EOTF_LUT_DATA_PORT 0x1adb
#define VIU_OSD1_OETF_CTL 0x1adc
#define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add
#define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade
#define VI_HIST_CTRL 0x2e00
#define VI_HIST_H_START_END 0x2e01
#define VI_HIST_V_START_END 0x2e02
#define VI_HIST_MAX_MIN 0x2e03
#define VI_HIST_SPL_VAL 0x2e04
#define VI_HIST_SPL_PIX_CNT 0x2e05
#define VI_HIST_CHROMA_SUM 0x2e06
#define VI_DNLP_HIST00 0x2e07
#define VI_DNLP_HIST01 0x2e08
#define VI_DNLP_HIST02 0x2e09
#define VI_DNLP_HIST03 0x2e0a
#define VI_DNLP_HIST04 0x2e0b
#define VI_DNLP_HIST05 0x2e0c
#define VI_DNLP_HIST06 0x2e0d
#define VI_DNLP_HIST07 0x2e0e
#define VI_DNLP_HIST08 0x2e0f
#define VI_DNLP_HIST09 0x2e10
#define VI_DNLP_HIST10 0x2e11
#define VI_DNLP_HIST11 0x2e12
#define VI_DNLP_HIST12 0x2e13
#define VI_DNLP_HIST13 0x2e14
#define VI_DNLP_HIST14 0x2e15
#define VI_DNLP_HIST15 0x2e16
#define VI_DNLP_HIST16 0x2e17
#define VI_DNLP_HIST17 0x2e18
#define VI_DNLP_HIST18 0x2e19
#define VI_DNLP_HIST19 0x2e1a
#define VI_DNLP_HIST20 0x2e1b
#define VI_DNLP_HIST21 0x2e1c
#define VI_DNLP_HIST22 0x2e1d
#define VI_DNLP_HIST23 0x2e1e
#define VI_DNLP_HIST24 0x2e1f
#define VI_DNLP_HIST25 0x2e20
#define VI_DNLP_HIST26 0x2e21
#define VI_DNLP_HIST27 0x2e22
#define VI_DNLP_HIST28 0x2e23
#define VI_DNLP_HIST29 0x2e24
#define VI_DNLP_HIST30 0x2e25
#define VI_DNLP_HIST31 0x2e26
#define VI_HIST_PIC_SIZE 0x2e28
#define VI_HIST_BLACK_WHITE_VALUE 0x2e29
#define VI_HIST_GCLK_CTRL 0x2e2a
#define VPP_IN_H_V_SIZE 0x1da6
/* 3D process */
#define VPU_VPU_3D_SYNC1 0x2738
#define VPU_VPU_3D_SYNC2 0x2739
#define VPU_VPU_PWM_V0 0x2730
#define VPU_VIU_VENC_MUX_CTRL 0x271a
#define VIU_MISC_CTRL0 0x1a06
#define VPU_VLOCK_CTRL 0x3000
#define VPU_VLOCK_MISC_CTRL 0x3001
#define VPU_VLOCK_LOOP0_ACCUM_LMT 0x3002
#define VPU_VLOCK_LOOP0_CTRL0 0x3003
#define VPU_VLOCK_LOOP1_CTRL0 0x3004
#define VPU_VLOCK_LOOP1_IMISSYNC_MAX 0x3005
#define VPU_VLOCK_LOOP1_IMISSYNC_MIN 0x3006
#define VPU_VLOCK_OVWRITE_ACCUM0 0x3007
#define VPU_VLOCK_OVWRITE_ACCUM1 0x3008
#define VPU_VLOCK_OUTPUT0_CAPT_LMT 0x3009
#define VPU_VLOCK_OUTPUT0_PLL_LMT 0x300a
#define VPU_VLOCK_OUTPUT1_CAPT_LMT 0x300b
#define VPU_VLOCK_OUTPUT1_PLL_LMT 0x300c
#define VPU_VLOCK_LOOP1_PHSDIF_TGT 0x300d
#define VPU_VLOCK_RO_LOOP0_ACCUM 0x300e
#define VPU_VLOCK_RO_LOOP1_ACCUM 0x300f
#define VPU_VLOCK_OROW_OCOL_MAX 0x3010
#define VPU_VLOCK_RO_VS_I_DIST 0x3011
#define VPU_VLOCK_RO_VS_O_DIST 0x3012
#define VPU_VLOCK_RO_LINE_PIX_ADJ 0x3013
#define VPU_VLOCK_RO_OUTPUT_00_01 0x3014
#define VPU_VLOCK_RO_OUTPUT_10_11 0x3015
#define VPU_VLOCK_MX4096 0x3016
#define VPU_VLOCK_STBDET_WIN0_WIN1 0x3017
#define VPU_VLOCK_STBDET_CLP 0x3018
#define VPU_VLOCK_STBDET_ABS_WIN0 0x3019
#define VPU_VLOCK_STBDET_ABS_WIN1 0x301a
#define VPU_VLOCK_STBDET_SGN_WIN0 0x301b
#define VPU_VLOCK_STBDET_SGN_WIN1 0x301c
#define VPU_VLOCK_ADJ_EN_SYNC_CTRL 0x301d
#define VPU_VLOCK_GCLK_EN 0x301e
#define VPU_VLOCK_LOOP1_ACCUM_LMT 0x301f
#define VPU_VLOCK_RO_M_INT_FRAC 0x3020
#define XVYCC_VD1_RGB_CTRST 0x3170
#define VIU_EOTF_CTL 0x31d0
#define VIU_EOTF_COEF00_01 0x31d1
#define VIU_EOTF_COEF02_10 0x31d2
#define VIU_EOTF_COEF11_12 0x31d3
#define VIU_EOTF_COEF20_21 0x31d4
#define VIU_EOTF_COEF22_RS 0x31d5
#define VIU_EOTF_LUT_ADDR_PORT 0x31d6
#define VIU_EOTF_LUT_DATA_PORT 0x31d7
/* sharpness */
#define SRSHARP0_PK_FINALGAIN_HP_BP 0x3222
#define SRSHARP0_SHARP_PK_NR_ENABLE 0x3227
#define SRSHARP0_SHARP_DNLP_EN 0x3245
#define SRSHARP1_PK_FINALGAIN_HP_BP 0x32a2
#define SRSHARP1_SHARP_PK_NR_ENABLE 0x32a7
#define SRSHARP1_SHARP_DNLP_EN 0x32c5
/*sr0 sr1 ybic cbic*/
#define SRSHARP0_SHARP_SR2_YBIC_HCOEF0 0x3258
#define SRSHARP0_SHARP_SR2_CBIC_HCOEF0 0x325a
#define SRSHARP0_SHARP_SR2_YBIC_VCOEF0 0x325c
#define SRSHARP0_SHARP_SR2_CBIC_VCOEF0 0x325e
#define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 0x32d8
#define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 0x32da
#define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 0x32dc
#define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 0x32de
/*sr0 sr1 lti cti*/
#define SRSHARP0_HCTI_FLT_CLP_DC 0x322e/*bit28*/
#define SRSHARP0_HLTI_FLT_CLP_DC 0x3234
#define SRSHARP0_VLTI_FLT_CON_CLP 0x323a/*bit14*/
#define SRSHARP0_VCTI_FLT_CON_CLP 0x323f
#define SRSHARP1_HCTI_FLT_CLP_DC 0x32ae/*bit28*/
#define SRSHARP1_HLTI_FLT_CLP_DC 0x32b4
#define SRSHARP1_VLTI_FLT_CON_CLP 0x32ba/*bit14*/
#define SRSHARP1_VCTI_FLT_CON_CLP 0x32bf
/*sr0 sr1 dejaggy/direction/dering*/
#define SRSHARP0_DEJ_CTRL 0x3264/*bit 0*/
#define SRSHARP0_SR3_DRTLPF_EN 0x3266/*bit 0-2*/
#define SRSHARP0_SR3_DERING_CTRL 0x326b/*bit 28-30*/
#define SRSHARP1_DEJ_CTRL 0x32e4/*bit 0*/
#define SRSHARP1_SR3_DRTLPF_EN 0x32e6/*bit 0-2*/
#define SRSHARP1_SR3_DERING_CTRL 0x32eb/*bit 28-30*/
/* for pll bug */
#define HHI_HDMI_PLL_CNTL 0x10c8
#define HHI_HDMI_PLL_CNTL2 0x10c9
#define HHI_VID_LOCK_CLK_CNTL 0x10f2
#define HHI_HDMI_PLL_CNTL6 0x10cd
#define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8
/* #define P_ENCL_MAX_LINE_SWITCH_POINT */
/* VCBUS_REG_ADDR(ENCL_MAX_LINE_SWITCH_POINT) */
#define HHI_VID_LOCK_CLK_CNTL 0x10f2
#define ENCL_VIDEO_MAX_LNCNT 0x1cbb
#define VDIN_MEAS_VS_COUNT_LO 0x125c
/*after GXL new add CNTL1,same with CNTL2 on G9TV/GXTVBB*/
#define HHI_HDMI_PLL_CNTL1 0x10c9
/*after GXL CNTL5[bit3] is same with CNTL6[bit20] on G9TV/GXTVBB*/
#define HHI_HDMI_PLL_CNTL5 0x10cd
/* #define VI_HIST_CTRL 0x2e00 */
/* the total pixels = VDIN_HISTXX*(2^(VDIN_HIST_POW+3)) */
#define VI_HIST_POW_BIT 5
#define VI_HIST_POW_WID 3
/* Histgram range: 0: full picture, 1: histgram window*/
/* defined by VDIN_HIST_H_START_END & VDIN_HIST_V_START_END */
#define VI_HIST_WIN_EN_BIT 1
#define VI_HIST_WIN_EN_WID 1
/* Histgram readback: 0: disable, 1: enable */
#define VI_HIST_RD_EN_BIT 0
#define VI_HIST_RD_EN_WID 1
/* #define VDIN_HIST_H_START_END 0x1231 */
#define VI_HIST_HSTART_BIT 16
#define VI_HIST_HSTART_WID 13
#define VI_HIST_HEND_BIT 0
#define VI_HIST_HEND_WID 13
/* #define VDIN_HIST_V_START_END 0x1232 */
#define VI_HIST_VSTART_BIT 16
#define VI_HIST_VSTART_WID 13
#define VI_HIST_VEND_BIT 0
#define VI_HIST_VEND_WID 13
/* #define VDIN_HIST_MAX_MIN 0x1233 */
#define VI_HIST_MAX_BIT 8
#define VI_HIST_MAX_WID 8
#define VI_HIST_MIN_BIT 0
#define VI_HIST_MIN_WID 8
/* #define VDIN_HIST_SPL_VAL 0x1234 */
#define VI_HIST_LUMA_SUM_BIT 0
#define VI_HIST_LUMA_SUM_WID 32
/* the total calculated pixels */
/* #define VDIN_HIST_SPL_PIX_CNT 0x1235 */
#define VI_HIST_PIX_CNT_BIT 0
#define VI_HIST_PIX_CNT_WID 22
/* the total chroma value */
/* #define VDIN_HIST_CHROMA_SUM 0x1236 */
#define VI_HIST_CHROMA_SUM_BIT 0
#define VI_HIST_CHROMA_SUM_WID 32
/* #define VDIN_DNLP_HIST00 0x1237 */
#define VI_HIST_ON_BIN_01_BIT 16
#define VI_HIST_ON_BIN_01_WID 16
#define VI_HIST_ON_BIN_00_BIT 0
#define VI_HIST_ON_BIN_00_WID 16
/* #define VDIN_DNLP_HIST01 0x1238 */
#define VI_HIST_ON_BIN_03_BIT 16
#define VI_HIST_ON_BIN_03_WID 16
#define VI_HIST_ON_BIN_02_BIT 0
#define VI_HIST_ON_BIN_02_WID 16
/* #define VDIN_DNLP_HIST02 0x1239 */
#define VI_HIST_ON_BIN_05_BIT 16
#define VI_HIST_ON_BIN_05_WID 16
#define VI_HIST_ON_BIN_04_BIT 0
#define VI_HIST_ON_BIN_04_WID 16
/* #define VDIN_DNLP_HIST03 0x123a */
#define VI_HIST_ON_BIN_07_BIT 16
#define VI_HIST_ON_BIN_07_WID 16
#define VI_HIST_ON_BIN_06_BIT 0
#define VI_HIST_ON_BIN_06_WID 16
/* #define VDIN_DNLP_HIST04 0x123b */
#define VI_HIST_ON_BIN_09_BIT 16
#define VI_HIST_ON_BIN_09_WID 16
#define VI_HIST_ON_BIN_08_BIT 0
#define VI_HIST_ON_BIN_08_WID 16
/* #define VDIN_DNLP_HIST05 0x123c */
#define VI_HIST_ON_BIN_11_BIT 16
#define VI_HIST_ON_BIN_11_WID 16
#define VI_HIST_ON_BIN_10_BIT 0
#define VI_HIST_ON_BIN_10_WID 16
/* #define VDIN_DNLP_HIST06 0x123d */
#define VI_HIST_ON_BIN_13_BIT 16
#define VI_HIST_ON_BIN_13_WID 16
#define VI_HIST_ON_BIN_12_BIT 0
#define VI_HIST_ON_BIN_12_WID 16
/* #define VDIN_DNLP_HIST07 0x123e */
#define VI_HIST_ON_BIN_15_BIT 16
#define VI_HIST_ON_BIN_15_WID 16
#define VI_HIST_ON_BIN_14_BIT 0
#define VI_HIST_ON_BIN_14_WID 16
/* #define VDIN_DNLP_HIST08 0x123f */
#define VI_HIST_ON_BIN_17_BIT 16
#define VI_HIST_ON_BIN_17_WID 16
#define VI_HIST_ON_BIN_16_BIT 0
#define VI_HIST_ON_BIN_16_WID 16
/* #define VDIN_DNLP_HIST09 0x1240 */
#define VI_HIST_ON_BIN_19_BIT 16
#define VI_HIST_ON_BIN_19_WID 16
#define VI_HIST_ON_BIN_18_BIT 0
#define VI_HIST_ON_BIN_18_WID 16
/* #define VDIN_DNLP_HIST10 0x1241 */
#define VI_HIST_ON_BIN_21_BIT 16
#define VI_HIST_ON_BIN_21_WID 16
#define VI_HIST_ON_BIN_20_BIT 0
#define VI_HIST_ON_BIN_20_WID 16
/* #define VDIN_DNLP_HIST11 0x1242 */
#define VI_HIST_ON_BIN_23_BIT 16
#define VI_HIST_ON_BIN_23_WID 16
#define VI_HIST_ON_BIN_22_BIT 0
#define VI_HIST_ON_BIN_22_WID 16
/* #define VDIN_DNLP_HIST12 0x1243 */
#define VI_HIST_ON_BIN_25_BIT 16
#define VI_HIST_ON_BIN_25_WID 16
#define VI_HIST_ON_BIN_24_BIT 0
#define VI_HIST_ON_BIN_24_WID 16
/* #define VDIN_DNLP_HIST13 0x1244 */
#define VI_HIST_ON_BIN_27_BIT 16
#define VI_HIST_ON_BIN_27_WID 16
#define VI_HIST_ON_BIN_26_BIT 0
#define VI_HIST_ON_BIN_26_WID 16
/* #define VDIN_DNLP_HIST14 0x1245 */
#define VI_HIST_ON_BIN_29_BIT 16
#define VI_HIST_ON_BIN_29_WID 16
#define VI_HIST_ON_BIN_28_BIT 0
#define VI_HIST_ON_BIN_28_WID 16
/* #define VDIN_DNLP_HIST15 0x1246 */
#define VI_HIST_ON_BIN_31_BIT 16
#define VI_HIST_ON_BIN_31_WID 16
#define VI_HIST_ON_BIN_30_BIT 0
#define VI_HIST_ON_BIN_30_WID 16
/* #define VDIN_DNLP_HIST16 0x1247 */
#define VI_HIST_ON_BIN_33_BIT 16
#define VI_HIST_ON_BIN_33_WID 16
#define VI_HIST_ON_BIN_32_BIT 0
#define VI_HIST_ON_BIN_32_WID 16
/* #define VDIN_DNLP_HIST17 0x1248 */
#define VI_HIST_ON_BIN_35_BIT 16
#define VI_HIST_ON_BIN_35_WID 16
#define VI_HIST_ON_BIN_34_BIT 0
#define VI_HIST_ON_BIN_34_WID 16
/* #define VDIN_DNLP_HIST18 0x1249 */
#define VI_HIST_ON_BIN_37_BIT 16
#define VI_HIST_ON_BIN_37_WID 16
#define VI_HIST_ON_BIN_36_BIT 0
#define VI_HIST_ON_BIN_36_WID 16
/* #define VDIN_DNLP_HIST19 0x124a */
#define VI_HIST_ON_BIN_39_BIT 16
#define VI_HIST_ON_BIN_39_WID 16
#define VI_HIST_ON_BIN_38_BIT 0
#define VI_HIST_ON_BIN_38_WID 16
/* #define VDIN_DNLP_HIST20 0x124b */
#define VI_HIST_ON_BIN_41_BIT 16
#define VI_HIST_ON_BIN_41_WID 16
#define VI_HIST_ON_BIN_40_BIT 0
#define VI_HIST_ON_BIN_40_WID 16
/* #define VDIN_DNLP_HIST21 0x124c */
#define VI_HIST_ON_BIN_43_BIT 16
#define VI_HIST_ON_BIN_43_WID 16
#define VI_HIST_ON_BIN_42_BIT 0
#define VI_HIST_ON_BIN_42_WID 16
/* #define VDIN_DNLP_HIST22 0x124d */
#define VI_HIST_ON_BIN_45_BIT 16
#define VI_HIST_ON_BIN_45_WID 16
#define VI_HIST_ON_BIN_44_BIT 0
#define VI_HIST_ON_BIN_44_WID 16
/* #define VDIN_DNLP_HIST23 0x124e */
#define VI_HIST_ON_BIN_47_BIT 16
#define VI_HIST_ON_BIN_47_WID 16
#define VI_HIST_ON_BIN_46_BIT 0
#define VI_HIST_ON_BIN_46_WID 16
/* #define VDIN_DNLP_HIST24 0x124f */
#define VI_HIST_ON_BIN_49_BIT 16
#define VI_HIST_ON_BIN_49_WID 16
#define VI_HIST_ON_BIN_48_BIT 0
#define VI_HIST_ON_BIN_48_WID 16
/* #define VDIN_DNLP_HIST25 0x1250 */
#define VI_HIST_ON_BIN_51_BIT 16
#define VI_HIST_ON_BIN_51_WID 16
#define VI_HIST_ON_BIN_50_BIT 0
#define VI_HIST_ON_BIN_50_WID 16
/* #define VDIN_DNLP_HIST26 0x1251 */
#define VI_HIST_ON_BIN_53_BIT 16
#define VI_HIST_ON_BIN_53_WID 16
#define VI_HIST_ON_BIN_52_BIT 0
#define VI_HIST_ON_BIN_52_WID 16
/* #define VDIN_DNLP_HIST27 0x1252 */
#define VI_HIST_ON_BIN_55_BIT 16
#define VI_HIST_ON_BIN_55_WID 16
#define VI_HIST_ON_BIN_54_BIT 0
#define VI_HIST_ON_BIN_54_WID 16
/* #define VDIN_DNLP_HIST28 0x1253 */
#define VI_HIST_ON_BIN_57_BIT 16
#define VI_HIST_ON_BIN_57_WID 16
#define VI_HIST_ON_BIN_56_BIT 0
#define VI_HIST_ON_BIN_56_WID 16
/* #define VDIN_DNLP_HIST29 0x1254 */
#define VI_HIST_ON_BIN_59_BIT 16
#define VI_HIST_ON_BIN_59_WID 16
#define VI_HIST_ON_BIN_58_BIT 0
#define VI_HIST_ON_BIN_58_WID 16
/* #define VDIN_DNLP_HIST30 0x1255 */
#define VI_HIST_ON_BIN_61_BIT 16
#define VI_HIST_ON_BIN_61_WID 16
#define VI_HIST_ON_BIN_60_BIT 0
#define VI_HIST_ON_BIN_60_WID 16
/* #define VDIN_DNLP_HIST31 0x1256 */
#define VI_HIST_ON_BIN_63_BIT 16
#define VI_HIST_ON_BIN_63_WID 16
#define VI_HIST_ON_BIN_62_BIT 0
#define VI_HIST_ON_BIN_62_WID 16
/* #define VDIN_HIST_PIC_SIZE 0x2e28 */
#define VI_HIST_PIC_HEIGHT_BIT 16
#define VI_HIST_PIC_HEIGHT_WID 13
#define VI_HIST_PIC_WIDTH_BIT 0
#define VI_HIST_PIC_WIDTH_WID 13
#endif

302
drivers/amlogic/media/enhancement/amvecm/dolby_vision/dolby_vision.h Normal file
View File

@@ -0,0 +1,302 @@
/*
* drivers/amlogic/media/enhancement/amvecm/dolby_vision/dolby_vision.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef _DV_H_
#define _DV_H_
#include <linux/types.h>
#define DEF_G2L_LUT_SIZE_2P 8
#define DEF_G2L_LUT_SIZE (1 << DEF_G2L_LUT_SIZE_2P)
enum signal_format_e {
FORMAT_DOVI = 0,
FORMAT_HDR10 = 1,
FORMAT_SDR = 2
};
enum priority_mode_e {
VIDEO_PRIORITY = 0,
GRAPHIC_PRIORITY = 1
};
enum cp_signal_range_e {
SIG_RANGE_SMPTE = 0, /* head range */
SIG_RANGE_FULL = 1, /* full range */
SIG_RANGE_SDI = 2 /* PQ */
};
struct composer_register_ipcore_s {
uint32_t Composer_Mode;
uint32_t VDR_Resolution;
uint32_t Bit_Depth;
uint32_t Coefficient_Log2_Denominator;
uint32_t BL_Num_Pivots_Y;
uint32_t BL_Pivot[5];
uint32_t BL_Order;
uint32_t BL_Coefficient_Y[8][3];
uint32_t EL_NLQ_Offset_Y;
uint32_t EL_Coefficient_Y[3];
uint32_t Mapping_IDC_U;
uint32_t BL_Num_Pivots_U;
uint32_t BL_Pivot_U[3];
uint32_t BL_Order_U;
uint32_t BL_Coefficient_U[4][3];
uint32_t MMR_Coefficient_U[22][2];
uint32_t MMR_Order_U;
uint32_t EL_NLQ_Offset_U;
uint32_t EL_Coefficient_U[3];
uint32_t Mapping_IDC_V;
uint32_t BL_Num_Pivots_V;
uint32_t BL_Pivot_V[3];
uint32_t BL_Order_V;
uint32_t BL_Coefficient_V[4][3];
uint32_t MMR_Coefficient_V[22][2];
uint32_t MMR_Order_V;
uint32_t EL_NLQ_Offset_V;
uint32_t EL_Coefficient_V[3];
};
/** @brief DM registers for IPCORE 1 */
struct dm_register_ipcore_1_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Frame_Format_1;
uint32_t Frame_Format_2;
uint32_t Frame_Pixel_Def;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t EOTF;
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
uint32_t C2D_Offset;
uint32_t Active_area_left_top;
uint32_t Active_area_bottom_right;
};
/** @brief DM registers for IPCORE 2 */
struct dm_register_ipcore_2_s {
uint32_t SRange;
uint32_t Srange_Inverse;
uint32_t Y2RGB_Coefficient_1;
uint32_t Y2RGB_Coefficient_2;
uint32_t Y2RGB_Coefficient_3;
uint32_t Y2RGB_Coefficient_4;
uint32_t Y2RGB_Coefficient_5;
uint32_t Y2RGB_Offset_1;
uint32_t Y2RGB_Offset_2;
uint32_t Y2RGB_Offset_3;
uint32_t Frame_Format;
uint32_t EOTF;
uint32_t A2B_Coefficient_1;
uint32_t A2B_Coefficient_2;
uint32_t A2B_Coefficient_3;
uint32_t A2B_Coefficient_4;
uint32_t A2B_Coefficient_5;
uint32_t C2D_Coefficient_1;
uint32_t C2D_Coefficient_2;
uint32_t C2D_Coefficient_3;
uint32_t C2D_Coefficient_4;
uint32_t C2D_Coefficient_5;
uint32_t C2D_Offset;
uint32_t VDR_Resolution;
};
/** @brief DM registers for IPCORE 3 */
struct dm_register_ipcore_3_s {
uint32_t D2C_coefficient_1;
uint32_t D2C_coefficient_2;
uint32_t D2C_coefficient_3;
uint32_t D2C_coefficient_4;
uint32_t D2C_coefficient_5;
uint32_t B2A_Coefficient_1;
uint32_t B2A_Coefficient_2;
uint32_t B2A_Coefficient_3;
uint32_t B2A_Coefficient_4;
uint32_t B2A_Coefficient_5;
uint32_t Eotf_param_1;
uint32_t Eotf_param_2;
uint32_t IPT_Scale;
uint32_t IPT_Offset_1;
uint32_t IPT_Offset_2;
uint32_t IPT_Offset_3;
uint32_t Output_range_1;
uint32_t Output_range_2;
uint32_t RGB2YUV_coefficient_register1;
uint32_t RGB2YUV_coefficient_register2;
uint32_t RGB2YUV_coefficient_register3;
uint32_t RGB2YUV_coefficient_register4;
uint32_t RGB2YUV_coefficient_register5;
uint32_t RGB2YUV_offset_0;
uint32_t RGB2YUV_offset_1;
uint32_t RGB2YUV_offset_2;
};
/** @brief DM luts for IPCORE 1 and 2 */
struct dm_lut_ipcore_s {
uint32_t TmLutI[64*4];
uint32_t TmLutS[64*4];
uint32_t SmLutI[64*4];
uint32_t SmLutS[64*4];
uint32_t G2L[DEF_G2L_LUT_SIZE];
};
/** @brief hdmi metadata for IPCORE 3 */
struct md_reister_ipcore_3_s {
uint32_t raw_metadata[128];
uint32_t size;
};
struct hdr_10_infoframe_s {
uint8_t infoframe_type_code;
uint8_t infoframe_version_number;
uint8_t length_of_info_frame;
uint8_t data_byte_1;
uint8_t data_byte_2;
uint8_t display_primaries_x_0_LSB;
uint8_t display_primaries_x_0_MSB;
uint8_t display_primaries_y_0_LSB;
uint8_t display_primaries_y_0_MSB;
uint8_t display_primaries_x_1_LSB;
uint8_t display_primaries_x_1_MSB;
uint8_t display_primaries_y_1_LSB;
uint8_t display_primaries_y_1_MSB;
uint8_t display_primaries_x_2_LSB;
uint8_t display_primaries_x_2_MSB;
uint8_t display_primaries_y_2_LSB;
uint8_t display_primaries_y_2_MSB;
uint8_t white_point_x_LSB;
uint8_t white_point_x_MSB;
uint8_t white_point_y_LSB;
uint8_t white_point_y_MSB;
uint8_t max_display_mastering_luminance_LSB;
uint8_t max_display_mastering_luminance_MSB;
uint8_t min_display_mastering_luminance_LSB;
uint8_t min_display_mastering_luminance_MSB;
uint8_t max_content_light_level_LSB;
uint8_t max_content_light_level_MSB;
uint8_t max_frame_average_light_level_LSB;
uint8_t max_frame_average_light_level_MSB;
};
struct hdr10_param_s {
uint32_t min_display_mastering_luminance;
uint32_t max_display_mastering_luminance;
uint16_t Rx;
uint16_t Ry;
uint16_t Gx;
uint16_t Gy;
uint16_t Bx;
uint16_t By;
uint16_t Wx;
uint16_t Wy;
uint16_t max_content_light_level;
uint16_t max_pic_average_light_level;
};
struct dovi_setting_s {
struct composer_register_ipcore_s comp_reg;
struct dm_register_ipcore_1_s dm_reg1;
struct dm_register_ipcore_2_s dm_reg2;
struct dm_register_ipcore_3_s dm_reg3;
struct dm_lut_ipcore_s dm_lut1;
struct dm_lut_ipcore_s dm_lut2;
/* for dovi output */
struct md_reister_ipcore_3_s md_reg3;
/* for hdr10 output */
struct hdr_10_infoframe_s hdr_info;
/* current process */
enum signal_format_e src_format;
enum signal_format_e dst_format;
/* enhanced layer */
bool el_flag;
bool el_halfsize_flag;
/* frame width & height */
uint32_t video_width;
uint32_t video_height;
};
extern int control_path(
enum signal_format_e in_format,
enum signal_format_e out_format,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
enum priority_mode_e set_priority,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
int set_graphic_min_lum, int set_graphic_max_lum,
int set_target_min_lum, int set_target_max_lum,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct dovi_setting_s *output);
extern void *metadata_parser_init(int flag);
extern int metadata_parser_reset(int flag);
extern int metadata_parser_process(
char *src_rpu, int rpu_len,
char *dst_comp, int *comp_len,
char *dst_md, int *md_len, bool src_eos);
extern void metadata_parser_release(void);
struct dolby_vision_func_s {
void * (*metadata_parser_init)(int);
int (*metadata_parser_reset)(int flag);
int (*metadata_parser_process)(
char *src_rpu, int rpu_len,
char *dst_comp, int *comp_len,
char *dst_md, int *md_len, bool src_eos);
void (*metadata_parser_release)(void);
int (*control_path)(
enum signal_format_e in_format,
enum signal_format_e out_format,
char *in_comp, int in_comp_size,
char *in_md, int in_md_size,
enum priority_mode_e set_priority,
int set_bit_depth, int set_chroma_format, int set_yuv_range,
int set_graphic_min_lum, int set_graphic_max_lum,
int set_target_min_lum, int set_target_max_lum,
int set_no_el,
struct hdr10_param_s *hdr10_param,
struct dovi_setting_s *output);
};
extern int register_dv_functions(const struct dolby_vision_func_s *func);
extern int unregister_dv_functions(void);
#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val)
#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr)
#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
WRITE_VPP_REG_BITS(adr, val, start, len)
#else
extern int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
extern u32 VSYNC_RD_MPEG_REG(u32 adr);
extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
#endif
#endif

6
drivers/amlogic/media/video_sink/video.c
View File

@@ -49,7 +49,7 @@
#include <linux/amlogic/media/video_sink/video_keeper.h>
#include "video_priv.h"
#if defined(CONFIG_AM_VECM)
#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM)
#include <linux/amlogic/media/amvecm/amvecm.h>
#endif
#include <linux/amlogic/media/utils/vdec_reg.h>
@@ -3671,7 +3671,7 @@ static irqreturn_t vsync_isr(int irq, void *dev_id)
}
#endif
#if defined(CONFIG_AM_VECM)
#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM)
amvecm_on_vs(vf);
#endif
#ifdef CONFIG_TVIN_VDIN
@@ -3876,7 +3876,7 @@ static irqreturn_t vsync_isr(int irq, void *dev_id)
}
#endif
#if defined(CONFIG_AM_VECM)
#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM)
refresh_on_vs(vf);
#endif

199
include/linux/amlogic/media/amvecm/amvecm.h Normal file
View File

@@ -0,0 +1,199 @@
/*
* include/linux/amlogic/media/amvecm/amvecm.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef AMVECM_H
#define AMVECM_H
#include "linux/amlogic/media/amvecm/ve.h"
#include "linux/amlogic/media/amvecm/cm.h"
#include <linux/amlogic/media/utils/amstream.h>
#include <linux/amlogic/cpu_version.h>
/* struct ve_dnlp_s video_ve_dnlp; */
#define FLAG_RSV31 (1 << 31)
#define FLAG_VADJ1_COLOR (1 << 30)
#define FLAG_VE_DNLP (1 << 29)
#define FLAG_VE_NEW_DNLP (1 << 28)
#define FLAG_RSV27 (1 << 27)
#define FLAG_RSV26 (1 << 26)
#define FLAG_3D_BLACK_DIS (1 << 25)
#define FLAG_3D_BLACK_EN (1 << 24)
#define FLAG_3D_SYNC_DIS (1 << 23)
#define FLAG_3D_SYNC_EN (1 << 22)
#define FLAG_VLOCK_DIS (1 << 21)
#define FLAG_VLOCK_EN (1 << 20)
#define FLAG_VE_DNLP_EN (1 << 19)
#define FLAG_VE_DNLP_DIS (1 << 18)
#define FLAG_VADJ1_CON (1 << 17)
#define FLAG_VADJ1_BRI (1 << 16)
#define FLAG_GAMMA_TABLE_EN (1 << 15)
#define FLAG_GAMMA_TABLE_DIS (1 << 14)
#define FLAG_GAMMA_TABLE_R (1 << 13)
#define FLAG_GAMMA_TABLE_G (1 << 12)
#define FLAG_GAMMA_TABLE_B (1 << 11)
#define FLAG_RGB_OGO (1 << 10)
#define FLAG_RSV9 (1 << 9)
#define FLAG_MATRIX_UPDATE (1 << 8)
#define FLAG_BRI_CON (1 << 7)
#define FLAG_LVDS_FREQ_SW (1 << 6)
#define FLAG_REG_MAP5 (1 << 5)
#define FLAG_REG_MAP4 (1 << 4)
#define FLAG_REG_MAP3 (1 << 3)
#define FLAG_REG_MAP2 (1 << 2)
#define FLAG_REG_MAP1 (1 << 1)
#define FLAG_REG_MAP0 (1 << 0)
#define VPP_VADJ2_BLMINUS_EN (1 << 3)
#define VPP_VADJ2_EN (1 << 2)
#define VPP_VADJ1_BLMINUS_EN (1 << 1)
#define VPP_VADJ1_EN (1 << 0)
#define VPP_DEMO_DNLP_DIS (1 << 3)
#define VPP_DEMO_DNLP_EN (1 << 2)
#define VPP_DEMO_CM_DIS (1 << 1)
#define VPP_DEMO_CM_EN (1 << 0)
/*white balance latch*/
#define MTX_BYPASS_RGB_OGO (1 << 0)
#define MTX_RGB2YUVL_RGB_OGO (1 << 1)
#define _VE_CM 'C'
#define AMVECM_IOC_VE_DNLP _IOW(_VE_CM, 0x21, struct ve_dnlp_s)
#define AMVECM_IOC_G_HIST_AVG _IOW(_VE_CM, 0x22, struct ve_hist_s)
#define AMVECM_IOC_VE_DNLP_EN _IO(_VE_CM, 0x23)
#define AMVECM_IOC_VE_DNLP_DIS _IO(_VE_CM, 0x24)
#define AMVECM_IOC_VE_NEW_DNLP _IOW(_VE_CM, 0x25, struct ve_dnlp_table_s)
#define AMVECM_IOC_G_HIST_BIN _IOW(_VE_CM, 0x26, struct vpp_hist_param_s)
#define AMVECM_IOC_G_HDR_METADATA _IOW(_VE_CM, 0x27, struct hdr_metadata_info_s)
/* VPP.CM IOCTL command list */
#define AMVECM_IOC_LOAD_REG _IOW(_VE_CM, 0x30, struct am_regs_s)
/* VPP.GAMMA IOCTL command list */
#define AMVECM_IOC_GAMMA_TABLE_EN _IO(_VE_CM, 0x40)
#define AMVECM_IOC_GAMMA_TABLE_DIS _IO(_VE_CM, 0x41)
#define AMVECM_IOC_GAMMA_TABLE_R _IOW(_VE_CM, 0x42, struct tcon_gamma_table_s)
#define AMVECM_IOC_GAMMA_TABLE_G _IOW(_VE_CM, 0x43, struct tcon_gamma_table_s)
#define AMVECM_IOC_GAMMA_TABLE_B _IOW(_VE_CM, 0x44, struct tcon_gamma_table_s)
#define AMVECM_IOC_S_RGB_OGO _IOW(_VE_CM, 0x45, struct tcon_rgb_ogo_s)
#define AMVECM_IOC_G_RGB_OGO _IOR(_VE_CM, 0x46, struct tcon_rgb_ogo_s)
/*VPP.VLOCK IOCTL command list*/
#define AMVECM_IOC_VLOCK_EN _IO(_VE_CM, 0x47)
#define AMVECM_IOC_VLOCK_DIS _IO(_VE_CM, 0x48)
/*VPP.3D-SYNC IOCTL command list*/
#define AMVECM_IOC_3D_SYNC_EN _IO(_VE_CM, 0x49)
#define AMVECM_IOC_3D_SYNC_DIS _IO(_VE_CM, 0x50)
/* #if (MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8) */
/* #define WRITE_VPP_REG(x,val)*/
/* WRITE_VCBUS_REG(x,val) */
/* #define WRITE_VPP_REG_BITS(x,val,start,length)*/
/* WRITE_VCBUS_REG_BITS(x,val,start,length) */
/* #define READ_VPP_REG(x)*/
/* READ_VCBUS_REG(x) */
/* #define READ_VPP_REG_BITS(x,start,length)*/
/* READ_VCBUS_REG_BITS(x,start,length) */
/* #else */
/* #define WRITE_VPP_REG(x,val)*/
/* WRITE_CBUS_REG(x,val) */
/* #define WRITE_VPP_REG_BITS(x,val,start,length)*/
/* WRITE_CBUS_REG_BITS(x,val,start,length) */
/* #define READ_VPP_REG(x)*/
/* READ_CBUS_REG(x) */
/* #define READ_VPP_REG_BITS(x,start,length)*/
/* READ_CBUS_REG_BITS(x,start,length) */
/* #endif */
static inline void WRITE_VPP_REG(uint32_t reg,
const uint32_t value)
{
aml_write_vcbus(reg, value);
}
static inline uint32_t READ_VPP_REG(uint32_t reg)
{
return aml_read_vcbus(reg);
}
static inline void WRITE_VPP_REG_BITS(uint32_t reg,
const uint32_t value,
const uint32_t start,
const uint32_t len)
{
WRITE_VPP_REG(reg, ((READ_VPP_REG(reg) &
~(((1L << (len)) - 1) << (start))) |
(((value) & ((1L << (len)) - 1)) << (start))));
}
static inline uint32_t READ_VPP_REG_BITS(uint32_t reg,
const uint32_t start,
const uint32_t len)
{
uint32_t val;
val = ((READ_VPP_REG(reg) >> (start)) & ((1L << (len)) - 1));
return val;
}
extern signed int vd1_brightness, vd1_contrast;
extern bool gamma_en;
extern void amvecm_on_vs(struct vframe_s *vf);
extern void refresh_on_vs(struct vframe_s *vf);
extern void pc_mode_process(void);
/* master_display_info for display device */
struct hdr_metadata_info_s {
u32 primaries[3][2]; /* normalized 50000 in G,B,R order */
u32 white_point[2]; /* normalized 50000 */
u32 luminance[2]; /* max/min lumin, normalized 10000 */
};
extern void vpp_vd_adj1_saturation_hue(signed int sat_val,
signed int hue_val, struct vframe_s *vf);
extern int metadata_read_u32(uint32_t *value);
extern int metadata_wait(struct vframe_s *vf);
extern int metadata_sync(uint32_t frame_id, uint64_t pts);
extern void enable_dolby_vision(int enable);
extern bool is_dolby_vision_enable(void);
extern bool is_dolby_vision_on(void);
extern bool for_dolby_vision_certification(void);
extern void set_dolby_vision_mode(int mode);
extern int get_dolby_vision_mode(void);
extern void dolby_vision_set_toggle_flag(int flag);
extern int dolby_vision_wait_metadata(struct vframe_s *vf);
extern int dolby_vision_pop_metadata(void);
extern int dolby_vision_update_metadata(struct vframe_s *vf);
extern int dolby_vision_process(struct vframe_s *vf);
extern void dolby_vision_init_receiver(void);
extern void dolby_vision_vf_put(struct vframe_s *vf);
extern struct vframe_s *dolby_vision_vf_peek_el(struct vframe_s *vf);
extern void dolby_vision_dump_setting(int debug_flag);
extern void dolby_vision_dump_struct(void);
extern void enable_osd_path(int on);
#endif /* AMVECM_H */

105
include/linux/amlogic/media/amvecm/cm.h
View File

@@ -1,27 +1,20 @@
/*
* Color Management
* include/linux/amlogic/media/amvecm/cm.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
* Copyright (C) 2010 Amlogic Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _TVOUT_CM_H
#define _TVOUT_CM_H
/* ******************************************************************* */
/* *** enum definitions ********************************************* */
/* ******************************************************************* */
enum cm_region_idx_e {
@@ -65,57 +58,55 @@ enum cm_csc_e {
};
/* ******************************************************************* */
/* *** struct definitions ********************************************* */
/* ******************************************************************* */
struct cm_region_s {
enum cm_region_idx_e region_idx;
/* sym */
unsigned char sym_en;
unsigned char sym_en;
/* sat - top */
unsigned char sat_en;
unsigned char sat_central_en;
unsigned char sat_en;
unsigned char sat_central_en;
enum cm_sat_shape_e sat_shape;
unsigned char sat_gain;
unsigned char sat_inc;
unsigned char sat_gain;
unsigned char sat_inc;
/* sat - lum */
unsigned char sat_lum_h_slope;
unsigned char sat_lum_l_slope;
unsigned char sat_lum_h;
unsigned char sat_lum_l;
unsigned char sat_lum_h_slope;
unsigned char sat_lum_l_slope;
unsigned char sat_lum_h;
unsigned char sat_lum_l;
/* sat - sat */
unsigned char sat_sat_h_slope;
unsigned char sat_sat_l_slope;
unsigned char sat_sat_h;
unsigned char sat_sat_l;
unsigned char sat_sat_h_slope;
unsigned char sat_sat_l_slope;
unsigned char sat_sat_h;
unsigned char sat_sat_l;
/* hue - top */
unsigned char hue_en;
unsigned char hue_central_en;
unsigned char hue_en;
unsigned char hue_central_en;
enum cm_hue_shape_e hue_shape;
unsigned char hue_gain;
unsigned char hue_clockwise;
unsigned char hue_shf_ran;
unsigned short hue_shf_sta;
unsigned char hue_gain;
unsigned char hue_clockwise;
unsigned char hue_shf_ran;
unsigned short hue_shf_sta;
/* hue - lum */
unsigned char hue_lum_h_slope;
unsigned char hue_lum_l_slope;
unsigned char hue_lum_h;
unsigned char hue_lum_l;
unsigned char hue_lum_h_slope;
unsigned char hue_lum_l_slope;
unsigned char hue_lum_h;
unsigned char hue_lum_l;
/* hue - sat */
unsigned char hue_sat_h_slope;
unsigned char hue_sat_l_slope;
unsigned char hue_sat_h;
unsigned char hue_sat_l;
unsigned char hue_sat_h_slope;
unsigned char hue_sat_l_slope;
unsigned char hue_sat_h;
unsigned char hue_sat_l;
};
struct cm_top_s {
unsigned char chroma_en;
enum cm_sat_sel_e sat_sel;
unsigned char uv_adj_en;
unsigned char rgb_to_hue_en;
enum cm_csc_e csc_sel;
unsigned char chroma_en;
enum cm_sat_sel_e sat_sel;
unsigned char uv_adj_en;
unsigned char rgb_to_hue_en;
enum cm_csc_e csc_sel;
};
struct cm_cbar_s {
@@ -126,11 +117,11 @@ struct cm_cbar_s {
unsigned char y;
};
struct cm_demo_s {
unsigned char en;
enum cm_demo_pos_e pos;
unsigned char hlight_adj;
unsigned short wid;
struct cm_cbar_s cbar;
unsigned char en;
enum cm_demo_pos_e pos;
unsigned char hlight_adj;
unsigned short wid;
struct cm_cbar_s cbar;
};
struct cm_regmap_s {
@@ -154,15 +145,15 @@ enum reg_bus_type_e {
/* Register table structure */
struct am_reg_s {
unsigned int type; /* 32-bits; 0: CBUS; 1: APB BUS... */
unsigned int addr; /* 32-bits; Register address */
unsigned int mask; /* 32-bits; Valid bits */
unsigned int val; /* 32-bits; Register Value */
unsigned int type; /* 32-bits; 0: CBUS; 1: APB BUS... */
unsigned int addr; /* 32-bits; Register address */
unsigned int mask; /* 32-bits; Valid bits */
unsigned int val; /* 32-bits; Register Value */
};
#define am_reg_size 900
struct am_regs_s {
unsigned int length; /* Length of total am_reg */
unsigned int length; /* Length of total am_reg */
struct am_reg_s am_reg[am_reg_size];
};
#endif /* _TVOUT_CM_H */
#endif /* _TVOUT_CM_H */

336
include/linux/amlogic/media/amvecm/ve.h Normal file
View File

@@ -0,0 +1,336 @@
/*
* include/linux/amlogic/media/amvecm/ve.h
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#ifndef __VE_H
#define __VE_H
/* ******************************************************************* */
/* *** enum definitions ********************************************* */
/* ******************************************************************* */
enum ve_demo_pos_e {
VE_DEMO_POS_TOP = 0,
VE_DEMO_POS_BOTTOM,
VE_DEMO_POS_LEFT,
VE_DEMO_POS_RIGHT,
};
enum ve_dnlp_rt_e {
VE_DNLP_RT_0S = 0,
VE_DNLP_RT_1S = 6,
VE_DNLP_RT_2S,
VE_DNLP_RT_4S,
VE_DNLP_RT_8S,
VE_DNLP_RT_16S,
VE_DNLP_RT_32S,
VE_DNLP_RT_64S,
VE_DNLP_RT_FREEZE,
};
/* ******************************************************************* */
/* *** struct definitions ********************************************* */
/* ******************************************************************* */
struct ve_bext_s {
unsigned char en;
unsigned char start;
unsigned char slope1;
unsigned char midpt;
unsigned char slope2;
};
#if defined(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM)
struct ve_dnlp_s {
unsigned int en;
unsigned int rt; /* 0 ~ 255, */
unsigned int rl; /* 0 ~ 15, 1.0000x ~ 1.9375x, step 0.0625x */
unsigned int black; /* 0 ~ 16, weak ~ strong */
unsigned int white; /* 0 ~ 16, weak ~ strong */
};
struct ve_hist_s {
ulong sum;
int width;
int height;
int ave;
};
struct ve_dnlp_table_s {
unsigned int en;
unsigned int method;
unsigned int cliprate;
unsigned int lowrange;
unsigned int hghrange;
unsigned int lowalpha;
unsigned int midalpha;
unsigned int hghalpha;
unsigned int adj_level;
unsigned int new_adj_level;
unsigned int new_mvreflsh;
unsigned int new_gmma_rate;
unsigned int new_lowalpha;
unsigned int new_hghalpha;
unsigned int new_sbgnbnd;
unsigned int new_sendbnd;
unsigned int new_clashBgn;
unsigned int new_clashEnd;
unsigned int new_cliprate;
unsigned int new_mtdbld_rate;
unsigned int new_dnlp_pst_gmarat;
unsigned int dnlp_sel;
unsigned int dnlp_blk_cctr;/*blk signal add brightness*/
unsigned int dnlp_brgt_ctrl;
unsigned int dnlp_brgt_range;
unsigned int dnlp_brght_add;
unsigned int dnlp_brght_max;
unsigned int dnlp_almst_wht;
unsigned int dnlp_hghbin;/*1*/
unsigned int dnlp_hghnum;
unsigned int dnlp_lowbin;
unsigned int dnlp_lownum;
unsigned int dnlp_bkgend;
unsigned int dnlp_bkgert;
unsigned int dnlp_blkext;
unsigned int dnlp_whtext;
unsigned int dnlp_bextmx;
unsigned int dnlp_wextmx;
unsigned int dnlp_smhist_ck;
unsigned int dnlp_glb_crate;/*12*/
unsigned int dnlp_pstgma_brghtrate;
unsigned int dnlp_pstgma_brghtrat1;
unsigned int dnlp_wext_autorat;
unsigned int dnlp_cliprate_min;
unsigned int dnlp_adpcrat_lbnd;
unsigned int dnlp_adpcrat_hbnd;
unsigned int dnlp_adpmtd_lbnd;
unsigned int dnlp_adpmtd_hbnd;
unsigned int dnlp_set_bext;
unsigned int dnlp_set_wext;
unsigned int dnlp_satur_rat;
unsigned int dnlp_satur_max;
unsigned int blk_prct_rng;
unsigned int blk_prct_max;
unsigned int dnlp_lowrange;
unsigned int dnlp_hghrange;
unsigned int dnlp_auto_rng;
unsigned int dnlp_bin0_absmax;
unsigned int dnlp_bin0_sbtmax;
unsigned int dnlp_adpalpha_lrate;
unsigned int dnlp_adpalpha_hrate;
unsigned int dnlp_lrate00;/*0-64bin curve slope*/
unsigned int dnlp_lrate02;
unsigned int dnlp_lrate04;
unsigned int dnlp_lrate06;
unsigned int dnlp_lrate08;
unsigned int dnlp_lrate10;
unsigned int dnlp_lrate12;
unsigned int dnlp_lrate14;
unsigned int dnlp_lrate16;
unsigned int dnlp_lrate18;
unsigned int dnlp_lrate20;
unsigned int dnlp_lrate22;
unsigned int dnlp_lrate24;
unsigned int dnlp_lrate26;
unsigned int dnlp_lrate28;
unsigned int dnlp_lrate30;
unsigned int dnlp_lrate32;
unsigned int dnlp_lrate34;
unsigned int dnlp_lrate36;
unsigned int dnlp_lrate38;
unsigned int dnlp_lrate40;
unsigned int dnlp_lrate42;
unsigned int dnlp_lrate44;
unsigned int dnlp_lrate46;
unsigned int dnlp_lrate48;
unsigned int dnlp_lrate50;
unsigned int dnlp_lrate52;
unsigned int dnlp_lrate54;
unsigned int dnlp_lrate56;
unsigned int dnlp_lrate58;
unsigned int dnlp_lrate60;
unsigned int dnlp_lrate62;
};
struct vpp_hist_param_s {
unsigned int vpp_hist_pow;
unsigned int vpp_luma_sum;
unsigned int vpp_pixel_sum;
unsigned short vpp_histgram[64];
};
#else
struct ve_dnlp_s {
unsigned char en;
enum ve_dnlp_rt_e rt;
unsigned char gamma[64];
};
#endif
struct ve_hsvs_s {
unsigned char en;
unsigned char peak_gain_h1;
unsigned char peak_gain_h2;
unsigned char peak_gain_h3;
unsigned char peak_gain_h4;
unsigned char peak_gain_h5;
unsigned char peak_gain_v1;
unsigned char peak_gain_v2;
unsigned char peak_gain_v3;
unsigned char peak_gain_v4;
unsigned char peak_gain_v5;
unsigned char peak_gain_v6;
unsigned char hpeak_slope1;
unsigned char hpeak_slope2;
unsigned char hpeak_thr1;
unsigned char hpeak_thr2;
unsigned char hpeak_nlp_cor_thr;
unsigned char hpeak_nlp_gain_pos;
unsigned char hpeak_nlp_gain_neg;
unsigned char vpeak_slope1;
unsigned char vpeak_slope2;
unsigned char vpeak_thr1;
unsigned char vpeak_thr2;
unsigned char vpeak_nlp_cor_thr;
unsigned char vpeak_nlp_gain_pos;
unsigned char vpeak_nlp_gain_neg;
unsigned char speak_slope1;
unsigned char speak_slope2;
unsigned char speak_thr1;
unsigned char speak_thr2;
unsigned char speak_nlp_cor_thr;
unsigned char speak_nlp_gain_pos;
unsigned char speak_nlp_gain_neg;
unsigned char peak_cor_gain;
unsigned char peak_cor_thr_l;
unsigned char peak_cor_thr_h;
unsigned char vlti_step;
unsigned char vlti_step2;
unsigned char vlti_thr;
unsigned char vlti_gain_pos;
unsigned char vlti_gain_neg;
unsigned char vlti_blend_factor;
unsigned char hlti_step;
unsigned char hlti_thr;
unsigned char hlti_gain_pos;
unsigned char hlti_gain_neg;
unsigned char hlti_blend_factor;
unsigned char vlimit_coef_h;
unsigned char vlimit_coef_l;
unsigned char hlimit_coef_h;
unsigned char hlimit_coef_l;
unsigned char cti_444_422_en;
unsigned char cti_422_444_en;
unsigned char cti_blend_factor;
unsigned char vcti_buf_en;
unsigned char vcti_buf_mode_c5l;
unsigned char vcti_filter;
unsigned char hcti_step;
unsigned char hcti_step2;
unsigned char hcti_thr;
unsigned char hcti_gain;
unsigned char hcti_mode_median;
};
struct ve_ccor_s {
unsigned char en;
unsigned char slope;
unsigned char thr;
};
struct ve_benh_s {
unsigned char en;
unsigned char cb_inc;
unsigned char cr_inc;
unsigned char gain_cr;
unsigned char gain_cb4cr;
unsigned char luma_h;
unsigned char err_crp;
unsigned char err_crn;
unsigned char err_cbp;
unsigned char err_cbn;
};
struct ve_cbar_s {
unsigned char en;
unsigned char wid;
unsigned char cr;
unsigned char cb;
unsigned char y;
};
struct ve_demo_s {
unsigned char bext;
unsigned char dnlp;
unsigned char hsvs;
unsigned char ccor;
unsigned char benh;
enum ve_demo_pos_e pos;
unsigned long wid;
struct ve_cbar_s cbar;
};
struct vdo_meas_s {
/* ... */
};
struct ve_regmap_s {
unsigned long reg[43];
};
#define EOTF_LUT_SIZE 33
#define OSD_OETF_LUT_SIZE 41
/********************OSD HDR registers backup********************************/
struct hdr_osd_lut_s {
uint32_t r_map[33];
uint32_t g_map[33];
uint32_t b_map[33];
uint32_t or_map[41];
uint32_t og_map[41];
uint32_t ob_map[41];
};
struct hdr_osd_reg_s {
uint32_t viu_osd1_matrix_ctrl; /* 0x1a90 */
uint32_t viu_osd1_matrix_coef00_01; /* 0x1a91 */
uint32_t viu_osd1_matrix_coef02_10; /* 0x1a92 */
uint32_t viu_osd1_matrix_coef11_12; /* 0x1a93 */
uint32_t viu_osd1_matrix_coef20_21; /* 0x1a94 */
uint32_t viu_osd1_matrix_colmod_coef42; /* 0x1a95 */
uint32_t viu_osd1_matrix_offset0_1; /* 0x1a96 */
uint32_t viu_osd1_matrix_offset2; /* 0x1a97 */
uint32_t viu_osd1_matrix_pre_offset0_1; /* 0x1a98 */
uint32_t viu_osd1_matrix_pre_offset2; /* 0x1a99 */
uint32_t viu_osd1_matrix_coef22_30; /* 0x1a9d */
uint32_t viu_osd1_matrix_coef31_32; /* 0x1a9e */
uint32_t viu_osd1_matrix_coef40_41; /* 0x1a9f */
uint32_t viu_osd1_eotf_ctl; /* 0x1ad4 */
uint32_t viu_osd1_eotf_coef00_01; /* 0x1ad5 */
uint32_t viu_osd1_eotf_coef02_10; /* 0x1ad6 */
uint32_t viu_osd1_eotf_coef11_12; /* 0x1ad7 */
uint32_t viu_osd1_eotf_coef20_21; /* 0x1ad8 */
uint32_t viu_osd1_eotf_coef22_rs; /* 0x1ad9 */
uint32_t viu_osd1_oetf_ctl; /* 0x1adc */
struct hdr_osd_lut_s lut_val;
};
extern struct hdr_osd_reg_s hdr_osd_reg;
/***********************OSD HDR registers*******************************/
/* ******************************************************************* */
/* *** MACRO definitions ********** */
/* ******************************************************************* */
/* ******************************************************************* */
/* *** FUNCTION definitions ********** */
/* ******************************************************************* */
#endif /* _VE_H */