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clock: G12A media/gpu/fclk_div2p5 clk

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PD#156734: G12A media/gpu/fclk_div2p5 clk

Change-Id: I804fdfff57f841a9628bc4a35cbc2ba63fe076c6
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
This commit is contained in:
Qiufang Dai
2018-01-02 19:56:29 +08:00
committed by Yixun Lan
parent 8b5ae71fdf
commit 229df792fa
6 changed files with 742 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
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@@ -14280,3 +14280,8 @@ F: include/dt-bindings/clock/amlogic,g12a-clkc.h
F: drivers/amlogic/clk/g12a/*
F: drivers/amlogic/clk/clkc.h
AMLOGIC G12A clk tree for media/gpu
M: Qiufang Dai <qiufang.dai@amlogic.com>
F: drivers/amlogic/clk/g12a/g12a_clk_gpu.c
F: drivers/amlogic/clk/g12a/g12a_clk_media.c

2
drivers/amlogic/clk/clkc.h
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@@ -241,5 +241,7 @@ void meson_txlx_media_init(void);
void meson_init_gpu(void);
void meson_g12a_sdemmc_init(void);
void meson_g12a_media_init(void);
void meson_g12a_gpu_init(void);
#endif /* __CLKC_H */

4
drivers/amlogic/clk/g12a/Makefile
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@@ -2,8 +2,8 @@
# Makefile for Meson G12A clk
#
obj-$(CONFIG_AMLOGIC_GX_CLK) += g12a.o g12a_clk-pll.o g12a_clk_sdemmc.o g12a_clk-mpll.o
obj-$(CONFIG_AMLOGIC_GX_CLK) += g12a.o g12a_clk-pll.o g12a_clk_sdemmc.o g12a_clk-mpll.o \
g12a_clk_media.o g12a_clk_gpu.o
# g12a_ao.o\
g12a_clk-pll.o \
g12a_clk_sdemmc.o g12a_clk_media.o g12a_clk_misc.o

2
drivers/amlogic/clk/g12a/g12a.c
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@@ -912,6 +912,8 @@ static void __init g12a_clkc_init(struct device_node *np)
}
meson_g12a_sdemmc_init();
meson_g12a_gpu_init();
meson_g12a_media_init();
/*g12a_amlogic_init_misc();*/
pr_debug("%s: register all clk ok!", __func__);

184
drivers/amlogic/clk/g12a/g12a_clk_gpu.c Normal file
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@@ -0,0 +1,184 @@
/*
* drivers/amlogic/clk/g12a/g12a_clk_gpu.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <dt-bindings/clock/amlogic,g12a-clkc.h>
#include "../clkc.h"
#include "g12a.h"
const char *g12a_gpu_parent_names[] = { "xtal", "gp0_pll", "hifi_pll",
"fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7"};
static struct clk_mux gpu_p0_mux = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.mask = 0x7,
.shift = 9,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gpu_p0_mux",
.ops = &clk_mux_ops,
.parent_names = g12a_gpu_parent_names,
.num_parents = 8,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_divider gpu_p0_div = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.shift = 0,
.width = 7,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gpu_p0_div",
.ops = &clk_divider_ops,
.parent_names = (const char *[]){ "gpu_p0_mux" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_gate gpu_p0_gate = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.bit_idx = 8,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "gpu_p0_gate",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "gpu_p0_div" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_mux gpu_p1_mux = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.mask = 0x7,
.shift = 25,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gpu_p1_mux",
.ops = &clk_mux_ops,
.parent_names = g12a_gpu_parent_names,
.num_parents = 8,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_divider gpu_p1_div = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.shift = 16,
.width = 7,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gpu_p1_div",
.ops = &clk_divider_ops,
.parent_names = (const char *[]){ "gpu_p1_mux" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_gate gpu_p1_gate = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.bit_idx = 24,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "gpu_p1_gate",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "gpu_p1_div" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_mux gpu_mux = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.mask = 0x1,
.shift = 31,
.lock = &clk_lock,
.flags = CLK_PARENT_ALTERNATE,
.hw.init = &(struct clk_init_data){
.name = "gpu_mux",
.ops = &meson_clk_mux_ops,
.parent_names = (const char *[]){ "gpu_p0_composite",
"gpu_p1_composite"},
.num_parents = 2,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_hw *gpu_clk_hws[] = {
[CLKID_GPU_P0_MUX - CLKID_GPU_P0_MUX] = &gpu_p0_mux.hw,
[CLKID_GPU_P0_DIV - CLKID_GPU_P0_MUX] = &gpu_p0_div.hw,
[CLKID_GPU_P0_GATE - CLKID_GPU_P0_MUX] = &gpu_p0_gate.hw,
[CLKID_GPU_P1_MUX - CLKID_GPU_P0_MUX] = &gpu_p1_mux.hw,
[CLKID_GPU_P1_DIV - CLKID_GPU_P0_MUX] = &gpu_p1_div.hw,
[CLKID_GPU_P1_GATE - CLKID_GPU_P0_MUX] = &gpu_p1_gate.hw,
[CLKID_GPU_MUX - CLKID_GPU_P0_MUX] = &gpu_mux.hw,
};
void meson_g12a_gpu_init(void)
{
gpu_p0_mux.reg = clk_base + (u64)(gpu_p0_mux.reg);
gpu_p0_div.reg = clk_base + (u64)(gpu_p0_div.reg);
gpu_p0_gate.reg = clk_base + (u64)(gpu_p0_gate.reg);
gpu_p1_mux.reg = clk_base + (u64)(gpu_p1_mux.reg);
gpu_p1_div.reg = clk_base + (u64)(gpu_p1_div.reg);
gpu_p1_gate.reg = clk_base + (u64)(gpu_p1_gate.reg);
gpu_mux.reg = clk_base + (u64)(gpu_mux.reg);
clks[CLKID_GPU_P0_COMP] = clk_register_composite(NULL,
"gpu_p0_composite",
g12a_gpu_parent_names, 8,
gpu_clk_hws[CLKID_GPU_P0_MUX - CLKID_GPU_P0_MUX],
&clk_mux_ops,
gpu_clk_hws[CLKID_GPU_P0_DIV - CLKID_GPU_P0_MUX],
&clk_divider_ops,
gpu_clk_hws[CLKID_GPU_P0_GATE - CLKID_GPU_P0_MUX],
&clk_gate_ops, 0);
if (IS_ERR(clks[CLKID_GPU_P0_COMP]))
panic("%s: %d clk_register_composite gpu_p0_composite error\n",
__func__, __LINE__);
clks[CLKID_GPU_P1_COMP] = clk_register_composite(NULL,
"gpu_p1_composite",
g12a_gpu_parent_names, 8,
gpu_clk_hws[CLKID_GPU_P1_MUX - CLKID_GPU_P0_MUX],
&clk_mux_ops,
gpu_clk_hws[CLKID_GPU_P1_DIV - CLKID_GPU_P0_MUX],
&clk_divider_ops,
gpu_clk_hws[CLKID_GPU_P1_GATE - CLKID_GPU_P0_MUX],
&clk_gate_ops, 0);
if (IS_ERR(clks[CLKID_GPU_P1_COMP]))
panic("%s: %d clk_register_composite gpu_p1_composite error\n",
__func__, __LINE__);
clks[CLKID_GPU_MUX] = clk_register(NULL,
gpu_clk_hws[CLKID_GPU_MUX - CLKID_GPU_P0_MUX]);
if (IS_ERR(clks[CLKID_GPU_MUX]))
panic("%s: %d clk_register gpu_mux error\n",
__func__, __LINE__);
pr_info("%s: register meson gpu clk\n", __func__);
}

547
drivers/amlogic/clk/g12a/g12a_clk_media.c Normal file
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@@ -0,0 +1,547 @@
/*
* drivers/amlogic/clk/g12a/g12a_clk_media.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <dt-bindings/clock/amlogic,g12a-clkc.h>
#include "../clkc.h"
#include "g12a.h"
#if 0
/* cts_dsi_meas_clk */ /*MIPI_HOST*/
static const char * const meas_parent_names[] = { "xtal", "fclk_div4",
"fclk_div3", "fclk_div5", "null", "null", "fclk_dvi2", "fclk_div7"};
/* cts_dsi_meas_clk */
static struct clk_mux dsi_meas_mux = {
.reg = (void *)HHI_VDIN_MEAS_CLK_CNTL,
.mask = 0x7,
.shift = 21,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "dsi_meas_mux",
.ops = &clk_mux_ops,
.parent_names = meas_parent_names,
.num_parents = 8,
.flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED),
},
};
static struct clk_divider dsi_meas_div = {
.reg = (void *)HHI_VDIN_MEAS_CLK_CNTL,
.shift = 12,
.width = 7,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "dsi_meas_div",
.ops = &clk_divider_ops,
.parent_names = (const char *[]){ "dsi_meas_mux" },
.num_parents = 1,
.flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED),
},
};
static struct clk_gate dsi_meas_gate = {
.reg = (void *)HHI_VDIN_MEAS_CLK_CNTL,
.bit_idx = 20,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "dsi_meas_gate",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "dsi_meas_div" },
.num_parents = 1,
.flags = (CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED),
},
};
static struct clk_hw *dsi_meas_clk_hws[] = {
[CLKID_DSI_MEAS_MUX - CLKID_DSI_MEAS_MUX] = &dsi_meas_mux.hw,
[CLKID_DSI_MEAS_DIV - CLKID_DSI_MEAS_MUX] = &dsi_meas_div.hw,
[CLKID_DSI_MEAS_GATE - CLKID_DSI_MEAS_MUX] = &dsi_meas_gate.hw,
};
#endif
static const char * const vpu_parent_names[] = { "fclk_div3",
"fclk_div4", "fclk_div5", "fclk_div7", "null", "null",
"null", "null"};
/* cts_vpu_clk */
static struct clk_mux vpu_p0_mux = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.mask = 0x7,
.shift = 9,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_p0_mux",
.ops = &clk_mux_ops,
.parent_names = vpu_parent_names,
.num_parents = 8,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_divider vpu_p0_div = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.shift = 0,
.width = 7,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_p0_div",
.ops = &clk_divider_ops,
.parent_names = (const char *[]){ "vpu_p0_mux" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_gate vpu_p0_gate = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.bit_idx = 8,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vpu_p0_gate",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "vpu_p0_div" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_mux vpu_p1_mux = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.mask = 0x7,
.shift = 25,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_p1_mux",
.ops = &clk_mux_ops,
.parent_names = vpu_parent_names,
.num_parents = 8,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_divider vpu_p1_div = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.shift = 16,
.width = 7,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_p1_div",
.ops = &clk_divider_ops,
.parent_names = (const char *[]){ "vpu_p1_mux" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_gate vpu_p1_gate = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.bit_idx = 24,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vpu_p1_gate",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "vpu_p1_div" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_mux vpu_mux = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.mask = 0x1,
.shift = 31,
.lock = &clk_lock,
.flags = CLK_PARENT_ALTERNATE,
.hw.init = &(struct clk_init_data){
.name = "vpu_mux",
.ops = &meson_clk_mux_ops,
.parent_names = (const char *[]){ "vpu_p0_composite",
"vpu_p1_composite"},
.num_parents = 2,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_hw *vpu_clk_hws[] = {
[CLKID_VPU_P0_MUX - CLKID_VPU_P0_MUX] = &vpu_p0_mux.hw,
[CLKID_VPU_P0_DIV - CLKID_VPU_P0_MUX] = &vpu_p0_div.hw,
[CLKID_VPU_P0_GATE - CLKID_VPU_P0_MUX] = &vpu_p0_gate.hw,
[CLKID_VPU_P1_MUX - CLKID_VPU_P0_MUX] = &vpu_p1_mux.hw,
[CLKID_VPU_P1_DIV - CLKID_VPU_P0_MUX] = &vpu_p1_div.hw,
[CLKID_VPU_P1_GATE - CLKID_VPU_P0_MUX] = &vpu_p1_gate.hw,
[CLKID_VPU_MUX - CLKID_VPU_P0_MUX] = &vpu_mux.hw,
};
static const char * const vapb_parent_names[] = { "fclk_div4",
"fclk_div3", "fclk_div5", "fclk_div7", "mpll1", "null",
"mpll2", "fclk_div2p5"};
/* cts_vapbclk */
static struct clk_mux vapb_p0_mux = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.mask = 0x7,
.shift = 9,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vapb_p0_mux",
.ops = &clk_mux_ops,
.parent_names = vapb_parent_names,
.num_parents = 8,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_divider vapb_p0_div = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.shift = 0,
.width = 7,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vapb_p0_div",
.ops = &clk_divider_ops,
.parent_names = (const char *[]){ "vapb_p0_mux" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_gate vapb_p0_gate = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.bit_idx = 8,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vapb_p0_gate",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "vapb_p0_div" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_mux vapb_p1_mux = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.mask = 0x7,
.shift = 25,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vapb_p1_mux",
.ops = &clk_mux_ops,
.parent_names = vapb_parent_names,
.num_parents = 8,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_divider vapb_p1_div = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.shift = 16,
.width = 7,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vapb_p1_div",
.ops = &clk_divider_ops,
.parent_names = (const char *[]){ "vapb_p1_mux" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_gate vapb_p1_gate = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.bit_idx = 24,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vapb_p1_gate",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "vapb_p1_div" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_mux vapb_mux = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.mask = 0x1,
.shift = 31,
.lock = &clk_lock,
.flags = CLK_PARENT_ALTERNATE,
.hw.init = &(struct clk_init_data){
.name = "vapb_mux",
.ops = &meson_clk_mux_ops,
.parent_names = (const char *[]){ "vapb_p0_composite",
"vapb_p1_composite"},
.num_parents = 2,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_hw *vapb_clk_hws[] = {
[CLKID_VPU_P0_MUX - CLKID_VPU_P0_MUX] = &vapb_p0_mux.hw,
[CLKID_VPU_P0_DIV - CLKID_VPU_P0_MUX] = &vapb_p0_div.hw,
[CLKID_VPU_P0_GATE - CLKID_VPU_P0_MUX] = &vapb_p0_gate.hw,
[CLKID_VPU_P1_MUX - CLKID_VPU_P0_MUX] = &vapb_p1_mux.hw,
[CLKID_VPU_P1_DIV - CLKID_VPU_P0_MUX] = &vapb_p1_div.hw,
[CLKID_VPU_P1_GATE - CLKID_VPU_P0_MUX] = &vapb_p1_gate.hw,
[CLKID_VPU_MUX - CLKID_VPU_P0_MUX] = &vapb_mux.hw,
};
static struct clk_gate ge2d_gate = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.bit_idx = 30,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "ge2d_gate",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "vapb_mux" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static const char * const vpu_clkb_tmp_parent_names[] = { "vpu_mux",
"fclk_div4", "fclk_div5", "fclk_div7"};
static struct clk_mux vpu_clkb_tmp_mux = {
.reg = (void *)HHI_VPU_CLKB_CNTL,
.mask = 0x3,
.shift = 20,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_clkb_tmp_mux",
.ops = &clk_mux_ops,
.parent_names = vpu_clkb_tmp_parent_names,
.num_parents = 8,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_divider vpu_clkb_tmp_div = {
.reg = (void *)HHI_VPU_CLKB_CNTL,
.shift = 16,
.width = 4,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_clkb_tmp_div",
.ops = &clk_divider_ops,
.parent_names = (const char *[]){ "vpu_clkb_tmp_mux" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_gate vpu_clkb_tmp_gate = {
.reg = (void *)HHI_VPU_CLKB_CNTL,
.bit_idx = 24,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vpu_clkb_tmp_gate",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "vpu_clkb_tmp_div" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static const char * const vpu_clkb_parent_names[]
= { "vpu_clkb_tmp_composite" };
static struct clk_divider vpu_clkb_div = {
.reg = (void *)HHI_VPU_CLKB_CNTL,
.shift = 0,
.width = 8,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_clkb_div",
.ops = &clk_divider_ops,
.parent_names = (const char *[]){ "vpu_clkb_tmp_composite" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
static struct clk_gate vpu_clkb_gate = {
.reg = (void *)HHI_VPU_CLKB_CNTL,
.bit_idx = 8,
.lock = &clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vpu_clkb_tmp_gate",
.ops = &clk_gate_ops,
.parent_names = (const char *[]){ "vpu_clkb_div" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
},
};
void meson_g12a_media_init(void)
{
#if 0
/* cts_dsi_meas_clk */
dsi_meas_mux.reg = clk_base + (u64)(dsi_meas_mux.reg);
dsi_meas_div.reg = clk_base + (u64)(dsi_meas_div.reg);
dsi_meas_gate.reg = clk_base + (u64)(dsi_meas_gate.reg);
#endif
/* cts_vpu_clk */
vpu_p0_mux.reg = clk_base + (u64)(vpu_p0_mux.reg);
vpu_p0_div.reg = clk_base + (u64)(vpu_p0_div.reg);
vpu_p0_gate.reg = clk_base + (u64)(vpu_p0_gate.reg);
vpu_p1_mux.reg = clk_base + (u64)(vpu_p1_mux.reg);
vpu_p1_div.reg = clk_base + (u64)(vpu_p1_div.reg);
vpu_p1_gate.reg = clk_base + (u64)(vpu_p1_gate.reg);
vpu_mux.reg = clk_base + (u64)(vpu_mux.reg);
/* cts_vapbclk */
vapb_p0_mux.reg = clk_base + (u64)(vapb_p0_mux.reg);
vapb_p0_div.reg = clk_base + (u64)(vapb_p0_div.reg);
vapb_p0_gate.reg = clk_base + (u64)(vapb_p0_gate.reg);
vapb_p1_mux.reg = clk_base + (u64)(vapb_p1_mux.reg);
vapb_p1_div.reg = clk_base + (u64)(vapb_p1_div.reg);
vapb_p1_gate.reg = clk_base + (u64)(vapb_p1_gate.reg);
vapb_mux.reg = clk_base + (u64)(vapb_mux.reg);
/* cts_ge2d_clk */
ge2d_gate.reg = clk_base + (u64)(ge2d_gate.reg);
/* vpu_clkb_tmp */
vpu_clkb_tmp_mux.reg = clk_base + (u64)(vpu_clkb_tmp_mux.reg);
vpu_clkb_tmp_div.reg = clk_base + (u64)(vpu_clkb_tmp_div.reg);
vpu_clkb_tmp_gate.reg = clk_base + (u64)(vpu_clkb_tmp_gate.reg);
vpu_clkb_div.reg = clk_base + (u64)(vpu_clkb_div.reg);
vpu_clkb_gate.reg = clk_base + (u64)(vpu_clkb_gate.reg);
#if 0
clks[CLKID_DSI_MEAS_COMP] = clk_register_composite(NULL,
"dsi_meas_composite",
meas_parent_names, 6,
dsi_meas_clk_hws[CLKID_DSI_MEAS_MUX - CLKID_DSI_MEAS_MUX],
&clk_mux_ops,
dsi_meas_clk_hws[CLKID_DSI_MEAS_DIV - CLKID_DSI_MEAS_MUX],
&clk_divider_ops,
dsi_meas_clk_hws[CLKID_DSI_MEAS_GATE - CLKID_DSI_MEAS_MUX],
&clk_gate_ops, 0);
if (IS_ERR(clks[CLKID_DSI_MEAS_COMP]))
pr_err("%s: %d clk_register_composite dsi_meas_composite error\n",
__func__, __LINE__);
#endif
/* cts_vpu_clk */
clks[CLKID_VPU_P0_COMP] = clk_register_composite(NULL,
"vpu_p0_composite",
vpu_parent_names, 8,
vpu_clk_hws[CLKID_VPU_P0_MUX - CLKID_VPU_P0_MUX],
&clk_mux_ops,
vpu_clk_hws[CLKID_VPU_P0_DIV - CLKID_VPU_P0_MUX],
&clk_divider_ops,
vpu_clk_hws[CLKID_VPU_P0_GATE - CLKID_VPU_P0_MUX],
&clk_gate_ops, 0);
if (IS_ERR(clks[CLKID_VPU_P0_COMP]))
panic("%s: %d clk_register_composite vpu_p0_composite error\n",
__func__, __LINE__);
clks[CLKID_VPU_P1_COMP] = clk_register_composite(NULL,
"vpu_p1_composite",
vpu_parent_names, 8,
vpu_clk_hws[CLKID_VPU_P1_MUX - CLKID_VPU_P0_MUX],
&clk_mux_ops,
vpu_clk_hws[CLKID_VPU_P1_DIV - CLKID_VPU_P0_MUX],
&clk_divider_ops,
vpu_clk_hws[CLKID_VPU_P1_GATE - CLKID_VPU_P0_MUX],
&clk_gate_ops, 0);
if (IS_ERR(clks[CLKID_VPU_P1_COMP]))
panic("%s: %d clk_register_composite vpu_p1_composite error\n",
__func__, __LINE__);
clks[CLKID_VPU_MUX] = clk_register(NULL,
vpu_clk_hws[CLKID_VPU_MUX - CLKID_VPU_P0_MUX]);
if (IS_ERR(clks[CLKID_VPU_MUX]))
panic("%s: %d clk_register vpu_mux error\n",
__func__, __LINE__);
/* cts_vapb_clk */
clks[CLKID_VAPB_P0_COMP] = clk_register_composite(NULL,
"vapb_p0_composite",
vpu_parent_names, 8,
vapb_clk_hws[CLKID_VAPB_P0_MUX - CLKID_VAPB_P0_MUX],
&clk_mux_ops,
vapb_clk_hws[CLKID_VAPB_P0_DIV - CLKID_VAPB_P0_MUX],
&clk_divider_ops,
vapb_clk_hws[CLKID_VAPB_P0_GATE - CLKID_VAPB_P0_MUX],
&clk_gate_ops, 0);
if (IS_ERR(clks[CLKID_VAPB_P0_COMP]))
panic("%s: %d clk_register_composite vapb_p0_composite error\n",
__func__, __LINE__);
clks[CLKID_VAPB_P1_COMP] = clk_register_composite(NULL,
"vapb_p1_composite",
vpu_parent_names, 8,
vapb_clk_hws[CLKID_VAPB_P1_MUX - CLKID_VAPB_P0_MUX],
&clk_mux_ops,
vapb_clk_hws[CLKID_VAPB_P1_DIV - CLKID_VAPB_P0_MUX],
&clk_divider_ops,
vapb_clk_hws[CLKID_VAPB_P1_GATE - CLKID_VAPB_P0_MUX],
&clk_gate_ops, 0);
if (IS_ERR(clks[CLKID_VAPB_P1_COMP]))
panic("%s: %d clk_register_composite vapb_p1_composite error\n",
__func__, __LINE__);
clks[CLKID_VAPB_MUX] = clk_register(NULL,
vapb_clk_hws[CLKID_VAPB_MUX - CLKID_VAPB_P0_MUX]);
if (IS_ERR(clks[CLKID_VAPB_MUX]))
panic("%s: %d clk_register vapb_mux error\n",
__func__, __LINE__);
clks[CLKID_GE2D_GATE] = clk_register(NULL,
&ge2d_gate.hw);
if (IS_ERR(clks[CLKID_GE2D_GATE]))
panic("%s: %d clk_register ge2d_gate error\n",
__func__, __LINE__);
clks[CLKID_VPU_CLKB_TMP_COMP] = clk_register_composite(NULL,
"vpu_clkb_tmp_composite",
vpu_clkb_tmp_parent_names, 4,
&vpu_clkb_tmp_mux.hw,
&clk_mux_ops,
&vpu_clkb_tmp_div.hw,
&clk_divider_ops,
&vpu_clkb_tmp_gate.hw,
&clk_gate_ops, 0);
if (IS_ERR(clks[CLKID_VPU_CLKB_TMP_COMP]))
panic("%s: %d clk_register_composite vpu_clkb_tmp_composite error\n",
__func__, __LINE__);
clks[CLKID_VPU_CLKB_COMP] = clk_register_composite(NULL,
"vpu_clkb_composite",
vpu_clkb_parent_names, 1,
NULL,
NULL,
&vpu_clkb_div.hw,
&clk_divider_ops,
&vpu_clkb_gate.hw,
&clk_gate_ops, 0);
if (IS_ERR(clks[CLKID_VPU_CLKB_COMP]))
panic("%s: %d clk_register_composite vpu_clkb_composite error\n",
__func__, __LINE__);
pr_info("%s: register meson media clk\n", __func__);
}