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rtw89: pci: add deglitch setting

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Add setting to support 8852ce.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220325060055.58482-7-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
2022-03-25 14:00:45 +08:00
committed by Kalle Valo
parent bab9e23917
commit 22a66e7c3a
2 changed files with 19 additions and 11 deletions
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27
drivers/net/wireless/realtek/rtw89/pci.c
View File

@@ -1809,19 +1809,24 @@ end:
static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev)
{
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
int ret;
if (rtwdev->chip->chip_id != RTL8852A)
return 0;
ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH,
PCIE_PHY_GEN1);
if (ret)
return ret;
ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH,
PCIE_PHY_GEN2);
if (ret)
return ret;
if (chip_id == RTL8852A) {
ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH,
PCIE_PHY_GEN1);
if (ret)
return ret;
ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH,
PCIE_PHY_GEN2);
if (ret)
return ret;
} else if (chip_id == RTL8852C) {
rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA24 * 2,
B_AX_DEGLITCH);
rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA24 * 2,
B_AX_DEGLITCH);
}
return 0;
}

3
drivers/net/wireless/realtek/rtw89/pci.h
View File

@@ -80,6 +80,9 @@
#define R_AX_PCIE_WDT_TIMER_S1 0x3128
#define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
#define R_RAC_DIRECT_OFFSET_G1 0x3800
#define R_RAC_DIRECT_OFFSET_G2 0x3880
#define RTW89_PCI_WR_RETRY_CNT 20
/* Interrupts */