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ODROID-M2:arm64/dts: change clock source(gpll -> v0pll) for rockchip vop
Signed-off-by: ckkim <changkon12@gmail.com> Change-Id: I146fbdf94e1fadeed62cf9e34fb1007449ad4bab
This commit is contained in:
@@ -653,6 +653,27 @@
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};
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&pinctrl {
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hdmi {
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hdmim0_tx0_scl: hdmim0-tx0-scl {
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rockchip,pins =
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/* hdmim0_tx0_scl */
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<4 RK_PB7 5 &pcfg_pull_none_drv_level_5_smt>;
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};
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/omit-if-no-ref/
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hdmim0_tx0_sda: hdmim0-tx0-sda {
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rockchip,pins =
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/* hdmim0_tx0_sda */
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<4 RK_PC0 5 &pcfg_pull_none_drv_level_5_smt>;
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};
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hdmim0_tx1_hpd: hdmim0-tx1-hpd {
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rockchip,pins =
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/* hdmim0_tx1_hpd */
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<1 RK_PA6 5 &pcfg_pull_none_drv_level_5_smt>;
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};
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};
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headphone {
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hp_det: hp-det {
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rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
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@@ -1032,6 +1053,8 @@
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&vop {
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status = "okay";
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assigned-clocks = <&cru PLL_V0PLL>;
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assigned-clock-rates = <1152000000>;
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};
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&vop_mmu {
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@@ -1039,16 +1062,22 @@
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};
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&vp0 {
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assigned-clocks = <&cru DCLK_VOP0>;
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assigned-clock-parents = <&hdptxphy_hdmi_clk0>;
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rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>;
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rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
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};
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&vp1 {
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assigned-clocks = <&cru DCLK_VOP1_SRC>;
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assigned-clock-parents = <&cru PLL_V0PLL>;
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rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
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rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
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};
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&vp2 {
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assigned-clocks = <&cru DCLK_VOP2_SRC>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>;
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rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
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};
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