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iommu/rockchip: support av1d iommu
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com> Change-Id: Ic7cbb95b83cef361ea4d62c969d5585318ec0dac
This commit is contained in:
Yandong Lin
@@ -19,7 +19,9 @@ obj-$(CONFIG_MTK_IOMMU) += mtk_iommu.o
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obj-$(CONFIG_MTK_IOMMU_V1) += mtk_iommu_v1.o
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obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
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obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
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obj-$(CONFIG_ROCKCHIP_IOMMU) += rockchip-iommu.o
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obj-$(CONFIG_ROCKCHIP_IOMMU) += rockchip_iommu.o
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rockchip_iommu-objs := rockchip-iommu.o
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rockchip_iommu-$(CONFIG_ROCKCHIP_MPP_AV1DEC) += rockchip-iommu-av1d.o
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obj-$(CONFIG_SUN50I_IOMMU) += sun50i-iommu.o
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obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
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obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o
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795
drivers/iommu/rockchip-iommu-av1d.c
Normal file
795
drivers/iommu/rockchip-iommu-av1d.c
Normal file
@@ -0,0 +1,795 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Compatible with the IOMMU of av1 decode
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*
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* Module Authors: Yandong Lin <yandong.lin@rock-chips.com>
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* Simon Xue <xxm@rock-chips.com>
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*/
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#include <linux/clk.h>
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#include <linux/compiler.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-map-ops.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/list.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_iommu.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <soc/rockchip/rockchip_iommu.h>
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struct av1d_iommu {
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struct device *dev;
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void __iomem **bases;
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int num_mmu;
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int num_irq;
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struct clk_bulk_data *clocks;
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int num_clocks;
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struct iommu_device iommu;
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struct iommu_domain *domain; /* domain to which iommu is attached */
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struct iommu_group *group;
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u32 *dt; /* page directory table */
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dma_addr_t dt_dma;
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spinlock_t iommus_lock; /* lock for iommus list */
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spinlock_t dt_lock; /* lock for modifying page directory table */
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/* for av1 iommu */
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u64 *pta; /* page directory table */
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dma_addr_t pta_dma;
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};
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#define RK_IOMMU_AV1 0xa
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#define NUM_DT_ENTRIES 1024
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#define NUM_PT_ENTRIES 1024
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#define SPAGE_ORDER 12
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#define SPAGE_SIZE (1 << SPAGE_ORDER)
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/* av1 iommu regs address */
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#define AV1_CLOCK_CTRL_BASE 0x0
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#define AV1_IDLE_ST_BASE 0x4
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#define AV1_MMU_CONFIG0_BASE 0x184
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#define AV1_MMU_CONFIG1_BASE 0x1ac
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#define AV1_MMU_AHB_EXCEPTION_BASE 0x380
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#define AV1_MMU_AHB_STATUS_BASE 0x384
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#define AV1_MMU_AHB_CONTROL_BASE 0x388
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#define AV1_MMU_AHB_TBL_ARRAY_BASE_L_BASE 0x38C
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#define AV1_MMU_AHB_TBL_ARRAY_BASE_H_BASE 0x390
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#define AV1_MMU_AHB_CTX_PD_BASE 0x3b4
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#define AV1_MMU_BUTT_BASE 0xffff
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/* MMU register offsets */
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#define AV1_MMU_FLUSH_BASE 0x184
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#define AV1_MMU_BIT_FLUSH BIT(4)
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#define AV1_MMU_PAGE_FAULT_ADDR 0x380
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#define AV1_MMU_STATUS_BASE 0x384 /* IRQ status */
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#define AV1_MMU_EN_BASE 0x388
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#define AV1_MMU_BIT_ENABLE BIT(0)
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#define AV1_MMU_OUT_OF_BOUND BIT(28)
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/* Irq mask */
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#define AV1_MMU_IRQ_MASK 0x7
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#define AV1_DTE_PT_ADDRESS_MASK 0xffffffc0
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#define AV1_DTE_PT_VALID BIT(0)
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#define AV1_PAGE_DESC_LO_MASK 0xfffff000
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#define AV1_PAGE_DESC_HI_MASK GENMASK_ULL(39, 32)
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#define AV1_PAGE_DESC_HI_SHIFT (32-4)
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#define AV1_IOMMU_PGSIZE_BITMAP 0x007ff000
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static inline phys_addr_t av1_dte_pt_address(u32 dte)
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{
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return (phys_addr_t)dte & AV1_DTE_PT_ADDRESS_MASK;
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}
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static inline u32 av1_mk_dte(dma_addr_t pt_dma)
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{
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return (pt_dma) | AV1_DTE_PT_VALID;
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}
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#define AV1_PTE_PAGE_ADDRESS_MASK 0xfffffff0
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#define AV1_PTE_PAGE_WRITABLE BIT(2)
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#define AV1_PTE_PAGE_VALID BIT(0)
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static struct device *dma_dev;
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static inline phys_addr_t av1_pte_page_address(u32 pte)
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{
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u64 pte_av1 = pte;
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pte_av1 = ((pte_av1 & AV1_PAGE_DESC_HI_MASK) << AV1_PAGE_DESC_HI_SHIFT) |
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(pte_av1 & AV1_PAGE_DESC_LO_MASK);
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return (phys_addr_t)pte_av1;
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}
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static u32 av1_mk_pte(phys_addr_t page, int prot)
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{
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u32 flags = 0;
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flags |= (prot & IOMMU_WRITE) ? AV1_PTE_PAGE_WRITABLE : 0;
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page = (page & AV1_PAGE_DESC_LO_MASK) |
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((page & AV1_PAGE_DESC_HI_MASK) >> AV1_PAGE_DESC_HI_SHIFT);
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page &= AV1_PTE_PAGE_ADDRESS_MASK;
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return page | flags | AV1_PTE_PAGE_VALID;
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}
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#define AV1_DTE_PT_VALID BIT(0)
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static inline bool av1_dte_is_pt_valid(u32 dte)
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{
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return dte & AV1_DTE_PT_VALID;
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}
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static inline bool av1_pte_is_page_valid(u32 pte)
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{
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return pte & AV1_PTE_PAGE_VALID;
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}
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static u32 av1_mk_pte_invalid(u32 pte)
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{
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return pte & ~AV1_PTE_PAGE_VALID;
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}
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#define AV1_MASTER_TLB_MASK GENMASK_ULL(31, 10)
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/* mode 0 : 4k */
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#define AV1_PTA_4K_MODE 0
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static u64 av1_mk_pta(dma_addr_t dt_dma)
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{
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u64 val = (dt_dma & AV1_MASTER_TLB_MASK) | AV1_PTA_4K_MODE;
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return val;
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}
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static void av1d_iommu_disable(struct av1d_iommu *iommu)
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{
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int i;
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/* Ignore error while disabling, just keep going */
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WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks));
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for (i = 0; i < iommu->num_mmu; i++)
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writel(0, iommu->bases[i] + AV1_MMU_AHB_CONTROL_BASE);
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clk_bulk_disable(iommu->num_clocks, iommu->clocks);
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}
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static int av1_iommu_disable(struct device *dev)
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{
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struct av1d_iommu *av1d_iommu = (struct av1d_iommu *)dev_get_platdata(dev);
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if (!av1d_iommu->domain)
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return 0;
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av1d_iommu_disable(av1d_iommu);
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return 0;
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}
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static int av1d_iommu_enable(struct av1d_iommu *av1d_iommu)
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{
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int ret, i;
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ret = clk_bulk_enable(av1d_iommu->num_clocks, av1d_iommu->clocks);
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if (ret)
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return ret;
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for (i = 0; i < av1d_iommu->num_mmu; i++) {
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u32 val = readl(av1d_iommu->bases[i] + AV1_MMU_AHB_CONTROL_BASE);
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if (!(val & AV1_MMU_BIT_ENABLE)) {
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writel(av1d_iommu->pta_dma,
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av1d_iommu->bases[i] + AV1_MMU_AHB_TBL_ARRAY_BASE_L_BASE);
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writel(AV1_MMU_OUT_OF_BOUND, av1d_iommu->bases[i] + AV1_MMU_CONFIG1_BASE);
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writel(AV1_MMU_BIT_ENABLE,
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av1d_iommu->bases[i] + AV1_MMU_AHB_EXCEPTION_BASE);
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writel(AV1_MMU_BIT_ENABLE, av1d_iommu->bases[i] + AV1_MMU_AHB_CONTROL_BASE);
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}
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}
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clk_bulk_disable(av1d_iommu->num_clocks, av1d_iommu->clocks);
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return ret;
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}
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static int av1_iommu_enable(struct device *dev)
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{
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struct av1d_iommu *av1d_iommu = (struct av1d_iommu *)dev_get_platdata(dev);
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if (!av1d_iommu->domain)
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return 0;
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return av1d_iommu_enable(av1d_iommu);
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}
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static inline void av1_table_flush(dma_addr_t dma, unsigned int count)
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{
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size_t size = count * sizeof(u32); /* count of u32 entry */
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dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE);
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}
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#define AV1_IOVA_DTE_MASK 0xffc00000
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#define AV1_IOVA_DTE_SHIFT 22
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#define AV1_IOVA_PTE_MASK 0x003ff000
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#define AV1_IOVA_PTE_SHIFT 12
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#define AV1_IOVA_PAGE_MASK 0x00000fff
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#define AV1_IOVA_PAGE_SHIFT 0
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static u32 av1_iova_dte_index(dma_addr_t iova)
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{
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return (u32)(iova & AV1_IOVA_DTE_MASK) >> AV1_IOVA_DTE_SHIFT;
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}
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static u32 av1_iova_pte_index(dma_addr_t iova)
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{
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return (u32)(iova & AV1_IOVA_PTE_MASK) >> AV1_IOVA_PTE_SHIFT;
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}
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static u32 av1_iova_page_offset(dma_addr_t iova)
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{
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return (u32)(iova & AV1_IOVA_PAGE_MASK) >> AV1_IOVA_PAGE_SHIFT;
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}
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static u32 av1_iommu_read(void __iomem *base, u32 offset)
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{
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return readl(base + offset);
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}
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static void av1_iommu_write(void __iomem *base, u32 offset, u32 value)
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{
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writel(value, base + offset);
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}
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static void av1_iommu_flush_tlb_all(struct iommu_domain *domain, struct device *dev)
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{
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struct av1d_iommu *av1d_iommu = (struct av1d_iommu *)dev_get_platdata(dev);
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unsigned long flags;
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int i, ret;
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if (WARN_ON(!av1d_iommu))
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return;
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spin_lock_irqsave(&av1d_iommu->iommus_lock, flags);
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ret = pm_runtime_get_if_in_use(av1d_iommu->dev);
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if (WARN_ON_ONCE(ret < 0)) {
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spin_unlock_irqrestore(&av1d_iommu->iommus_lock, flags);
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return;
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}
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if (ret) {
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WARN_ON(clk_bulk_enable(av1d_iommu->num_clocks, av1d_iommu->clocks));
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for (i = 0; i < av1d_iommu->num_mmu; i++) {
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writel(AV1_MMU_BIT_FLUSH,
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av1d_iommu->bases[i] + AV1_MMU_FLUSH_BASE);
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writel(0, av1d_iommu->bases[i] + AV1_MMU_FLUSH_BASE);
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}
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clk_bulk_disable(av1d_iommu->num_clocks, av1d_iommu->clocks);
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pm_runtime_put(av1d_iommu->dev);
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}
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spin_unlock_irqrestore(&av1d_iommu->iommus_lock, flags);
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}
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static irqreturn_t av1_iommu_irq(int irq, void *dev_id)
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{
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struct av1d_iommu *av1d_iommu = dev_id;
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u32 int_status;
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dma_addr_t iova;
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irqreturn_t ret = IRQ_NONE;
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int i, err;
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err = pm_runtime_get_if_in_use(av1d_iommu->dev);
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if (!err || WARN_ON_ONCE(err < 0))
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return ret;
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if (WARN_ON(clk_bulk_enable(av1d_iommu->num_clocks, av1d_iommu->clocks)))
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goto out;
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for (i = 0; i < av1d_iommu->num_mmu; i++) {
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int_status = av1_iommu_read(av1d_iommu->bases[i], AV1_MMU_STATUS_BASE);
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if (int_status & AV1_MMU_IRQ_MASK) {
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dev_err(av1d_iommu->dev, "unexpected int_status=%08x\n", int_status);
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iova = av1_iommu_read(av1d_iommu->bases[i], AV1_MMU_PAGE_FAULT_ADDR);
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if (av1d_iommu->domain)
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report_iommu_fault(av1d_iommu->domain, av1d_iommu->dev,
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iova, int_status);
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else
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dev_err(av1d_iommu->dev,
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"Page fault while av1d_iommu not attached to domain?\n");
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}
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av1_iommu_write(av1d_iommu->bases[i], AV1_MMU_STATUS_BASE, 0);
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ret = IRQ_HANDLED;
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}
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clk_bulk_disable(av1d_iommu->num_clocks, av1d_iommu->clocks);
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out:
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pm_runtime_put(av1d_iommu->dev);
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return ret;
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}
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static int av1d_iommu_init(struct av1d_iommu *av1d_iommu)
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{
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if (!dma_dev)
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return -ENAVAIL;
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/*
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* av132xx iommus use a 2 level pagetable.
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* Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
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* Allocate one 4 KiB page for each table.
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*/
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av1d_iommu->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
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if (!av1d_iommu->dt)
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return -1;
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av1d_iommu->dt_dma = dma_map_single(dma_dev, av1d_iommu->dt,
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SPAGE_SIZE, DMA_TO_DEVICE);
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if (dma_mapping_error(dma_dev, av1d_iommu->dt_dma)) {
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dev_err(dma_dev, "DMA map error for DT\n");
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goto err_free_dt;
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}
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av1d_iommu->pta = (u64 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
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if (!av1d_iommu->pta)
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goto err_unmap_dt;
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av1d_iommu->pta_dma = dma_map_single(dma_dev, av1d_iommu->pta,
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SPAGE_SIZE, DMA_TO_DEVICE);
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if (dma_mapping_error(dma_dev, av1d_iommu->pta_dma)) {
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dev_err(dma_dev, "DMA map error for PTA\n");
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goto err_free_pta;
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}
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av1d_iommu->pta[0] = av1_mk_pta(av1d_iommu->dt_dma);
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av1_table_flush(av1d_iommu->pta_dma, 1024);
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av1_table_flush(av1d_iommu->dt_dma, NUM_DT_ENTRIES);
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spin_lock_init(&av1d_iommu->iommus_lock);
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spin_lock_init(&av1d_iommu->dt_lock);
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return 0;
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err_free_pta:
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free_page((unsigned long)av1d_iommu->pta);
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err_unmap_dt:
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dma_unmap_single(dma_dev, av1d_iommu->dt_dma,
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SPAGE_SIZE, DMA_TO_DEVICE);
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err_free_dt:
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free_page((unsigned long)av1d_iommu->dt);
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return -1;
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}
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static phys_addr_t av1_iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova,
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struct device *dev)
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{
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struct av1d_iommu *av1d_iommu = (struct av1d_iommu *)dev_get_platdata(dev);
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unsigned long flags;
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phys_addr_t pt_phys, phys = 0;
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u32 dte, pte;
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u32 *page_table;
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spin_lock_irqsave(&av1d_iommu->dt_lock, flags);
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dte = av1d_iommu->dt[av1_iova_dte_index(iova)];
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if (!av1_dte_is_pt_valid(dte))
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goto out;
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pt_phys = av1_dte_pt_address(dte);
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page_table = (u32 *)phys_to_virt(pt_phys);
|
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pte = page_table[av1_iova_pte_index(iova)];
|
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if (!av1_pte_is_page_valid(pte))
|
||||
goto out;
|
||||
|
||||
phys = av1_pte_page_address(pte) + av1_iova_page_offset(iova);
|
||||
out:
|
||||
spin_unlock_irqrestore(&av1d_iommu->dt_lock, flags);
|
||||
|
||||
return phys;
|
||||
}
|
||||
|
||||
static u32 *av1_dte_get_page_table(struct av1d_iommu *av1d_iommu, dma_addr_t iova)
|
||||
{
|
||||
u32 *page_table, *dte_addr;
|
||||
u32 dte_index, dte;
|
||||
phys_addr_t pt_phys;
|
||||
dma_addr_t pt_dma;
|
||||
|
||||
assert_spin_locked(&av1d_iommu->dt_lock);
|
||||
|
||||
dte_index = av1_iova_dte_index(iova);
|
||||
dte_addr = &av1d_iommu->dt[dte_index];
|
||||
dte = *dte_addr;
|
||||
if (av1_dte_is_pt_valid(dte))
|
||||
goto done;
|
||||
|
||||
page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32);
|
||||
if (!page_table)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(dma_dev, pt_dma)) {
|
||||
dev_err(dma_dev, "DMA mapping error while allocating page table\n");
|
||||
free_page((unsigned long)page_table);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
dte = av1_mk_dte(pt_dma);
|
||||
*dte_addr = dte;
|
||||
|
||||
av1_table_flush(pt_dma, NUM_PT_ENTRIES);
|
||||
av1_table_flush(av1d_iommu->dt_dma + dte_index * sizeof(u32), 1);
|
||||
done:
|
||||
pt_phys = av1_dte_pt_address(dte);
|
||||
|
||||
return (u32 *)phys_to_virt(pt_phys);
|
||||
}
|
||||
|
||||
static size_t av1_iommu_unmap_iova(struct av1d_iommu *av1d_iommu,
|
||||
u32 *pte_addr, dma_addr_t pte_dma,
|
||||
size_t size)
|
||||
{
|
||||
unsigned int pte_count;
|
||||
unsigned int pte_total = size / SPAGE_SIZE;
|
||||
|
||||
assert_spin_locked(&av1d_iommu->dt_lock);
|
||||
|
||||
for (pte_count = 0; pte_count < pte_total; pte_count++) {
|
||||
u32 pte = pte_addr[pte_count];
|
||||
|
||||
if (!av1_pte_is_page_valid(pte))
|
||||
break;
|
||||
|
||||
pte_addr[pte_count] = av1_mk_pte_invalid(pte);
|
||||
}
|
||||
|
||||
av1_table_flush(pte_dma, pte_count);
|
||||
|
||||
return pte_count * SPAGE_SIZE;
|
||||
}
|
||||
|
||||
static int av1_iommu_map_iova(struct av1d_iommu *av1_iommu, u32 *pte_addr,
|
||||
dma_addr_t pte_dma, dma_addr_t iova,
|
||||
phys_addr_t paddr, size_t size, int prot)
|
||||
{
|
||||
unsigned int pte_count;
|
||||
unsigned int pte_total = size / SPAGE_SIZE;
|
||||
phys_addr_t page_phys;
|
||||
|
||||
assert_spin_locked(&av1_iommu->dt_lock);
|
||||
|
||||
for (pte_count = 0; pte_count < pte_total; pte_count++) {
|
||||
u32 pte = pte_addr[pte_count];
|
||||
|
||||
if (av1_pte_is_page_valid(pte))
|
||||
goto unwind;
|
||||
|
||||
pte_addr[pte_count] = av1_mk_pte(paddr, prot);
|
||||
|
||||
paddr += SPAGE_SIZE;
|
||||
}
|
||||
|
||||
av1_table_flush(pte_dma, pte_total);
|
||||
|
||||
return 0;
|
||||
unwind:
|
||||
/* Unmap the range of iovas that we just mapped */
|
||||
av1_iommu_unmap_iova(av1_iommu, pte_addr, pte_dma,
|
||||
pte_count * SPAGE_SIZE);
|
||||
|
||||
iova += pte_count * SPAGE_SIZE;
|
||||
page_phys = av1_pte_page_address(pte_addr[pte_count]);
|
||||
pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
|
||||
&iova, &page_phys, &paddr, prot);
|
||||
|
||||
return -EADDRINUSE;
|
||||
}
|
||||
|
||||
static size_t av1_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
|
||||
size_t size, struct iommu_iotlb_gather *gather, struct device *dev)
|
||||
{
|
||||
struct av1d_iommu *av1d_iommu = (struct av1d_iommu *)dev_get_platdata(dev);
|
||||
unsigned long flags;
|
||||
dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
|
||||
phys_addr_t pt_phys;
|
||||
u32 dte;
|
||||
u32 *pte_addr;
|
||||
size_t unmap_size;
|
||||
|
||||
spin_lock_irqsave(&av1d_iommu->dt_lock, flags);
|
||||
|
||||
dte = av1d_iommu->dt[av1_iova_dte_index(iova)];
|
||||
/* Just return 0 if iova is unmapped */
|
||||
if (!av1_dte_is_pt_valid(dte)) {
|
||||
spin_unlock_irqrestore(&av1d_iommu->dt_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
pt_phys = av1_dte_pt_address(dte);
|
||||
pte_addr = (u32 *)phys_to_virt(pt_phys) + av1_iova_pte_index(iova);
|
||||
pte_dma = pt_phys + av1_iova_pte_index(iova) * sizeof(u32);
|
||||
unmap_size = av1_iommu_unmap_iova(av1d_iommu, pte_addr, pte_dma, size);
|
||||
|
||||
spin_unlock_irqrestore(&av1d_iommu->dt_lock, flags);
|
||||
|
||||
return unmap_size;
|
||||
}
|
||||
|
||||
static int av1_iommu_map(struct iommu_domain *domain, unsigned long _iova, phys_addr_t paddr,
|
||||
size_t size, int prot, gfp_t gfp, struct device *dev)
|
||||
{
|
||||
struct av1d_iommu *av1d_iommu = (struct av1d_iommu *)dev_get_platdata(dev);
|
||||
unsigned long flags;
|
||||
dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
|
||||
u32 *page_table, *pte_addr;
|
||||
u32 dte, pte_index;
|
||||
int ret;
|
||||
|
||||
if (WARN_ON(!av1d_iommu))
|
||||
return -1;
|
||||
|
||||
spin_lock_irqsave(&av1d_iommu->dt_lock, flags);
|
||||
|
||||
page_table = av1_dte_get_page_table(av1d_iommu, iova);
|
||||
if (IS_ERR(page_table)) {
|
||||
spin_unlock_irqrestore(&av1d_iommu->dt_lock, flags);
|
||||
return PTR_ERR(page_table);
|
||||
}
|
||||
|
||||
dte = av1d_iommu->dt[av1_iova_dte_index(iova)];
|
||||
pte_index = av1_iova_pte_index(iova);
|
||||
pte_addr = &page_table[pte_index];
|
||||
pte_dma = av1_dte_pt_address(dte) + pte_index * sizeof(u32);
|
||||
ret = av1_iommu_map_iova(av1d_iommu, pte_addr, pte_dma, iova,
|
||||
paddr, size, prot);
|
||||
|
||||
spin_unlock_irqrestore(&av1d_iommu->dt_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void av1_iommu_detach_device(struct iommu_domain *domain, struct device *dev)
|
||||
{
|
||||
struct av1d_iommu *iommu = (struct av1d_iommu *)dev_get_platdata(dev);
|
||||
int ret;
|
||||
|
||||
if (WARN_ON(!iommu))
|
||||
return;
|
||||
|
||||
dev_dbg(dev, "Detaching from iommu domain\n");
|
||||
|
||||
if (!iommu->domain)
|
||||
return;
|
||||
|
||||
ret = pm_runtime_get_if_in_use(iommu->dev);
|
||||
WARN_ON_ONCE(ret < 0);
|
||||
if (ret > 0) {
|
||||
av1d_iommu_disable(iommu);
|
||||
pm_runtime_put(iommu->dev);
|
||||
}
|
||||
iommu->domain = NULL;
|
||||
}
|
||||
|
||||
static int av1_iommu_attach_device(struct iommu_domain *domain, struct device *dev)
|
||||
{
|
||||
struct av1d_iommu *iommu = (struct av1d_iommu *)dev_get_platdata(dev);
|
||||
int ret;
|
||||
|
||||
if (WARN_ON(!iommu))
|
||||
return -ENODEV;
|
||||
|
||||
if (iommu->domain)
|
||||
av1_iommu_detach_device(iommu->domain, dev);
|
||||
|
||||
iommu->domain = domain;
|
||||
|
||||
/* Attach NULL for disable iommu */
|
||||
if (!domain)
|
||||
return 0;
|
||||
|
||||
ret = pm_runtime_get_if_in_use(iommu->dev);
|
||||
if (!ret || WARN_ON_ONCE(ret < 0))
|
||||
return 0;
|
||||
|
||||
ret = av1d_iommu_enable(iommu);
|
||||
if (ret)
|
||||
av1_iommu_detach_device(iommu->domain, dev);
|
||||
|
||||
pm_runtime_put(iommu->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void av1_iommu_domain_free(struct iommu_domain *domain, struct device *dev)
|
||||
{
|
||||
struct av1d_iommu *av1d_iommu = (struct av1d_iommu *)dev_get_platdata(dev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < NUM_DT_ENTRIES; i++) {
|
||||
u32 dte = av1d_iommu->dt[i];
|
||||
|
||||
if (av1_dte_is_pt_valid(dte)) {
|
||||
phys_addr_t pt_phys = av1_dte_pt_address(dte);
|
||||
u32 *page_table = phys_to_virt(pt_phys);
|
||||
|
||||
dma_unmap_single(dma_dev, pt_phys,
|
||||
SPAGE_SIZE, DMA_TO_DEVICE);
|
||||
free_page((unsigned long)page_table);
|
||||
}
|
||||
}
|
||||
|
||||
dma_unmap_single(dma_dev, av1d_iommu->dt_dma,
|
||||
SPAGE_SIZE, DMA_TO_DEVICE);
|
||||
free_page((unsigned long)av1d_iommu->dt);
|
||||
|
||||
dma_unmap_single(dma_dev, av1d_iommu->pta_dma,
|
||||
SPAGE_SIZE, DMA_TO_DEVICE);
|
||||
free_page((unsigned long)av1d_iommu->pta);
|
||||
|
||||
kfree(av1d_iommu);
|
||||
}
|
||||
|
||||
static int av1_iommu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct av1d_iommu *iommu;
|
||||
struct resource *res;
|
||||
int num_res = pdev->num_resources;
|
||||
int err, i;
|
||||
|
||||
iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
|
||||
if (!iommu)
|
||||
return -ENOMEM;
|
||||
|
||||
iommu->dev = dev;
|
||||
iommu->num_mmu = 0;
|
||||
|
||||
iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases),
|
||||
GFP_KERNEL);
|
||||
if (!iommu->bases)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < num_res; i++) {
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
|
||||
if (!res)
|
||||
continue;
|
||||
iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(iommu->bases[i]))
|
||||
continue;
|
||||
iommu->num_mmu++;
|
||||
}
|
||||
if (iommu->num_mmu == 0) {
|
||||
dev_err(dev, "get iommu base failed\n");
|
||||
return PTR_ERR(iommu->bases[0]);
|
||||
}
|
||||
|
||||
iommu->num_irq = platform_irq_count(pdev);
|
||||
if (iommu->num_irq < 0) {
|
||||
dev_err(dev, "get av1 iommu irq num failed\n");
|
||||
return iommu->num_irq;
|
||||
}
|
||||
|
||||
err = devm_clk_bulk_get_all(dev, &iommu->clocks);
|
||||
if (err >= 0)
|
||||
iommu->num_clocks = err;
|
||||
else if (err == -ENOENT)
|
||||
iommu->num_clocks = 0;
|
||||
else {
|
||||
dev_err(dev, "get av1 iommu clocks failed\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (!dma_dev)
|
||||
dma_dev = &pdev->dev;
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
for (i = 0; i < iommu->num_irq; i++) {
|
||||
int irq = platform_get_irq(pdev, i);
|
||||
|
||||
if (irq < 0) {
|
||||
err = -ENODEV;
|
||||
dev_err(dev, "av1 iommu get irq failed\n");
|
||||
goto err_disable_runtime;
|
||||
}
|
||||
|
||||
err = devm_request_irq(iommu->dev, irq, av1_iommu_irq,
|
||||
IRQF_SHARED, dev_name(dev), iommu);
|
||||
if (err) {
|
||||
dev_err(dev, "av1 iommu request irq handle failed\n");
|
||||
goto err_disable_runtime;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
err = av1d_iommu_init(iommu);
|
||||
if (err) {
|
||||
dev_err(dev, "av1 iommu init failed err %d\n", err);
|
||||
goto err_disable_runtime;
|
||||
}
|
||||
|
||||
/* store av1d-iommu data to dev->platform_data */
|
||||
dev->platform_data = iommu;
|
||||
|
||||
return 0;
|
||||
err_disable_runtime:
|
||||
pm_runtime_disable(dev);
|
||||
clk_bulk_unprepare(iommu->num_clocks, iommu->clocks);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void av1_iommu_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
struct av1d_iommu *av1d_iommu = (struct av1d_iommu *)dev_get_platdata(&pdev->dev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < av1d_iommu->num_irq; i++) {
|
||||
int irq = platform_get_irq(pdev, i);
|
||||
|
||||
devm_free_irq(av1d_iommu->dev, irq, av1d_iommu);
|
||||
}
|
||||
|
||||
pm_runtime_force_suspend(&pdev->dev);
|
||||
}
|
||||
|
||||
static int __maybe_unused av1_iommu_suspend(struct device *dev)
|
||||
{
|
||||
struct av1d_iommu *av1d_iommu = (struct av1d_iommu *)dev_get_platdata(dev);
|
||||
|
||||
if (!av1d_iommu->domain)
|
||||
return 0;
|
||||
|
||||
av1d_iommu_disable(av1d_iommu);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused av1_iommu_resume(struct device *dev)
|
||||
{
|
||||
struct av1d_iommu *av1d_iommu = (struct av1d_iommu *)dev_get_platdata(dev);
|
||||
|
||||
if (!av1d_iommu->domain)
|
||||
return 0;
|
||||
|
||||
return av1d_iommu_enable(av1d_iommu);
|
||||
}
|
||||
|
||||
static struct third_iommu_ops_wrap av1d_iommu_ops = {
|
||||
.attach_dev = av1_iommu_attach_device,
|
||||
.detach_dev = av1_iommu_detach_device,
|
||||
.map = av1_iommu_map,
|
||||
.unmap = av1_iommu_unmap,
|
||||
.flush_iotlb_all = av1_iommu_flush_tlb_all,
|
||||
.iova_to_phys = av1_iommu_iova_to_phys,
|
||||
.free = av1_iommu_domain_free,
|
||||
.enable = av1_iommu_enable,
|
||||
.disable = av1_iommu_disable,
|
||||
.shutdown = av1_iommu_shutdown,
|
||||
.suspend = av1_iommu_suspend,
|
||||
.resume = av1_iommu_resume,
|
||||
.probe = av1_iommu_probe,
|
||||
};
|
||||
|
||||
struct third_iommu_ops_wrap *av1d_iommu_get_ops(void)
|
||||
{
|
||||
return &av1d_iommu_ops;
|
||||
}
|
||||
@@ -1597,7 +1597,9 @@ static int rk_iommu_probe(struct platform_device *pdev)
|
||||
return -EINVAL;
|
||||
|
||||
if (device_property_match_string(dev, "compatible", "rockchip,iommu-av1d") >= 0) {
|
||||
iommu->opt_ops = NULL;
|
||||
iommu->opt_ops = av1d_iommu_get_ops();
|
||||
if (iommu->opt_ops)
|
||||
dev_info(dev, "av1d iommu enabled\n");
|
||||
goto alloc_group;
|
||||
}
|
||||
|
||||
@@ -1825,6 +1827,9 @@ static const struct of_device_id rk_iommu_dt_ids[] = {
|
||||
{ .compatible = "rockchip,rk3568-iommu",
|
||||
.data = &iommu_data_ops_v2,
|
||||
},
|
||||
{ .compatible = "rockchip,iommu-av1d",
|
||||
.data = &iommu_data_ops_v2,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
||||
@@ -77,4 +77,13 @@ static inline int rockchip_iommu_force_reset(struct device *dev)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_ROCKCHIP_MPP_AV1DEC)
|
||||
struct third_iommu_ops_wrap *av1d_iommu_get_ops(void);
|
||||
#else
|
||||
static inline struct third_iommu_ops_wrap *av1d_iommu_get_ops(void)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user