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clk: rockchip: rk3568 export clk id CPLL_333M

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cpll_333m need change rate by ebc.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I39cf3b436d0822c5e9be74f0fa181a74960c3e57
This commit is contained in:
Elaine Zhang
2020-11-12 17:05:30 +08:00
committed by Tao Huang
parent c7a7525815
commit 23dfbd105e
2 changed files with 2 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3568.c
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@@ -462,7 +462,7 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
COMPOSITE_NOMUX(0, "cpll_500m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 7, GFLAGS),
COMPOSITE_NOMUX(0, "cpll_333m", "cpll", CLK_IGNORE_UNUSED,
COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED,
RK3568_CLKSEL_CON(79), 0, 5, DFLAGS,
RK3568_CLKGATE_CON(35), 8, GFLAGS),
COMPOSITE_NOMUX(0, "cpll_250m", "cpll", CLK_IGNORE_UNUSED,

1
include/dt-bindings/clock/rk3568-cru.h
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@@ -74,6 +74,7 @@
#define PLL_NPLL 6
/* cru clocks */
#define CPLL_333M 9
#define ARMCLK 10
#define USB480M 11
#define ACLK_CORE_NIU2BUS 18