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FROMGIT: ASoC: codecs: lpass: fix the order or clks turn off during suspend
The order in which clocks are stopped matters as some of the clock like NPL are derived from MCLK. Without this patch, Dragonboard RB5 DSP would crash with below error: qcom_q6v5_pas 17300000.remoteproc: fatal error received: ABT_dal.c:278:ABTimeout: AHB Bus hang is detected, Number of bus hang detected := 2 , addr0 = 0x3370000 , addr1 = 0x0!!! Turn off fsgen first, followed by npl and then finally mclk, which is exactly the opposite order of enable sequence. Fixes:1dc3459009("ASoC: codecs: lpass: register mclk after runtime pm") Reported-by: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Tested-by: Amit Pundir <amit.pundir@linaro.org> Link: https://lore.kernel.org/r/20230323110125.23790-1-srinivas.kandagatla@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org> Bug: 146449535 (cherry picked from commita4a3203426https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git/log/?h=for-next) Change-Id: I73a42a21898195c98dfbb3e5c38b7c160866dd7b Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
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Treehugger Robot
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4754c5690b
commit
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@@ -3667,9 +3667,9 @@ static int __maybe_unused rx_macro_runtime_suspend(struct device *dev)
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regcache_cache_only(rx->regmap, true);
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regcache_mark_dirty(rx->regmap);
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clk_disable_unprepare(rx->mclk);
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clk_disable_unprepare(rx->npl);
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clk_disable_unprepare(rx->fsgen);
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clk_disable_unprepare(rx->npl);
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clk_disable_unprepare(rx->mclk);
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return 0;
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}
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@@ -1945,9 +1945,9 @@ static int __maybe_unused tx_macro_runtime_suspend(struct device *dev)
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regcache_cache_only(tx->regmap, true);
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regcache_mark_dirty(tx->regmap);
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clk_disable_unprepare(tx->mclk);
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clk_disable_unprepare(tx->npl);
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clk_disable_unprepare(tx->fsgen);
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clk_disable_unprepare(tx->npl);
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clk_disable_unprepare(tx->mclk);
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return 0;
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}
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@@ -2502,9 +2502,9 @@ static int __maybe_unused wsa_macro_runtime_suspend(struct device *dev)
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regcache_cache_only(wsa->regmap, true);
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regcache_mark_dirty(wsa->regmap);
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clk_disable_unprepare(wsa->mclk);
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clk_disable_unprepare(wsa->npl);
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clk_disable_unprepare(wsa->fsgen);
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clk_disable_unprepare(wsa->npl);
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clk_disable_unprepare(wsa->mclk);
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return 0;
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}
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