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media_modules: tl1 bringup changes [1/3]

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PD#SWPL-520

Problem:
tl1 bringup changes

Solution:
1. add tl1 cpu type
2. hevc decoder support 8k
3. replace get_cpu_type() with get_cpu_major_id()
ucode commitid:
d9582c3a6697c25d81b706d41d20d8908158ef9f

Change-Id:
Iac3a5f20698277d3f7f500fba6a27b88f6ac5839

Verify:
p212, w400

Change-Id: Iac3a5f20698277d3f7f500fba6a27b88f6ac5839
Signed-off-by: shihong.zheng <shihong.zheng@amlogic.com>
This commit is contained in:
shihong.zheng
2018-10-02 16:51:26 +08:00
committed by Dongjin Kim
parent 4d1f1ffb27
commit 24e759113f
14 changed files with 692 additions and 190 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/amlogic/media_modules/common/chips/chips.c
View File

@@ -31,6 +31,7 @@
#include "chips.h"
#include <linux/amlogic/media/utils/log.h>
#include <linux/amlogic/media/utils/vdec_reg.h>
#include "decoder_cpu_ver_info.h"
#define VIDEO_FIRMWARE_FATHER_NAME "video"
@@ -56,22 +57,23 @@ struct type_name {
const char *name;
};
static const struct type_name cpu_type_name[] = {
{MESON_CPU_MAJOR_ID_M6, "m6"},
{MESON_CPU_MAJOR_ID_M6TV, "m6tv"},
{MESON_CPU_MAJOR_ID_M6TVL, "m6tvl"},
{MESON_CPU_MAJOR_ID_M8, "m8"},
{MESON_CPU_MAJOR_ID_MTVD, "mtvd"},
{MESON_CPU_MAJOR_ID_M8B, "m8b"},
{MESON_CPU_MAJOR_ID_MG9TV, "mg9tv"},
{MESON_CPU_MAJOR_ID_M8M2, "m8"},
{MESON_CPU_MAJOR_ID_GXBB, "gxbb"},
{MESON_CPU_MAJOR_ID_GXTVBB, "gxtvbb"},
{MESON_CPU_MAJOR_ID_GXL, "gxl"},
{MESON_CPU_MAJOR_ID_GXM, "gxm"},
{MESON_CPU_MAJOR_ID_TXL, "txl"},
{MESON_CPU_MAJOR_ID_TXLX, "txlx"},
{MESON_CPU_MAJOR_ID_G12A, "g12a"},
{MESON_CPU_MAJOR_ID_G12B, "g12b"},
{AM_MESON_CPU_MAJOR_ID_M6, "m6"},
{AM_MESON_CPU_MAJOR_ID_M6TV, "m6tv"},
{AM_MESON_CPU_MAJOR_ID_M6TVL, "m6tvl"},
{AM_MESON_CPU_MAJOR_ID_M8, "m8"},
{AM_MESON_CPU_MAJOR_ID_MTVD, "mtvd"},
{AM_MESON_CPU_MAJOR_ID_M8B, "m8b"},
{AM_MESON_CPU_MAJOR_ID_MG9TV, "mg9tv"},
{AM_MESON_CPU_MAJOR_ID_M8M2, "m8"},
{AM_MESON_CPU_MAJOR_ID_GXBB, "gxbb"},
{AM_MESON_CPU_MAJOR_ID_GXTVBB, "gxtvbb"},
{AM_MESON_CPU_MAJOR_ID_GXL, "gxl"},
{AM_MESON_CPU_MAJOR_ID_GXM, "gxm"},
{AM_MESON_CPU_MAJOR_ID_TXL, "txl"},
{AM_MESON_CPU_MAJOR_ID_TXLX, "txlx"},
{AM_MESON_CPU_MAJOR_ID_G12A, "g12a"},
{AM_MESON_CPU_MAJOR_ID_G12B, "g12b"},
{AM_MESON_CPU_MAJOR_ID_TL1, "tl1"},
{0, NULL},
};
@@ -99,7 +101,7 @@ const char *get_cpu_type_name(void)
return get_type_name(cpu_type_name,
sizeof(cpu_type_name) / sizeof(struct type_name),
get_cpu_type());
get_cpu_major_id());
}
EXPORT_SYMBOL(get_cpu_type_name);

8
drivers/amlogic/media_modules/common/chips/decoder_cpu_ver_info.c
View File

@@ -35,7 +35,8 @@ static enum AM_MESON_CPU_MAJOR_ID cpu_ver_info[AM_MESON_CPU_MAJOR_ID_MAX - MAJOR
AM_MESON_CPU_MAJOR_ID_GXLX,
AM_MESON_CPU_MAJOR_ID_TXHD,
AM_MESON_CPU_MAJOR_ID_G12A,
AM_MESON_CPU_MAJOR_ID_G12B
AM_MESON_CPU_MAJOR_ID_G12B,
AM_MESON_CPU_MAJOR_ID_TL1,
};
static const struct of_device_id cpu_ver_of_match[] = {
@@ -68,6 +69,11 @@ static const struct of_device_id cpu_ver_of_match[] = {
.compatible = "amlogic, cpu-major-id-txlx",
.data = &cpu_ver_info[AM_MESON_CPU_MAJOR_ID_TXLX - MAJOR_ID_START],
},
{
.compatible = "amlogic, cpu-major-id-tl1",
.data = &cpu_ver_info[AM_MESON_CPU_MAJOR_ID_TL1 - MAJOR_ID_START],
},
{},
};

2
drivers/amlogic/media_modules/common/chips/decoder_cpu_ver_info.h
View File

@@ -23,6 +23,8 @@ enum AM_MESON_CPU_MAJOR_ID
AM_MESON_CPU_MAJOR_ID_TXHD = 0x27,
AM_MESON_CPU_MAJOR_ID_G12A = 0x28,
AM_MESON_CPU_MAJOR_ID_G12B = 0x29,
AM_MESON_CPU_MAJOR_ID_GXLX2 = 0x2a,
AM_MESON_CPU_MAJOR_ID_TL1 = 0x2e,
AM_MESON_CPU_MAJOR_ID_MAX,
};

3
drivers/amlogic/media_modules/common/firmware/firmware_drv.c
View File

@@ -38,6 +38,7 @@
#include <linux/amlogic/major.h>
#include <linux/cdev.h>
#include <linux/crc32.h>
#include "../chips/decoder_cpu_ver_info.h"
/* major.minor.revision */
#define PACK_VERS "v0.0.1"
@@ -721,7 +722,7 @@ static int fw_mgr_init(void)
if (IS_ERR_OR_NULL(g_mgr))
return -ENOMEM;
g_mgr->cur_cpu = get_cpu_type();
g_mgr->cur_cpu = get_cpu_major_id();
INIT_LIST_HEAD(&g_mgr->files_head);
INIT_LIST_HEAD(&g_mgr->fw_head);
spin_lock_init(&g_mgr->lock);

12
drivers/amlogic/media_modules/common/firmware/firmware_type.c
View File

@@ -1,5 +1,5 @@
#include "firmware_type.h"
#include <linux/amlogic/cpu_version.h>
#include "../chips/decoder_cpu_ver_info.h"
static const struct format_name_s format_name[] = {
{VIDEO_DEC_MPEG12, "mpeg12"},
@@ -42,10 +42,12 @@ static const struct format_name_s format_name[] = {
};
static const struct cpu_type_s cpu_type[] = {
{MESON_CPU_MAJOR_ID_GXL, "gxl"},
{MESON_CPU_MAJOR_ID_GXM, "gxm"},
{MESON_CPU_MAJOR_ID_G12A, "g12a"},
{MESON_CPU_MAJOR_ID_G12B, "g12b"},
{AM_MESON_CPU_MAJOR_ID_GXL, "gxl"},
{AM_MESON_CPU_MAJOR_ID_GXM, "gxm"},
{AM_MESON_CPU_MAJOR_ID_G12A, "g12a"},
{AM_MESON_CPU_MAJOR_ID_G12B, "g12b"},
{AM_MESON_CPU_MAJOR_ID_GXLX2, "gxlx2"},
{AM_MESON_CPU_MAJOR_ID_TL1, "tl1"},
};
const char *get_fw_format_name(unsigned int format)

10
drivers/amlogic/media_modules/common/media_clock/clk/clkg12.c
View File

@@ -599,6 +599,16 @@ static int hevc_clock_init(void)
return (gp_pll_user_hevc) ? 0 : -ENOMEM;
}
static int hevc_back_clock_init(void)
{
return 0;
}
static int hevc_back_clock_set(int clk)
{
return 0;
}
static int hevc_clock_set(int clk)
{
int use_gpll = 0;

5
drivers/amlogic/media_modules/common/media_clock/switch/amports_gate.c
View File

@@ -191,14 +191,9 @@ int amports_clock_gate_init(struct device *dev)
}
EXPORT_SYMBOL(amports_clock_gate_init);
static int amports_switch_gate(struct gate_switch_node *gate_node, int enable)
{
return 0;
}
int amports_switch_gate(const char *name, int enable)
{
amports_switch_gate(0, 0);
return 0;
}
EXPORT_SYMBOL(amports_switch_gate);

338
drivers/amlogic/media_modules/frame_provider/decoder/avs2/vavs2.c
View File

@@ -57,7 +57,6 @@
#include <linux/amlogic/tee.h>
#define MIX_STREAM_SUPPORT
#define SUPPORT_4K2K
#define G12A_BRINGUP_DEBUG
@@ -150,11 +149,6 @@
#define MULTI_INSTANCE_SUPPORT
/* #define ERROR_HANDLE_DEBUG */
#if 0 /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B*/
#undef SUPPORT_4K2K
#else
#define SUPPORT_4K2K
#endif
#ifndef STAT_KTHREAD
#define STAT_KTHREAD 0x40
@@ -266,7 +260,14 @@ static u32 on_no_keyframe_skiped;
#define COUNT_BUF_SIZE (0x300 * 4 * 4)
/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
#define MAX_FRAME_4K_NUM 0x1200
#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
#define MAX_FRAME_8K_NUM 0x4800
//#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
static int get_frame_mmu_map_size(void)
{
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
return (MAX_FRAME_8K_NUM * 4);
return (MAX_FRAME_4K_NUM * 4);
}
static inline int div_r32(int64_t m, int n)
{
@@ -436,6 +437,7 @@ static void WRITE_VREG_DBG2(unsigned adr, unsigned val)
#ifdef AVS2_10B_MMU
#define MMU_COMPRESS_HEADER_SIZE 0x48000
#define MMU_COMPRESS_8K_HEADER_SIZE 0x48000*4
#endif
#define INVALID_IDX -1 /* Invalid buffer index.*/
@@ -705,6 +707,12 @@ static int avs2_print_cont(struct AVS2Decoder_s *dec,
return 0;
}
static int get_compress_header_size(void)
{
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
return MMU_COMPRESS_8K_HEADER_SIZE;
return MMU_COMPRESS_HEADER_SIZE;
}
static void reset_process_time(struct AVS2Decoder_s *dec)
{
if (dec->start_process_time) {
@@ -791,7 +799,7 @@ static int get_double_write_ratio(struct AVS2Decoder_s *dec,
return ratio;
}
#define MAX_4K_NUM 0x1200
//#define MAX_4K_NUM 0x1200
#ifdef AVS2_10B_MMU
int avs2_alloc_mmu(
struct AVS2Decoder_s *dec,
@@ -803,13 +811,17 @@ int avs2_alloc_mmu(
{
int bit_depth_10 = (bit_depth == AVS2_BITS_10);
int picture_size;
int cur_mmu_4k_number;
int cur_mmu_4k_number, max_frame_num;
picture_size = compute_losless_comp_body_size(
dec, pic_width, pic_height,
bit_depth_10);
cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
if (cur_mmu_4k_number > MAX_4K_NUM) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
max_frame_num = MAX_FRAME_8K_NUM;
else
max_frame_num = MAX_FRAME_4K_NUM;
if (cur_mmu_4k_number > max_frame_num) {
pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
cur_mmu_4k_number, pic_width, pic_height);
return -1;
@@ -1077,13 +1089,9 @@ static u32 decode_pic_begin;
static uint slice_parse_begin;
static u32 step;
#ifdef MIX_STREAM_SUPPORT
#ifdef SUPPORT_4K2K
static u32 buf_alloc_width = 4096;
static u32 buf_alloc_height = 2304;
#else
static u32 buf_alloc_width = 1920;
static u32 buf_alloc_height = 1088;
#endif
static u32 dynamic_buf_num_margin;
#else
static u32 buf_alloc_width;
@@ -1153,7 +1161,7 @@ static DEFINE_MUTEX(vavs2_mutex);
#define HEVC_DEC_STATUS_REG HEVC_ASSIST_SCRATCH_0
#define HEVC_RPM_BUFFER HEVC_ASSIST_SCRATCH_1
#define HEVC_SHORT_TERM_RPS HEVC_ASSIST_SCRATCH_2
#define AVS2_ALF_SWAP_BUFFER HEVC_ASSIST_SCRATCH_2
#define HEVC_RCS_BUFFER HEVC_ASSIST_SCRATCH_3
#define HEVC_SPS_BUFFER HEVC_ASSIST_SCRATCH_4
#define HEVC_PPS_BUFFER HEVC_ASSIST_SCRATCH_5
@@ -1210,7 +1218,7 @@ bit [31:20]: used by ucode for debug purpose
#define RPM_BUF_SIZE (0x400 * 2)
#define LMEM_BUF_SIZE (0x400 * 2)
#define WORK_BUF_SPEC_NUM 2
#define WORK_BUF_SPEC_NUM 3
static struct BuffInfo_s amvavs2_workbuff_spec[WORK_BUF_SPEC_NUM] = {
{
/* 8M bytes */
@@ -1402,6 +1410,71 @@ static struct BuffInfo_s amvavs2_workbuff_spec[WORK_BUF_SPEC_NUM] = {
.lmem = {
.buf_size = 0x400 * 2,
}
},
{
.max_width = 4096*2,
.max_height = 2304*2,
.ipp = {
// IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
.buf_size = 0x4000*2,
},
.sao_abv = {
.buf_size = 0x30000*2,
},
.sao_vb = {
.buf_size = 0x30000*2,
},
.short_term_rps = {
// SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
.buf_size = 0x800,
},
.rcs = {
// RCS STORE AREA - Max 16 RCS, each has 32 bytes, total 0x0400 bytes
.buf_size = 0x400,
},
.sps = {
// SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
.buf_size = 0x800,
},
.pps = {
// PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
.buf_size = 0x2000,
},
.sao_up = {
// SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
.buf_size = 0x2800*2,
},
.swap_buf = {
// 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
.buf_size = 0x800,
},
.swap_buf2 = {
.buf_size = 0x800,
},
.scalelut = {
// support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
.buf_size = 0x8000*2,
},
.dblk_para = { .buf_size = 0x40000*2, },
.dblk_data = { .buf_size = 0x80000*2, },
.dblk_data2 = { .buf_size = 0x80000*2, },
#ifdef AVS2_10B_MMU
.mmu_vbh = {
.buf_size = 0x5000*2, //2*16*2304/4, 4K
},
.cm_header = {
.buf_size = MMU_COMPRESS_8K_HEADER_SIZE*17, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
},
#endif
.mpred_above = {
.buf_size = 0x8000*2,
},
.mpred_mv = {
.buf_size = 0x100000*16*4, //4k2k , 0x100000 per buffer
},
.rpm = {
.buf_size = 0x80*2,
}
}
};
@@ -1945,7 +2018,7 @@ static void init_pic_list(struct AVS2Decoder_s *dec,
unsigned long buf_addr;
if (decoder_bmmu_box_alloc_buf_phy
(dec->bmmu_box,
HEADER_BUFFER_IDX(i), MMU_COMPRESS_HEADER_SIZE,
HEADER_BUFFER_IDX(i), get_compress_header_size(),
DRIVER_HEADER_NAME,
&buf_addr) < 0){
avs2_print(dec, 0,
@@ -1996,6 +2069,7 @@ static void init_pic_list_hw(struct AVS2Decoder_s *dec)
int i;
struct avs2_decoder *avs2_dec = &dec->avs2_dec;
struct avs2_frame_s *pic;
if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TL1) {
/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0x0);*/
WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
(0x1 << 1) | (0x1 << 2));
@@ -2004,6 +2078,7 @@ static void init_pic_list_hw(struct AVS2Decoder_s *dec)
WRITE_VREG(HEVC2_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
(0x1 << 1) | (0x1 << 2));
#endif
}
for (i = 0; i < dec->used_buf_num; i++) {
if (i == (dec->used_buf_num - 1))
pic = avs2_dec->m_bg;
@@ -2011,7 +2086,14 @@ static void init_pic_list_hw(struct AVS2Decoder_s *dec)
pic = avs2_dec->fref[i];
if (pic->index < 0)
break;
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
(0x1 << 1) | (i << 8));
#ifdef DUAL_CORE_64
WRITE_VREG(HEVC2_MPP_ANC2AXI_TBL_CONF_ADDR,
(0x1 << 1) | (i << 8));
#endif
}
#ifdef AVS2_10B_MMU
/*WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
pic->header_adr
@@ -2205,6 +2287,139 @@ static int config_mc_buffer(struct AVS2Decoder_s *dec)
return 0;
}
static void mcrcc_get_hitrate(void)
{
u32 tmp;
u32 raw_mcr_cnt;
u32 hit_mcr_cnt;
u32 byp_mcr_cnt_nchoutwin;
u32 byp_mcr_cnt_nchcanv;
int hitrate;
if (debug & AVS2_DBG_CACHE)
pr_info("[cache_util.c] Entered mcrcc_get_hitrate...\n");
WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x0<<1));
raw_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x1<<1));
hit_mcr_cnt = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x2<<1));
byp_mcr_cnt_nchoutwin = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x3<<1));
byp_mcr_cnt_nchcanv = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
if (debug & AVS2_DBG_CACHE) {
pr_info("raw_mcr_cnt_total: %d\n",raw_mcr_cnt);
pr_info("hit_mcr_cnt_total: %d\n",hit_mcr_cnt);
pr_info("byp_mcr_cnt_nchoutwin_total: %d\n",byp_mcr_cnt_nchoutwin);
pr_info("byp_mcr_cnt_nchcanv_total: %d\n",byp_mcr_cnt_nchcanv);
}
WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x4<<1));
tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
if (debug & AVS2_DBG_CACHE)
pr_info("miss_mcr_0_cnt_total: %d\n", tmp);
WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x5<<1));
tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
if (debug & AVS2_DBG_CACHE)
pr_info("miss_mcr_1_cnt_total: %d\n", tmp);
WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x6<<1));
tmp = READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
if (debug & AVS2_DBG_CACHE)
pr_info("hit_mcr_0_cnt_total: %d\n",tmp);
WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)(0x7<<1));
tmp= READ_VREG(HEVCD_MCRCC_PERFMON_DATA);
if (debug & AVS2_DBG_CACHE)
pr_info("hit_mcr_1_cnt_total: %d\n",tmp);
if (raw_mcr_cnt != 0) {
hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
pr_info("MCRCC_HIT_RATE : %d\n", hitrate);
hitrate = ((byp_mcr_cnt_nchoutwin + byp_mcr_cnt_nchcanv)
/raw_mcr_cnt) * 100;
pr_info("MCRCC_BYP_RATE : %d\n", hitrate);
} else {
pr_info("MCRCC_HIT_RATE : na\n");
pr_info("MCRCC_BYP_RATE : na\n");
}
return;
}
static void decomp_get_hitrate(void)
{
u32 raw_mcr_cnt;
u32 hit_mcr_cnt;
int hitrate;
if (debug & AVS2_DBG_CACHE)
pr_info("[cache_util.c] Entered decomp_get_hitrate...\n");
WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x0<<1));
raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x1<<1));
hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
if (debug & AVS2_DBG_CACHE) {
pr_info("hcache_raw_cnt_total: %d\n",raw_mcr_cnt);
pr_info("hcache_hit_cnt_total: %d\n",hit_mcr_cnt);
}
if (raw_mcr_cnt != 0) {
hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
pr_info("DECOMP_HCACHE_HIT_RATE : %d\n", hitrate);
} else {
pr_info("DECOMP_HCACHE_HIT_RATE : na\n");
}
WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x2<<1));
raw_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x3<<1));
hit_mcr_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
if (debug & AVS2_DBG_CACHE) {
pr_info("dcache_raw_cnt_total: %d\n", raw_mcr_cnt);
pr_info("dcache_hit_cnt_total: %d\n", hit_mcr_cnt);
}
if (raw_mcr_cnt != 0) {
hitrate = (hit_mcr_cnt / raw_mcr_cnt) * 100;
pr_info("DECOMP_DCACHE_HIT_RATE : %d\n", hitrate);
} else {
pr_info("DECOMP_DCACHE_HIT_RATE : na\n");
}
return;
}
static void decomp_get_comprate(void)
{
u32 raw_ucomp_cnt;
u32 fast_comp_cnt;
u32 slow_comp_cnt;
int comprate;
if (debug & AVS2_DBG_CACHE)
pr_info("[cache_util.c] Entered decomp_get_comprate...\n");
WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x4<<1));
fast_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x5<<1));
slow_comp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)(0x6<<1));
raw_ucomp_cnt = READ_VREG(HEVCD_MPP_DECOMP_PERFMON_DATA);
if (debug & AVS2_DBG_CACHE) {
pr_info("decomp_fast_comp_total: %d\n", fast_comp_cnt);
pr_info("decomp_slow_comp_total: %d\n", slow_comp_cnt);
pr_info("decomp_raw_uncomp_total: %d\n", raw_ucomp_cnt);
}
if (raw_ucomp_cnt != 0) {
comprate = ((fast_comp_cnt + slow_comp_cnt)
/ raw_ucomp_cnt) * 100;
pr_info("DECOMP_COMP_RATIO : %d\n", comprate);
} else {
pr_info("DECOMP_COMP_RATIO : na\n");
}
return;
}
static void config_mcrcc_axi_hw(struct AVS2Decoder_s *dec)
{
@@ -2220,11 +2435,11 @@ static void config_mcrcc_axi_hw(struct AVS2Decoder_s *dec)
return;
}
#if 0
mcrcc_get_hitrate();
decomp_get_hitrate();
decomp_get_comprate();
#endif
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
mcrcc_get_hitrate();
decomp_get_hitrate();
decomp_get_comprate();
}
if ((avs2_dec->img.type == B_IMG) ||
(avs2_dec->img.type == F_IMG)) { /*B-PIC or F_PIC*/
@@ -2574,7 +2789,7 @@ static void config_sao_hw(struct AVS2Decoder_s *dec)
data32 |= endian; /* Big-Endian per 64-bit */
data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
#if 0
if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) {
if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
if (get_double_write_mode(dec) == 0)
data32 |= 0x2; /*disable double write*/
#ifndef AVS2_10B_MMU
@@ -2919,7 +3134,7 @@ static void avs2_config_work_space_hw(struct AVS2Decoder_s *dec)
WRITE_VREG(HEVCD_IPP_LINEBUFF_BASE, buf_spec->ipp.buf_start);
if ((debug & AVS2_DBG_SEND_PARAM_WITH_REG) == 0)
WRITE_VREG(HEVC_RPM_BUFFER, (u32)dec->rpm_phy_addr);
WRITE_VREG(HEVC_SHORT_TERM_RPS, buf_spec->short_term_rps.buf_start);
WRITE_VREG(AVS2_ALF_SWAP_BUFFER, buf_spec->short_term_rps.buf_start);
WRITE_VREG(HEVC_RCS_BUFFER, buf_spec->rcs.buf_start);
WRITE_VREG(HEVC_SPS_BUFFER, buf_spec->sps.buf_start);
WRITE_VREG(HEVC_PPS_BUFFER, buf_spec->pps.buf_start);
@@ -2984,11 +3199,32 @@ static void avs2_config_work_space_hw(struct AVS2Decoder_s *dec)
WRITE_VREG(HEVC_SAO_CTRL5, data32);
#endif
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
WRITE_VREG(HEVC_MPRED_ABV_START_ADDR, buf_spec->mpred_above.buf_start);
}
WRITE_VREG(LMEM_DUMP_ADR, (u32)dec->lmem_phy_addr);
}
static void decomp_perfcount_reset(void)
{
if (debug & AVS2_DBG_CACHE)
pr_info("[cache_util.c] Entered decomp_perfcount_reset...\n");
WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x1);
WRITE_VREG(HEVCD_MPP_DECOMP_PERFMON_CTL, (unsigned int)0x0);
return;
}
static void mcrcc_perfcount_reset(void)
{
if (debug & AVS2_DBG_CACHE)
pr_info("[cache_util.c] Entered mcrcc_perfcount_reset...\n");
WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x1);
WRITE_VREG(HEVCD_MCRCC_PERFMON_CTL, (unsigned int)0x0);
return;
}
static void avs2_init_decoder_hw(struct AVS2Decoder_s *dec)
{
unsigned int data32;
@@ -3167,6 +3403,11 @@ static void avs2_init_decoder_hw(struct AVS2Decoder_s *dec)
avs2_print(dec, AVS2_DBG_BUFMGR_MORE,
"Bitstream level Init for DBLK .Done.\n");
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
mcrcc_perfcount_reset();
decomp_perfcount_reset();
}
return;
}
@@ -3245,7 +3486,7 @@ static void avs2_local_uninit(struct AVS2Decoder_s *dec)
if (dec->frame_mmu_map_addr) {
if (dec->frame_mmu_map_phy_addr)
dma_free_coherent(amports_get_dma_device(),
FRAME_MMU_MAP_SIZE, dec->frame_mmu_map_addr,
get_frame_mmu_map_size(), dec->frame_mmu_map_addr,
dec->frame_mmu_map_phy_addr);
dec->frame_mmu_map_addr = NULL;
}
@@ -3263,17 +3504,18 @@ static int avs2_local_init(struct AVS2Decoder_s *dec)
struct BuffInfo_s *cur_buf_info = NULL;
cur_buf_info = &dec->work_space_buf_store;
#ifdef SUPPORT_4K2K
if (vdec_is_support_4k())
memcpy(cur_buf_info, &amvavs2_workbuff_spec[1], /* 4k */
sizeof(struct BuffInfo_s));
else
if (vdec_is_support_4k()) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
memcpy(cur_buf_info, &amvavs2_workbuff_spec[2], /* 8k */
sizeof(struct BuffInfo_s));
else
memcpy(cur_buf_info, &amvavs2_workbuff_spec[1], /* 4k */
sizeof(struct BuffInfo_s));
} else
memcpy(cur_buf_info, &amvavs2_workbuff_spec[0],/* 1080p */
sizeof(struct BuffInfo_s));
#else
memcpy(cur_buf_info, &amvavs2_workbuff_spec[0], /* 1080p work space */
sizeof(struct BuffInfo_s));
#endif
cur_buf_info->start_adr = dec->buf_start;
#ifndef AVS2_10B_MMU
dec->mc_buf_spec.buf_end = dec->buf_start + dec->buf_size;
@@ -3303,6 +3545,11 @@ static int avs2_local_init(struct AVS2Decoder_s *dec)
&& (buf_alloc_width > 1920 && buf_alloc_height > 1088)) {
buf_alloc_width = 1920;
buf_alloc_height = 1088;
} else {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
buf_alloc_width = 8192;
buf_alloc_height = 4608;
}
}
dec->init_pic_w = buf_alloc_width ? buf_alloc_width :
(dec->vavs2_amstream_dec_info.width ?
@@ -3377,7 +3624,7 @@ static int avs2_local_init(struct AVS2Decoder_s *dec)
#ifdef AVS2_10B_MMU
dec->frame_mmu_map_addr = dma_alloc_coherent(amports_get_dma_device(),
FRAME_MMU_MAP_SIZE,
get_frame_mmu_map_size(),
&dec->frame_mmu_map_phy_addr, GFP_KERNEL);
if (dec->frame_mmu_map_addr == NULL) {
pr_err("%s: failed to alloc count_buffer\n", __func__);
@@ -5871,14 +6118,15 @@ static int __init amvdec_avs2_driver_init_module(void)
#ifdef AVS2_10B_MMU
struct BuffInfo_s *p_buf_info;
#ifdef SUPPORT_4K2K
if (vdec_is_support_4k())
p_buf_info = &amvavs2_workbuff_spec[1];
else
if (vdec_is_support_4k()) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
p_buf_info = &amvavs2_workbuff_spec[2];
else
p_buf_info = &amvavs2_workbuff_spec[1];
} else
p_buf_info = &amvavs2_workbuff_spec[0];
#else
p_buf_info = &amvavs2_workbuff_spec[0];
#endif
init_buff_spec(NULL, p_buf_info);
work_buf_size =
(p_buf_info->end_adr - p_buf_info->start_adr
@@ -5907,7 +6155,7 @@ static int __init amvdec_avs2_driver_init_module(void)
}
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
/*&& get_cpu_type() != MESON_CPU_MAJOR_ID_GXLX*/) {
/*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/) {
if (vdec_is_support_4k())
amvdec_avs2_profile.profile =
"4k, 10bit, dwrite, compressed";

12
drivers/amlogic/media_modules/frame_provider/decoder/h264_multi/vmh264.c
View File

@@ -1226,7 +1226,7 @@ static void hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
/* ipp_enable*/
WRITE_VREG(HEVCD_IPP_TOP_CNTL, 0x1 << 1);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
if (hw->double_write_mode)
@@ -1389,7 +1389,7 @@ static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
}
/*Reset SAO + Enable SAO slice_start*/
if (hw->mmu_enable && get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A)
if (hw->mmu_enable && get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
WRITE_VREG(HEVC_DBLK_CFG0, 0x1); // reset buffer32x4 in lpf for every picture
WRITE_VREG(HEVC_SAO_INT_STATUS,
READ_VREG(HEVC_SAO_INT_STATUS) | 0x1 << 28);
@@ -1398,7 +1398,7 @@ static void hevc_sao_set_pic_buffer(struct vdec_h264_hw_s *hw,
/*pr_info("hevc_sao_set_pic_buffer:mc_y_adr: %x\n", mc_y_adr);*/
/*Send coommand to hevc-code to supply 4k buffers to sao*/
if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) {
if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
WRITE_VREG(H265_SAO_4K_SET_BASE, (u32)hw->frame_mmu_map_phy_addr);
WRITE_VREG(H265_SAO_4K_SET_COUNT, MAX_FRAME_4K_NUM);
} else
@@ -1473,7 +1473,7 @@ static void hevc_sao_wait_done(struct vdec_h264_hw_s *hw)
}
timeout = jiffies + HZ;
if ((hw->frame_busy == 1) && (hw->frame_done == 1) ) {
if (get_cpu_type() < MESON_CPU_MAJOR_ID_G12A) {
if (get_cpu_major_id() < MESON_CPU_MAJOR_ID_G12A) {
WRITE_VREG(SYS_COMMAND, H265_ABORT_SAO_4K_SET);
while ((READ_VREG(SYS_COMMAND) & 0xff) !=
H265_ABORT_SAO_4K_SET_DONE) {
@@ -6923,7 +6923,7 @@ static void run(struct vdec_s *vdec, unsigned long mask,
WRITE_VREG(AV_SCRATCH_K, udebug_flag);
mod_timer(&hw->check_timer, jiffies + CHECK_INTERVAL);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
if (hw->mmu_enable)
SET_VREG_MASK(VDEC_ASSIST_MMC_CTRL1, 1 << 3);
@@ -7306,7 +7306,7 @@ static int ammvdec_h264_probe(struct platform_device *pdev)
DCAC_READ_MARGIN;
if (hw->mmu_enable) {
u32 extif_size = EXTIF_BUF_SIZE;
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A)
if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A)
extif_size <<= 1;
if (decoder_bmmu_box_alloc_buf_phy(hw->bmmu_box, BMMU_EXTIF_IDX,
extif_size, DRIVER_NAME, &hw->extif_addr) < 0) {

199
drivers/amlogic/media_modules/frame_provider/decoder/h265/vh265.c
View File

@@ -59,8 +59,12 @@
#define MPRED_MV_BUF_SIZE 0x120000
#define MMU_COMPRESS_HEADER_SIZE 0x48000
#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
#define MAX_FRAME_4K_NUM 0x1200
#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
#define MAX_FRAME_8K_NUM (0x1200*4)
//#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
#define H265_MMU_MAP_BUFFER HEVC_ASSIST_SCRATCH_7
#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
@@ -73,7 +77,6 @@
#define HEVC_DBLK_CFGB 0x350b
#define HEVCD_MPP_DECOMP_AXIURG_CTL 0x34c7
#define MEM_NAME "codec_265"
/* #include <mach/am_regs.h> */
#include <linux/amlogic/media/utils/vdec_reg.h>
@@ -86,11 +89,6 @@
#define SEND_LMEM_WITH_RPM
#define SUPPORT_10BIT
/* #define ERROR_HANDLE_DEBUG */
#if 0/*MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B*/
#undef SUPPORT_4K2K
#else
#define SUPPORT_4K2K
#endif
#ifndef STAT_KTHREAD
#define STAT_KTHREAD 0x40
@@ -114,8 +112,9 @@
#define PTS_MODE_SWITCHING_RECOVERY_THREASHOLD 3
#define DUR2PTS(x) ((x)*90/96)
#define MAX_SIZE (4096 + 2304)
#define OVER_SIZE(w, h) (MAX_SIZE < (w + h))
#define MAX_SIZE_8K ((4096 * 2304) * 2)
#define MAX_SIZE_4K (4096 * 2304)
static struct semaphore h265_sema;
@@ -849,7 +848,7 @@ struct BuffInfo_s {
struct buff_s rpm;
struct buff_s lmem;
};
#define WORK_BUF_SPEC_NUM 2
#define WORK_BUF_SPEC_NUM 3
static struct BuffInfo_s amvh265_workbuff_spec[WORK_BUF_SPEC_NUM] = {
{
/* 8M bytes */
@@ -1051,6 +1050,76 @@ static struct BuffInfo_s amvh265_workbuff_spec[WORK_BUF_SPEC_NUM] = {
.lmem = {
.buf_size = 0x500 * 2,
}
},
{
.max_width = 4096*2,
.max_height = 2048*2,
.ipp = {
// IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
.buf_size = 0x4000*2,
},
.sao_abv = {
.buf_size = 0x30000*2,
},
.sao_vb = {
.buf_size = 0x30000*2,
},
.short_term_rps = {
// SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
.buf_size = 0x800,
},
.vps = {
// VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
.buf_size = 0x800,
},
.sps = {
// SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
.buf_size = 0x800,
},
.pps = {
// PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
.buf_size = 0x2000,
},
.sao_up = {
// SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
.buf_size = 0x2800*2,
},
.swap_buf = {
// 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
.buf_size = 0x800,
},
.swap_buf2 = {
.buf_size = 0x800,
},
.scalelut = {
// support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
.buf_size = 0x8000*2,
},
.dblk_para = {.buf_size = 0x40000*2, }, // dblk parameter
.dblk_data = {.buf_size = 0x80000*2, }, // dblk data for left/top
.dblk_data2 = {.buf_size = 0x80000*2, }, // dblk data for adapter
.mmu_vbh = {
.buf_size = 0x5000*2, //2*16*2304/4, 4K
},
.cm_header = {
.buf_size = MMU_COMPRESS_8K_HEADER_SIZE *
MAX_REF_PIC_NUM, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
},
.mpred_above = {
.buf_size = 0x8000*2,
},
#ifdef MV_USE_FIXED_BUF
.mpred_mv = {
.buf_size = MPRED_MV_BUF_SIZE * MAX_REF_PIC_NUM * 4, //4k2k , 0x120000 per buffer
},
#endif
.rpm = {
.buf_size = RPM_BUF_SIZE,
},
.lmem = {
.buf_size = 0x500 * 2,
},
}
};
@@ -1567,6 +1636,29 @@ u32 again_threshold = 0x40;
#define get_lmem_params(hevc, ladr) \
hevc->lmem_ptr[ladr - (ladr & 0x3) + 3 - (ladr & 0x3)]
static int get_frame_mmu_map_size(void)
{
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
return (MAX_FRAME_8K_NUM * 4);
return (MAX_FRAME_4K_NUM * 4);
}
static int is_oversize(int w, int h)
{
int max = (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)?
MAX_SIZE_8K : MAX_SIZE_4K;
if (w < 0 || h < 0)
return true;
if (h != 0 && (w > max / h))
return true;
return false;
}
void check_head_error(struct hevc_state_s *hevc)
{
#define pcm_enabled_flag 0x040
@@ -2283,11 +2375,14 @@ static int cal_current_buf_size(struct hevc_state_s *hevc,
int dw_mode = get_double_write_mode(hevc);
if (hevc->mmu_enable)
buf_size =
((MMU_COMPRESS_HEADER_SIZE + 0xffff) >> 16)
<< 16;
else
if (hevc->mmu_enable) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
buf_size = ((MMU_COMPRESS_8K_HEADER_SIZE + 0xffff) >> 16)
<< 16;
else
buf_size = ((MMU_COMPRESS_HEADER_SIZE + 0xffff) >> 16)
<< 16;
} else
buf_size = 0;
if (dw_mode) {
@@ -2506,7 +2601,12 @@ static int config_pic(struct hevc_state_s *hevc, struct PIC_s *pic)
if (hevc->mmu_enable) {
pic->header_adr = hevc->m_BUF[i].start_adr;
y_adr = hevc->m_BUF[i].start_adr + MMU_COMPRESS_HEADER_SIZE;
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
y_adr = hevc->m_BUF[i].start_adr +
MMU_COMPRESS_8K_HEADER_SIZE;
else
y_adr = hevc->m_BUF[i].start_adr +
MMU_COMPRESS_HEADER_SIZE;
} else
y_adr = hevc->m_BUF[i].start_adr;
@@ -3065,6 +3165,7 @@ static void apply_ref_pic_set(struct hevc_state_s *hevc, int cur_poc,
unsigned char is_referenced;
/* hevc_print(hevc, 0,
"%s cur_poc %d\n", __func__, cur_poc); */
for (ii = 0; ii < MAX_REF_PIC_NUM; ii++) {
pic = hevc->m_PIC[ii];
if (pic == NULL ||
@@ -3577,7 +3678,7 @@ static void hevc_init_decoder_hw(struct hevc_state_s *hevc,
unsigned int data32;
int i;
#if 0
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
/* Set MCR fetch priorities*/
data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
(24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
@@ -4261,8 +4362,12 @@ static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
/* DBLK CONFIG HERE */
if (hevc->new_pic) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
data32 = (0x57 << 8) | /* 1st/2nd write both enable*/
(0x0 << 0); /* h265 video format*/
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
data32 = (0xff << 8) | (0x0 << 0);
else
data32 = (0x57 << 8) | /* 1st/2nd write both enable*/
(0x0 << 0); /* h265 video format*/
if (hevc->pic_w >= 1280)
data32 |= (0x1 << 4); /*dblk pipeline mode=1 for performance*/
data32 &= (~0x300); /*[8]:first write enable (compress) [9]:double write enable (uncompress)*/
@@ -4307,7 +4412,7 @@ static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
"[DBLK DEBUG] HEVC1 STS1 : 0x%x\n",
data32);
/*}*/
}
}
}
#if 0
data32 = READ_VREG(HEVC_SAO_CTRL1);
@@ -5224,7 +5329,7 @@ static int hevc_slice_segment_header_process(struct hevc_state_s *hevc,
#endif
}
if (OVER_SIZE(hevc->pic_w, hevc->pic_h)) {
if (is_oversize(hevc->pic_w, hevc->pic_h)) {
hevc_print(hevc, 0, "over size : %u x %u.\n",
hevc->pic_w, hevc->pic_h);
if ((!hevc->m_ins_flag) &&
@@ -5779,7 +5884,7 @@ static int H265_alloc_mmu(struct hevc_state_s *hevc, struct PIC_s *new_pic,
int bit_depth_10 = (bit_depth != 0x00);
int picture_size;
int cur_mmu_4k_number;
int ret;
int ret, max_frame_num;
picture_size = compute_losless_comp_body_size(hevc, new_pic->width,
new_pic->height, !bit_depth_10);
cur_mmu_4k_number = ((picture_size+(1<<12)-1) >> 12);
@@ -5791,7 +5896,11 @@ static int H265_alloc_mmu(struct hevc_state_s *hevc, struct PIC_s *new_pic,
decoder_mmu_box_free_idx(hevc->mmu_box, new_pic->index);
new_pic->scatter_alloc = 0;
}
if (cur_mmu_4k_number > MAX_FRAME_4K_NUM) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
max_frame_num = MAX_FRAME_8K_NUM;
else
max_frame_num = MAX_FRAME_4K_NUM;
if (cur_mmu_4k_number > max_frame_num) {
hevc_print(hevc, 0, "over max !! 0x%x width %d height %d\n",
cur_mmu_4k_number,
new_pic->width,
@@ -5865,7 +5974,7 @@ static void hevc_local_uninit(struct hevc_state_s *hevc)
if (hevc->mmu_enable && hevc->frame_mmu_map_addr) {
if (hevc->frame_mmu_map_phy_addr)
dma_free_coherent(amports_get_dma_device(),
FRAME_MMU_MAP_SIZE, hevc->frame_mmu_map_addr,
get_frame_mmu_map_size(), hevc->frame_mmu_map_addr,
hevc->frame_mmu_map_phy_addr);
hevc->frame_mmu_map_addr = NULL;
@@ -5883,17 +5992,18 @@ static int hevc_local_init(struct hevc_state_s *hevc)
memset(&hevc->param, 0, sizeof(union param_u));
cur_buf_info = &hevc->work_space_buf_store;
#ifdef SUPPORT_4K2K
if (vdec_is_support_4k())
memcpy(cur_buf_info, &amvh265_workbuff_spec[1], /* 4k */
sizeof(struct BuffInfo_s));
else
if (vdec_is_support_4k()) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
memcpy(cur_buf_info, &amvh265_workbuff_spec[2], /* 4k */
sizeof(struct BuffInfo_s));
else
memcpy(cur_buf_info, &amvh265_workbuff_spec[1], /* 4k */
sizeof(struct BuffInfo_s));
} else
memcpy(cur_buf_info, &amvh265_workbuff_spec[0], /* 1080p */
sizeof(struct BuffInfo_s));
#else
memcpy(cur_buf_info, &amvh265_workbuff_spec[0], /* 1080p work space */
sizeof(struct BuffInfo_s));
#endif
cur_buf_info->start_adr = hevc->buf_start;
init_buff_spec(hevc, cur_buf_info);
@@ -5969,13 +6079,13 @@ static int hevc_local_init(struct hevc_state_s *hevc)
if (hevc->mmu_enable) {
hevc->frame_mmu_map_addr =
dma_alloc_coherent(amports_get_dma_device(),
FRAME_MMU_MAP_SIZE,
get_frame_mmu_map_size(),
&hevc->frame_mmu_map_phy_addr, GFP_KERNEL);
if (hevc->frame_mmu_map_addr == NULL) {
pr_err("%s: failed to alloc count_buffer\n", __func__);
return -1;
}
memset(hevc->frame_mmu_map_addr, 0, FRAME_MMU_MAP_SIZE);
memset(hevc->frame_mmu_map_addr, 0, get_frame_mmu_map_size());
}
ret = 0;
return ret;
@@ -8390,7 +8500,7 @@ pic_done:
hevc->lcu_size_log2 = log2i(hevc->lcu_size);
if (hevc->pic_w == 0 || hevc->pic_h == 0
|| hevc->lcu_size == 0
|| OVER_SIZE(hevc->pic_w, hevc->pic_h)) {
|| is_oversize(hevc->pic_w, hevc->pic_h)) {
/* skip search next start code */
WRITE_VREG(HEVC_WAIT_FLAG, READ_VREG(HEVC_WAIT_FLAG)
& (~0x2));
@@ -9117,7 +9227,7 @@ static int vh265_local_init(struct hevc_state_s *hevc)
hevc->get_frame_dur = false;
hevc->frame_width = hevc->vh265_amstream_dec_info.width;
hevc->frame_height = hevc->vh265_amstream_dec_info.height;
if (OVER_SIZE(hevc->frame_width, hevc->frame_height)) {
if (is_oversize(hevc->frame_width, hevc->frame_height)) {
pr_info("over size : %u x %u.\n",
hevc->frame_width, hevc->frame_height);
hevc->fatal_error |= DECODER_FATAL_ERROR_SIZE_OVERFLOW;
@@ -10802,14 +10912,15 @@ static struct mconfig_node decoder_265_node;
static int __init amvdec_h265_driver_init_module(void)
{
struct BuffInfo_s *p_buf_info;
#ifdef SUPPORT_4K2K
if (vdec_is_support_4k())
p_buf_info = &amvh265_workbuff_spec[1];
else
if (vdec_is_support_4k()) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
p_buf_info = &amvh265_workbuff_spec[2];
else
p_buf_info = &amvh265_workbuff_spec[1];
} else
p_buf_info = &amvh265_workbuff_spec[0];
#else
p_buf_info = &amvh265_workbuff_spec[0];
#endif
init_buff_spec(NULL, p_buf_info);
work_buf_size =
(p_buf_info->end_adr - p_buf_info->start_adr

2
drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec.c
View File

@@ -3800,7 +3800,7 @@ static int vdec_probe(struct platform_device *pdev)
return r;
}
#if 0
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
r = vdec_request_threaded_irq(VDEC_IRQ_HEVC_BACK, NULL, NULL,
IRQF_ONESHOT, "vdec-hevc_back", NULL);
if (r < 0) {

2
drivers/amlogic/media_modules/frame_provider/decoder/utils/vdec_profile.c
View File

@@ -62,7 +62,7 @@ static u64 get_us_time_hw(void)
int offset = 0;
/* txlx, g12a isa register base is 0x3c00 */
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX)
if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_TXLX)
offset = 0x1600;
do {

253
drivers/amlogic/media_modules/frame_provider/decoder/vp9/vvp9.c
View File

@@ -56,7 +56,6 @@
#include "../../../common/chips/decoder_cpu_ver_info.h"
#define MIX_STREAM_SUPPORT
#define SUPPORT_4K2K
#include "vvp9.h"
@@ -132,11 +131,6 @@
#define MULTI_INSTANCE_SUPPORT
#define SUPPORT_10BIT
/* #define ERROR_HANDLE_DEBUG */
#if 0 /* MESON_CPU_TYPE == MESON_CPU_TYPE_MESON8B*/
#undef SUPPORT_4K2K
#else
#define SUPPORT_4K2K
#endif
#ifndef STAT_KTHREAD
#define STAT_KTHREAD 0x40
@@ -243,7 +237,7 @@ static u32 on_no_keyframe_skiped;
#define COUNT_BUF_SIZE (0x300 * 4 * 4)
/*compute_losless_comp_body_size(4096, 2304, 1) = 18874368(0x1200000)*/
#define MAX_FRAME_4K_NUM 0x1200
#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)
#define MAX_FRAME_8K_NUM (0x1200*4)
#define HEVC_ASSIST_MMU_MAP_ADDR 0x3009
@@ -295,7 +289,8 @@ struct MVBUF_s {
/* #undef BUFMGR_ONLY to enable hardware configuration */
/*#define TEST_WR_PTR_INC*/
#define WR_PTR_INC_NUM 128
/*#define WR_PTR_INC_NUM 128*/
#define WR_PTR_INC_NUM 1
#define SIMULATION
#define DOS_PROJECT
@@ -409,7 +404,22 @@ VP9 buffer management start
***************************************************/
#define MMU_COMPRESS_HEADER_SIZE 0x48000
#define MMU_COMPRESS_8K_HEADER_SIZE (0x48000*4)
static int vvp9_mmu_compress_header_size(void)
{
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
return (MMU_COMPRESS_8K_HEADER_SIZE);
return (MMU_COMPRESS_HEADER_SIZE);
}
/*#define FRAME_MMU_MAP_SIZE (MAX_FRAME_4K_NUM * 4)*/
static int vvp9_frame_mmu_map_size(void)
{
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
return (MAX_FRAME_8K_NUM * 4);
return (MAX_FRAME_4K_NUM * 4);
}
#define INVALID_IDX -1 /* Invalid buffer index.*/
@@ -1211,7 +1221,9 @@ static int setup_frame_size(
(" * 16-bits h read : %d (height : %d)\n", width, height);
WRITE_VREG(HEVC_PARSER_PICTURE_SIZE, (height << 16) | width);
#ifdef VP9_10B_HED_FB
WRITE_VREG(HEVC_ASSIST_PIC_SIZE_FB_READ, (height << 16) | width);
#endif
if (pbi->mmu_enable) {
ret = vp9_alloc_mmu(pbi,
cm->new_fb_idx,
@@ -1566,7 +1578,7 @@ static int get_double_write_ratio(struct VP9Decoder_s *pbi,
return ratio;
}
#define MAX_4K_NUM 0x1200
//#define MAX_4K_NUM 0x1200
int vp9_alloc_mmu(
struct VP9Decoder_s *pbi,
@@ -1578,7 +1590,7 @@ int vp9_alloc_mmu(
{
int bit_depth_10 = (bit_depth == VPX_BITS_10);
int picture_size;
int cur_mmu_4k_number;
int cur_mmu_4k_number, max_frame_num;
if (!pbi->mmu_box) {
pr_err("error no mmu box!\n");
return -1;
@@ -1591,7 +1603,13 @@ int vp9_alloc_mmu(
picture_size = compute_losless_comp_body_size(pic_width, pic_height,
bit_depth_10);
cur_mmu_4k_number = ((picture_size + (1 << 12) - 1) >> 12);
if (cur_mmu_4k_number > MAX_4K_NUM) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
max_frame_num = MAX_FRAME_8K_NUM;
else
max_frame_num = MAX_FRAME_4K_NUM;
if (cur_mmu_4k_number > max_frame_num) {
pr_err("over max !! cur_mmu_4k_number 0x%x width %d height %d\n",
cur_mmu_4k_number, pic_width, pic_height);
return -1;
@@ -1672,13 +1690,16 @@ static int init_mv_buf_list(struct VP9Decoder_s *pbi)
int size = ((lcu_total * MV_MEM_UNIT) + 0xffff) &
(~0xffff);
#ifndef MV_USE_FIXED_BUF
if (pbi->init_pic_w >= 3840 && pbi->init_pic_h >= 2160)
count = REF_FRAMES_4K;
else if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
count = REF_FRAMES_2K;
else
#endif
count = REF_FRAMES;
count += pbi->dec_buf_margin;
if (debug) {
pr_info("%s w:%d, h:%d, count: %d\n",
__func__, pbi->init_pic_w, pbi->init_pic_h, count);
@@ -2692,18 +2713,11 @@ static u32 decode_pic_begin;
static uint slice_parse_begin;
static u32 step;
#ifdef MIX_STREAM_SUPPORT
#ifdef SUPPORT_4K2K
static u32 buf_alloc_width = 4096;
static u32 buf_alloc_height = 2304;
static u32 vp9_max_pic_w = 4096;
static u32 vp9_max_pic_h = 2304;
#else
static u32 buf_alloc_width = 1920;
static u32 buf_alloc_height = 1088;
static u32 vp9_max_pic_w = 1920;
static u32 vp9_max_pic_h = 1088;
#endif
static u32 dynamic_buf_num_margin;
#else
static u32 buf_alloc_width;
@@ -2836,7 +2850,7 @@ static struct device *cma_dev;
#endif
#define LMEM_BUF_SIZE (0x400 * 2)
#define WORK_BUF_SPEC_NUM 2
#define WORK_BUF_SPEC_NUM 3
static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
{
/* 8M bytes */
@@ -3042,6 +3056,78 @@ static struct BuffInfo_s amvvp9_workbuff_spec[WORK_BUF_SPEC_NUM] = {
.lmem = {
.buf_size = 0x400 * 2,
}
},
{
.max_width = 4096*2,
.max_height = 2304*2,
.ipp = {
// IPP work space calculation : 4096 * (Y+CbCr+Flags) = 12k, round to 16k
.buf_size = 0x4000*2,
},
.sao_abv = {
.buf_size = 0x30000*2,
},
.sao_vb = {
.buf_size = 0x30000*2,
},
.short_term_rps = {
// SHORT_TERM_RPS - Max 64 set, 16 entry every set, total 64x16x2 = 2048 bytes (0x800)
.buf_size = 0x800,
},
.vps = {
// VPS STORE AREA - Max 16 VPS, each has 0x80 bytes, total 0x0800 bytes
.buf_size = 0x800,
},
.sps = {
// SPS STORE AREA - Max 16 SPS, each has 0x80 bytes, total 0x0800 bytes
.buf_size = 0x800,
},
.pps = {
// PPS STORE AREA - Max 64 PPS, each has 0x80 bytes, total 0x2000 bytes
.buf_size = 0x2000,
},
.sao_up = {
// SAO UP STORE AREA - Max 640(10240/16) LCU, each has 16 bytes total 0x2800 bytes
.buf_size = 0x2800*2,
},
.swap_buf = {
// 256cyclex64bit = 2K bytes 0x800 (only 144 cycles valid)
.buf_size = 0x800,
},
.swap_buf2 = {
.buf_size = 0x800,
},
.scalelut = {
// support up to 32 SCALELUT 1024x32 = 32Kbytes (0x8000)
.buf_size = 0x8000*2,
},
.dblk_para = {
// DBLK -> Max 256(4096/16) LCU, each para 1024bytes(total:0x40000), data 1024bytes(total:0x40000)
.buf_size = 0x80000*2,
},
.dblk_data = {
.buf_size = 0x80000*2,
},
.mmu_vbh = {
.buf_size = 0x5000*2, //2*16*(more than 2304)/4, 4K
},
.cm_header = {
//.buf_size = MMU_COMPRESS_HEADER_SIZE*8, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
.buf_size = MMU_COMPRESS_HEADER_SIZE*16, // 0x44000 = ((1088*2*1024*4)/32/4)*(32/8)
},
.mpred_above = {
.buf_size = 0x10000*2, /* 2 * size of hevc*/
},
#ifdef MV_USE_FIXED_BUF
.mpred_mv = {
//4k2k , 0x100000 per buffer */
/* 4096x2304 , 0x120000 per buffer */
.buf_size = 0x120000 * 16 * 4,
},
#endif
.rpm = {
.buf_size = 0x80*2,
}
}
};
@@ -4587,13 +4673,16 @@ static void init_pic_list(struct VP9Decoder_s *pbi)
int i;
struct VP9_Common_s *cm = &pbi->common;
struct PIC_BUFFER_CONFIG_s *pic_config;
u32 header_size;
if (pbi->mmu_enable) {
header_size = vvp9_mmu_compress_header_size();
/*alloc VP9 compress header first*/
for (i = 0; i < pbi->used_buf_num; i++) {
unsigned long buf_addr;
if (decoder_bmmu_box_alloc_buf_phy
(pbi->bmmu_box,
HEADER_BUFFER_IDX(i), MMU_COMPRESS_HEADER_SIZE,
HEADER_BUFFER_IDX(i), header_size,
DRIVER_HEADER_NAME,
&buf_addr) < 0) {
pr_info("%s malloc compress header failed %d\n",
@@ -4760,7 +4849,8 @@ static int config_pic_size(struct VP9Decoder_s *pbi, unsigned short bit_depth)
else
WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (1 << 3));
}
WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TL1)
WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, (losless_comp_body_size >> 5));
/*WRITE_VREG(HEVCD_MPP_DECOMP_CTL3,(0xff<<20) | (0xff<<10) | 0xff);*/
WRITE_VREG(HEVC_CM_BODY_LENGTH, losless_comp_body_size);
WRITE_VREG(HEVC_CM_HEADER_OFFSET, losless_comp_body_size);
@@ -5112,11 +5202,21 @@ static void vp9_config_work_space_hw(struct VP9Decoder_s *pbi, u32 mask)
/* cfg_d_addr */
WRITE_VREG(HEVC_DBLK_CFG5, buf_spec->dblk_data.buf_start);
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
/*
* data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>8) & 0xff; // xio left offset, default is 0x40
* data32 = data32 * 2;
* data32 = (READ_VREG(P_HEVC_DBLK_CFG3)>>16) & 0xff; // adp left offset, default is 0x040
* data32 = data32 * 2;
*/
WRITE_VREG(HEVC_DBLK_CFG3, 0x808010); // make left storage 2 x 4k]
}
#ifdef LOSLESS_COMPRESS_MODE
if (pbi->mmu_enable) {
/*bit[4] : paged_mem_mode*/
WRITE_VREG(HEVCD_MPP_DECOMP_CTL1, (0x1 << 4));
WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_TL1)
WRITE_VREG(HEVCD_MPP_DECOMP_CTL2, 0);
} else {
/*if(cur_pic_config->bit_depth == VPX_BITS_10)
* WRITE_VREG(P_HEVCD_MPP_DECOMP_CTL1, (0<<3));
@@ -5301,6 +5401,7 @@ void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
struct loopfilter *lf = pbi->lf;
struct segmentation *seg_4lf = pbi->seg_4lf;
int i;
unsigned int data32;
memset(lfi, 0, sizeof(struct loop_filter_info_n));
memset(lf, 0, sizeof(struct loopfilter));
@@ -5326,16 +5427,21 @@ void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
}
/*video format is VP9*/
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
unsigned int data32;
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
data32 = (0x3 << 14) | // (dw fifo thres r and b)
(0x3 << 12) | // (dw fifo thres r or b)
(0x3 << 10) | // (dw fifo thres not r/b)
(0x3 << 8) | // 1st/2nd write both enable
(0x1 << 0); // vp9 video format
} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
data32 = (0x57 << 8) | /*1st/2nd write both enable*/
(0x1 << 0); /*vp9 video format*/
WRITE_VREG(HEVC_DBLK_CFGB, data32);
if (debug & VP9_DEBUG_BUFMGR_MORE)
pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
(0x1 << 0); /*vp9 video format*/
} else
WRITE_VREG(HEVC_DBLK_CFGB, 0x40400001);
data32 = 0x40400001;
WRITE_VREG(HEVC_DBLK_CFGB, data32);
if (debug & VP9_DEBUG_BUFMGR_MORE)
pr_info("[DBLK DEBUG] CFGB : 0x%x\n", data32);
}
/* perform this function per frame*/
void vp9_loop_filter_frame_init(struct segmentation *seg,
@@ -5461,7 +5567,7 @@ static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
0x7C00
};
#if 0
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
/* Set MCR fetch priorities*/
data32 = 0x1 | (0x1 << 2) | (0x1 <<3) |
(24 << 4) | (32 << 11) | (24 << 18) | (32 << 25);
@@ -5681,11 +5787,11 @@ static void config_mcrcc_axi_hw(struct VP9Decoder_s *pbi)
return;
}
#if 0
mcrcc_get_hitrate();
decomp_get_hitrate();
decomp_get_comprate();
#endif
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
mcrcc_get_hitrate(pbi->m_ins_flag);
decomp_get_hitrate();
decomp_get_comprate();
}
WRITE_VREG(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
(0 << 8) | (1 << 1) | 0);
@@ -5931,10 +6037,11 @@ static void vp9_local_uninit(struct VP9Decoder_s *pbi)
pbi->count_buffer_addr = NULL;
}
if (pbi->mmu_enable) {
u32 mmu_map_size = vvp9_frame_mmu_map_size();
if (pbi->frame_mmu_map_addr) {
if (pbi->frame_mmu_map_phy_addr)
dma_free_coherent(amports_get_dma_device(),
FRAME_MMU_MAP_SIZE,
mmu_map_size,
pbi->frame_mmu_map_addr,
pbi->frame_mmu_map_phy_addr);
pbi->frame_mmu_map_addr = NULL;
@@ -5972,31 +6079,32 @@ static int vp9_local_init(struct VP9Decoder_s *pbi)
memset(&pbi->common, 0, sizeof(struct VP9_Common_s));
#ifdef MULTI_INSTANCE_SUPPORT
cur_buf_info = &pbi->work_space_buf_store;
#ifdef SUPPORT_4K2K
if (vdec_is_support_4k())
memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
sizeof(struct BuffInfo_s));
else
if (vdec_is_support_4k()) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
memcpy(cur_buf_info, &amvvp9_workbuff_spec[2], /* 4k */
sizeof(struct BuffInfo_s));
} else
memcpy(cur_buf_info, &amvvp9_workbuff_spec[1], /* 4k */
sizeof(struct BuffInfo_s));
} else
memcpy(cur_buf_info, &amvvp9_workbuff_spec[0],/* 1080p */
sizeof(struct BuffInfo_s));
#else
memcpy(cur_buf_info, &amvvp9_workbuff_spec[0], /* 1080p work space */
sizeof(struct BuffInfo_s));
#endif
cur_buf_info->start_adr = pbi->buf_start;
if (!pbi->mmu_enable)
pbi->mc_buf_spec.buf_end = pbi->buf_start + pbi->buf_size;
#else
/*! MULTI_INSTANCE_SUPPORT*/
#ifdef SUPPORT_4K2K
if (vdec_is_support_4k())
cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
else
if (vdec_is_support_4k()) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
cur_buf_info = &amvvp9_workbuff_spec[2];/* 8k work space */
else
cur_buf_info = &amvvp9_workbuff_spec[1];/* 4k2k work space */
} else
cur_buf_info = &amvvp9_workbuff_spec[0];/* 1080p work space */
#else
cur_buf_info = &amvvp9_workbuff_spec[0]; /* 1080p work space */
#endif
#endif
init_buff_spec(pbi, cur_buf_info);
@@ -6010,6 +6118,11 @@ static int vp9_local_init(struct VP9Decoder_s *pbi)
pbi->max_pic_w = 1920;
pbi->max_pic_h = 1088;
}
} else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
buf_alloc_width = 8192;
buf_alloc_height = 4608;
pbi->max_pic_w = 8192;
pbi->max_pic_h = 4068;
}
pbi->init_pic_w = pbi->max_pic_w ? pbi->max_pic_w :
(buf_alloc_width ? buf_alloc_width :
@@ -6122,9 +6235,10 @@ static int vp9_local_init(struct VP9Decoder_s *pbi)
}
*/
if (pbi->mmu_enable) {
u32 mmu_map_size = vvp9_frame_mmu_map_size();
pbi->frame_mmu_map_addr =
dma_alloc_coherent(amports_get_dma_device(),
FRAME_MMU_MAP_SIZE,
mmu_map_size,
&pbi->frame_mmu_map_phy_addr, GFP_KERNEL);
if (pbi->frame_mmu_map_addr == NULL) {
pr_err("%s: failed to alloc count_buffer\n", __func__);
@@ -6132,7 +6246,7 @@ static int vp9_local_init(struct VP9Decoder_s *pbi)
}
memset(pbi->frame_mmu_map_addr, 0, COUNT_BUF_SIZE);
/* pbi->frame_mmu_map_phy_addr = dma_map_single(amports_get_dma_device(),
pbi->frame_mmu_map_addr, FRAME_MMU_MAP_SIZE, DMA_BIDIRECTIONAL);
pbi->frame_mmu_map_addr, mmu_map_size, DMA_BIDIRECTIONAL);
if (dma_mapping_error(amports_get_dma_device(),
pbi->frame_mmu_map_phy_addr)) {
pr_err("%s: failed to map count_buffer\n", __func__);
@@ -8154,6 +8268,11 @@ static int amvdec_vp9_probe(struct platform_device *pdev)
memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
pbi->init_flag = 0;
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
vp9_max_pic_w = 8192;
vp9_max_pic_h = 4608;
pr_info("%s tl1 force vp9 max resolution 8192*4608\n", __func__);
}
pbi->max_pic_w = vp9_max_pic_w;
pbi->max_pic_h = vp9_max_pic_h;
@@ -9125,6 +9244,11 @@ static int ammvdec_vp9_probe(struct platform_device *pdev)
&config_val) == 0) {
pbi->max_pic_h = config_val;
}
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1) {
pbi->max_pic_w = 8192;
pbi->max_pic_h = 4608;
pr_info("%s tl1 force vp9 max resolution 8192*4608\n", __func__);
}
#endif
if (get_config_int(pdata->config, "HDRStaticInfo",
&vf_dp.present_flag) == 0
@@ -9327,14 +9451,15 @@ static int __init amvdec_vp9_driver_init_module(void)
{
struct BuffInfo_s *p_buf_info;
#ifdef SUPPORT_4K2K
if (vdec_is_support_4k())
p_buf_info = &amvvp9_workbuff_spec[1];
else
if (vdec_is_support_4k()) {
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TL1)
p_buf_info = &amvvp9_workbuff_spec[2];
else
p_buf_info = &amvvp9_workbuff_spec[1];
} else
p_buf_info = &amvvp9_workbuff_spec[0];
#else
p_buf_info = &amvvp9_workbuff_spec[0];
#endif
init_buff_spec(NULL, p_buf_info);
work_buf_size =
(p_buf_info->end_adr - p_buf_info->start_adr
@@ -9364,7 +9489,7 @@ static int __init amvdec_vp9_driver_init_module(void)
}
if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_GXL
/*&& get_cpu_type() != MESON_CPU_MAJOR_ID_GXLX*/) {
/*&& get_cpu_major_id() != MESON_CPU_MAJOR_ID_GXLX*/) {
if (vdec_is_support_4k())
amvdec_vp9_profile.profile =
"4k, 10bit, dwrite, compressed";

BIN
firmware/video/video_ucode.bin Executable file → Normal file
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