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UPSTREAM: clk: rockchip: rk3368: fix hdmi_cec gate-register

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Fix a typo making the sclk_hdmi_cec access a wrong register to handle
its gate.

Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.6-clk/next
 commit fd0c0740fa)

Change-Id: I549ef7e3c29df9fe7d4280288639e401727a001e
This commit is contained in:
Heiko Stuebner
2016-01-20 21:47:57 +01:00
committed by Gerrit Code Review
parent cb438027f7
commit 24ebcaf1c0
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3368.c
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@@ -442,7 +442,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
RK3368_CLKGATE_CON(4), 13, GFLAGS),
GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
RK3368_CLKGATE_CON(5), 12, GFLAGS),
RK3368_CLKGATE_CON(4), 12, GFLAGS),
COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,