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ARM: dts: rockchip: rv1103: Change CLK_339M_SRC to 264MHz

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ISP's parents are CLK_339M_SRC and CLK_200M_SRC, 4M/30fps requires
264M for better power and performance. But it can only get 200M as
CLK_200M_SRC is the closest clk src than CLK_339M_SRC.

CLK_339M_SRC only outputs for ISP and VICAP modules, it's fine to
change CLK_339M_SRC to 264MHz.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I9d349ec7e1dc29f2f6ecdda954a6c0419b9b7d89
This commit is contained in:
Finley Xiao
2022-05-24 18:27:03 +08:00
committed by Tao Huang
parent 4e9a347fc0
commit 24f9c771cc
1 changed files with 17 additions and 0 deletions
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17
arch/arm/boot/dts/rv1103.dtsi
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@@ -21,6 +21,23 @@
/delete-node/ opp-1608000000;
};
&cru {
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ARMCLK>,
<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
<&cru HCLK_PMU_ROOT>, <&cru CLK_339M_SRC>;
assigned-clock-rates =
<1188000000>, <1000000000>,
<1104000000>,
<400000000>, <200000000>,
<100000000>, <300000000>,
<100000000>, <100000000>,
<200000000>, <264000000>;
};
&u2phy_otg {
rockchip,vbus-always-on;
};